x86: Support platform PIRQ routing
On x86 boards, platform chipset receives up to four different interrupt signals from PCI devices (INTA/B/C/D), which in turn will be routed to chipset internal PIRQ lines then routed to 8259 PIC finally if configuring the whole system to work under the so-called PIC mode (in contrast to symmetric IO mode which uses IOAPIC). We add two major APIs to aid this, one for routing PIRQ and the other one for generating a PIRQ routing table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng
Simon Glass
parent
5e2400e8f8
commit
b5b6b01960
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@ -442,6 +442,37 @@ config TSC_FREQ_IN_MHZ
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help
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The running frequency in MHz of Time-Stamp Counter (TSC).
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menu "System tables"
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config GENERATE_PIRQ_TABLE
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bool "Generate a PIRQ table"
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default n
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help
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Generate a PIRQ routing table for this board. The PIRQ routing table
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is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
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at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
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It specifies the interrupt router information as well how all the PCI
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devices' interrupt pins are wired to PIRQs.
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endmenu
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config MAX_PIRQ_LINKS
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int
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default 8
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help
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This variable specifies the number of PIRQ interrupt links which are
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routable. On most older chipsets, this is 4, PIRQA through PIRQD.
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Some newer chipsets offer more than four links, commonly up to PIRQH.
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config IRQ_SLOT_COUNT
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int
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default 128
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help
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U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
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which in turns forms a table of exact 4KiB. The default value 128
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should be enough for most boards. If this does not fit your board,
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change it according to your needs.
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source "board/coreboot/coreboot/Kconfig"
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source "board/google/chromebook_link/Kconfig"
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@ -0,0 +1,139 @@
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* Ported from coreboot src/arch/x86/include/arch/pirq_routing.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _PIRQ_ROUTING_H_
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#define _PIRQ_ROUTING_H_
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/*
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* This is the maximum number on interrupt entries that a PCI device may have.
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* This is NOT the number of slots or devices in the system
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* This is NOT the number of entries in the PIRQ table
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*
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* This tells us that in the PIRQ table, we are going to have 4 link-bitmap
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* entries per PCI device which is fixed at 4: INTA, INTB, INTC, and INTD.
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*
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* CAUTION: If you change this, PIRQ routing will not work correctly.
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*/
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#define MAX_INTX_ENTRIES 4
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#define PIRQ_SIGNATURE \
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(('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24))
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#define PIRQ_VERSION 0x0100
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struct __packed irq_info {
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u8 bus; /* Bus number */
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u8 devfn; /* Device and function number */
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struct __packed {
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u8 link; /* IRQ line ID, 0=not routed */
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u16 bitmap; /* Available IRQs */
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} irq[MAX_INTX_ENTRIES];
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u8 slot; /* Slot number, 0=onboard */
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u8 rfu;
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};
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struct __packed irq_routing_table {
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u32 signature; /* PIRQ_SIGNATURE */
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u16 version; /* PIRQ_VERSION */
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u16 size; /* Table size in bytes */
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u8 rtr_bus; /* busno of the interrupt router */
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u8 rtr_devfn; /* devfn of the interrupt router */
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u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */
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u16 rtr_vendor; /* Vendor ID of the interrupt router */
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u16 rtr_device; /* Device ID of the interrupt router */
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u32 miniport_data;
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u8 rfu[11];
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u8 checksum; /* Modulo 256 checksum must give zero */
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struct irq_info slots[CONFIG_IRQ_SLOT_COUNT];
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};
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/**
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* get_irq_slot_count() - Get the number of entries in the irq_info table
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*
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* This calculates the number of entries for the irq_info table.
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*
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* @rt: pointer to the base address of the struct irq_info
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* @return: number of entries
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*/
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static inline int get_irq_slot_count(struct irq_routing_table *rt)
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{
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return (rt->size - 32) / sizeof(struct irq_info);
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}
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/**
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* pirq_check_irq_routed() - Check whether an IRQ is routed to 8259 PIC
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*
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* This function checks whether an IRQ is routed to 8259 PIC for a given link.
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*
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* Note: this function should be provided by the platform codes, as the
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* implementation of interrupt router may be different.
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*
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* @link: link number which represents a PIRQ
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* @irq: the 8259 IRQ number
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* @return: true if the irq is already routed to 8259 for a given link,
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* false elsewise
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*/
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bool pirq_check_irq_routed(int link, u8 irq);
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/**
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* pirq_translate_link() - Translate a link value
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*
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* This function translates a platform-specific link value to a link number.
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* On Intel platforms, the link value is normally a offset into the PCI
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* configuration space into the legacy bridge.
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*
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* Note: this function should be provided by the platform codes, as the
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* implementation of interrupt router may be different.
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*
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* @link: platform-specific link value
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* @return: link number which represents a PIRQ
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*/
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int pirq_translate_link(int link);
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/**
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* pirq_assign_irq() - Assign an IRQ to a PIRQ link
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*
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* This function assigns the IRQ to a PIRQ link so that the PIRQ is routed to
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* the 8259 PIC.
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*
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* Note: this function should be provided by the platform codes, as the
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* implementation of interrupt router may be different.
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*
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* @link: link number which represents a PIRQ
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* @irq: IRQ to which the PIRQ is routed
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*/
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void pirq_assign_irq(int link, u8 irq);
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/**
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* pirq_route_irqs() - Route PIRQs to 8259 PIC
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*
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* This function configures all PCI devices' interrupt pins and maps them to
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* PIRQs and finally 8259 PIC. The routed irq number is written to interrupt
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* line register in the configuration space of the PCI device for OS to use.
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* The configuration source is taken from a struct irq_info table, the format
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* of which is defined in PIRQ routing table spec and PCI BIOS spec.
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*
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* @irq: pointer to the base address of the struct irq_info
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* @num: number of entries in the struct irq_info
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*/
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void pirq_route_irqs(struct irq_info *irq, int num);
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/**
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* copy_pirq_routing_table() - Copy a PIRQ routing table
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*
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* This helper function copies the given PIRQ routing table to a given address.
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* Before copying, it does several sanity tests against the PIRQ routing table.
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* It also fixes up the table checksum and align the given address to a 16 byte
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* boundary to meet the PIRQ routing table spec requirements.
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*
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* @addr: address to store the copied PIRQ routing table
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* @rt: pointer to the PIRQ routing table to copy from
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* @return: end address of the copied PIRQ routing table
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*/
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u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt);
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#endif /* _PIRQ_ROUTING_H_ */
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@ -22,6 +22,7 @@ ifndef CONFIG_DM_PCI
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obj-$(CONFIG_PCI) += pci_type1.o
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endif
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obj-y += pch-uclass.o
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obj-y += pirq_routing.o
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obj-y += relocate.o
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obj-y += physmem.o
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obj-$(CONFIG_X86_RAMTEST) += ramtest.o
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@ -0,0 +1,129 @@
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* Part of this file is ported from coreboot src/arch/x86/boot/pirq_routing.c
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/pci.h>
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#include <asm/pirq_routing.h>
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#include <asm/tables.h>
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static bool irq_already_routed[16];
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static u8 pirq_get_next_free_irq(u8 *pirq, u16 bitmap)
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{
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int i, link;
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u8 irq = 0;
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/* IRQ sharing starts from IRQ#3 */
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for (i = 3; i < 16; i++) {
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/* Can we assign this IRQ? */
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if (!((bitmap >> i) & 1))
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continue;
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/* We can, now let's assume we can use this IRQ */
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irq = i;
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/* Have we already routed it? */
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if (irq_already_routed[irq])
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continue;
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for (link = 0; link < CONFIG_MAX_PIRQ_LINKS; link++) {
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if (pirq_check_irq_routed(link, irq)) {
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irq_already_routed[irq] = true;
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break;
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}
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}
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/* If it's not yet routed, use it */
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if (!irq_already_routed[irq]) {
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irq_already_routed[irq] = true;
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break;
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}
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/* But if it was already routed, try the next one */
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}
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/* Now we get our IRQ */
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return irq;
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}
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void pirq_route_irqs(struct irq_info *irq, int num)
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{
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unsigned char irq_slot[MAX_INTX_ENTRIES];
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unsigned char pirq[CONFIG_MAX_PIRQ_LINKS];
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int i, intx;
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memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS);
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/* Set PCI IRQs */
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for (i = 0; i < num; i++) {
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debug("PIRQ Entry %d Dev: %d.%x.%d\n", i,
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irq->bus, irq->devfn >> 3, irq->devfn & 7);
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for (intx = 0; intx < MAX_INTX_ENTRIES; intx++) {
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int link = irq->irq[intx].link;
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int bitmap = irq->irq[intx].bitmap;
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int irq = 0;
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debug("INT%c link: %x bitmap: %x ",
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'A' + intx, link, bitmap);
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if (!bitmap || !link) {
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debug("not routed\n");
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irq_slot[intx] = irq;
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continue;
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}
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/* translate link value to link number */
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link = pirq_translate_link(link);
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/* yet not routed */
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if (!pirq[link]) {
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irq = pirq_get_next_free_irq(pirq, bitmap);
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pirq[link] = irq;
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} else {
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irq = pirq[link];
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}
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debug("IRQ: %d\n", irq);
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irq_slot[intx] = irq;
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/* Assign IRQ in the interrupt router */
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pirq_assign_irq(link, irq);
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}
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/* Bus, device, slots IRQs for {A,B,C,D} */
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pci_assign_irqs(irq->bus, irq->devfn >> 3, irq->devfn & 7,
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irq_slot);
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irq++;
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}
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for (i = 0; i < CONFIG_MAX_PIRQ_LINKS; i++)
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debug("PIRQ%c: %d\n", 'A' + i, pirq[i]);
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}
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u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt)
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{
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if (rt->signature != PIRQ_SIGNATURE || rt->version != PIRQ_VERSION ||
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rt->size % 16) {
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debug("Interrupt Routing Table not valid\n");
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return addr;
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}
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/* Fix up the table checksum */
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rt->checksum = table_compute_checksum(rt, rt->size);
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/* Align the table to be 16 byte aligned */
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addr = ALIGN(addr, 16);
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debug("Copying Interrupt Routing Table to 0x%x\n", addr);
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memcpy((void *)addr, rt, rt->size);
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return addr + rt->size;
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}
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