Merge git://www.denx.de/git/u-boot
This commit is contained in:
commit
b721ff745d
84 changed files with 4031 additions and 1110 deletions
483
CHANGELOG
483
CHANGELOG
|
@ -1,9 +1,438 @@
|
|||
commit c440bfe6d6d92d66478a7e84402b31f48413617b
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Wed Jun 6 11:42:13 2007 +0200
|
||||
|
||||
ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval board
|
||||
|
||||
This patch adds NAND booting support for the AMCC Acadia eval board.
|
||||
|
||||
Please make sure to configure jumper J7 to position 2-3 when booting
|
||||
from NOR, and to position 1-2 when booting for NAND.
|
||||
|
||||
I also added a board command to configure the I2C bootstrap EEPROM
|
||||
values. Right now only 267MHz is support for booting either via NOR
|
||||
or NAND FLASH. Here the usage:
|
||||
|
||||
=> bootstrap 267 nor ;to configure the board for 267MHz NOR booting
|
||||
=> bootstrap 267 nand ;to configure the board for 267MHz NNAND booting
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 32922cdc470fdfd39bea0c1c4f582d3fb340421e
|
||||
Author: Ed Swarthout <Ed.Swarthout@freescale.com>
|
||||
Date: Tue Jun 5 12:30:52 2007 -0500
|
||||
|
||||
mpc8641 image size cleanup
|
||||
|
||||
e600 does not have a bootpg restriction.
|
||||
Move the version string to beginning of image at fff00000.
|
||||
Resetvec.S is not needed.
|
||||
Update flash copy instructions.
|
||||
Add tftpflash env variable
|
||||
|
||||
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
|
||||
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
||||
|
||||
commit e3cbe1f93c5722f8ebbad468e30c069a2b511097
|
||||
Author: Benoît Monin <bmonin@adeneo.eu>
|
||||
Date: Mon Jun 4 08:36:05 2007 +0200
|
||||
|
||||
[PATCH] Fix ppc4xx bootstrap letter displayed on startup
|
||||
|
||||
The attached patch is mainly cosmetic, allowing u-boot to
|
||||
display the correct bootstrap option letter according to the
|
||||
datasheets.
|
||||
|
||||
The original patch was extended with 405EZ support by Stefan
|
||||
Roese.
|
||||
|
||||
Signed-off-by: Benoit Monin <bmonin@adeneo.eu>
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 18d156eb37c90fadc8ec7a81a3b89176161f85b7
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Fri Jun 1 16:18:17 2007 +0200
|
||||
|
||||
ppc4xx: Add missing file for Bamboo NAND booting support
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 155a96478a0881e6da96cbbbcf34952d6a3b1b4b
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Fri Jun 1 15:58:19 2007 +0200
|
||||
|
||||
ppc4xx: Undo Sequoia patch for dynamic EBC speed support of 83MHz
|
||||
|
||||
This patch undoes the patch by Jeff Mann with commit-id ada4697d. As
|
||||
suggested by AMCC it is not recommended to dynamically change the EBC
|
||||
speed after bootup. So we undo this change to be on the safe side.
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 9d9096043e8f713d4bf1743d32e1459e6a11644b
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Fri Jun 1 15:29:04 2007 +0200
|
||||
|
||||
ppc4xx: Update Sequoia NAND booting support with ECC
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit cf959c7d6687567c308e366e9581e1a5aff5cc5b
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Fri Jun 1 15:27:11 2007 +0200
|
||||
|
||||
ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval board
|
||||
|
||||
This patch adds NAND booting support for the AMCC Bamboo eval board.
|
||||
Since the NAND-SPL boot image is limited to 4kbytes, this version
|
||||
only supports the onboard 64MBytes of DDR. The DIMM modules can't be
|
||||
supported, since the setup code for I2C DIMM autodetection and
|
||||
configuration is too big for this NAND bootloader.
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 42be56f53c8b107868e6125c8524ae84293e95a7
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Fri Jun 1 15:23:04 2007 +0200
|
||||
|
||||
NAND: Add ECC support to NAND booting support in nand_spl/nand_boot.c
|
||||
|
||||
The U-Boot NAND booting support is now extended to support ECC
|
||||
upon loading of the NAND U-Boot image.
|
||||
|
||||
Tested on AMCC Sequoia (440EPx) and Bamboo (440EP).
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit a471db07fbb65a841ffc9f4f112562b945230f98
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Fri Jun 1 15:19:29 2007 +0200
|
||||
|
||||
ppc4xx: Prepare Bamboo port for NAND booting support
|
||||
|
||||
This patch updates the "normal" Bamboo NOR booting port, so
|
||||
that it is compatible with the coming soon NAND booting
|
||||
Bamboo port.
|
||||
|
||||
It also enables the 2nd NAND flash on the Bamboo.
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 53ad02103fb8be4138a9937a8ab91fcdff7b4987
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Fri Jun 1 15:16:58 2007 +0200
|
||||
|
||||
ppc4xx: Update in_be32() functions and friends to latest Linux version
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 91da09cfbce0c1de05d6d84aa8363d666fa7ea3c
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Fri Jun 1 15:15:12 2007 +0200
|
||||
|
||||
NAND: Add hardware ECC support to the PPC4xx NAND driver ndfc.c
|
||||
|
||||
This patch adds hardware ECC support to the NDFC driver. It also
|
||||
changes the register access from using the "simple" in32/out32
|
||||
functions to the in_be32/out_be32 functions, which make sure
|
||||
that the access is correctly synced. This is the only recommended
|
||||
access to SoC registers in the current Linux kernel.
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 17b5e862287cca76f19dcf8b741e61a7d06617f2
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Fri Jun 1 15:12:15 2007 +0200
|
||||
|
||||
NAND: Update nand_ecc.c to latest Linux version
|
||||
|
||||
This patch updates the nand_ecc code to the latest Linux version.
|
||||
The main reason for this is the more compact code. This makes
|
||||
it possible to include the ECC code into the NAND bootloader
|
||||
image (NAND_SPL) for PPC4xx.
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit d2d432760d2199d0e8558fdd9d1789b8131abcf7
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Fri Jun 1 15:09:50 2007 +0200
|
||||
|
||||
ppc4xx: 44x DDR driver code cleanup and small fix for Bamboo
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit e4bbed2803a2ad0521c7362f5d3e065f99abaedc
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Fri Jun 1 13:45:24 2007 +0200
|
||||
|
||||
ppc4xx: Change Luan config file to support ECC
|
||||
|
||||
With the updated 44x DDR2 driver the Luan board now supports
|
||||
ECC generation and checking.
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 7187db73491c8de0fb56efb5e5134ba5ec443089
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Fri Jun 1 13:45:00 2007 +0200
|
||||
|
||||
ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)
|
||||
|
||||
Add config option for 180 degree advance clock control as needed
|
||||
for the AMCC Luan eval board.
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit ee1529838abbfaa35f14e3ffbeaaba693159475f
|
||||
Author: Wolfgang Denk <wd@denx.de>
|
||||
Date: Thu May 31 17:20:09 2007 +0200
|
||||
|
||||
Add support for STX GP3SSA (stxssa) Board with 4 MiB flash.
|
||||
|
||||
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
||||
|
||||
commit 7049288fb1f16f1b317140226cdebd07bd416395
|
||||
Author: Bartlomiej Sieka <tur@semihalf.com>
|
||||
Date: Sun May 27 17:26:46 2007 +0200
|
||||
|
||||
Motion-PRO: Code cleanup, fix of a typo in OF_STDOUT_PATH.
|
||||
|
||||
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
|
||||
|
||||
commit 4520fd4d2c450da49637216aa0e53739b61c60ac
|
||||
Author: Bartlomiej Sieka <tur@semihalf.com>
|
||||
Date: Sun May 27 17:06:36 2007 +0200
|
||||
|
||||
Motion-PRO: Add support for redundant environment.
|
||||
|
||||
Enable redundant environment, add a MTD partition for it; also add env.
|
||||
variable command for passing MTD partitions to the kernel command line.
|
||||
|
||||
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
|
||||
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
|
||||
|
||||
commit a26eabeec31746f06d309103690892805696e344
|
||||
Author: Bartlomiej Sieka <tur@semihalf.com>
|
||||
Date: Sun May 27 17:05:11 2007 +0200
|
||||
|
||||
Motion-PRO: Change maximum console buffer size from 256 to 1024 bytes.
|
||||
|
||||
Allow passing longer command line to the kernel - useful especially
|
||||
for passing MTD partition layout.
|
||||
|
||||
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
|
||||
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
|
||||
|
||||
commit 9160b96f71483a116de81c68985e8ee306d36764
|
||||
Author: Bartlomiej Sieka <tur@semihalf.com>
|
||||
Date: Sun May 27 17:04:18 2007 +0200
|
||||
|
||||
Fix: Add missing NULL termination in strings expanded by macros parser.
|
||||
|
||||
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
|
||||
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
|
||||
|
||||
commit 630ec84aef7228fc1dbfb38dec78541403a786cd
|
||||
Author: Bartlomiej Sieka <tur@semihalf.com>
|
||||
Date: Sun May 27 17:03:37 2007 +0200
|
||||
|
||||
Motion-PRO: Update EEPROM's page write bits and write delay.
|
||||
|
||||
Change EEPROM configuration according to the datasheet: "The 24C01A and 24C02A
|
||||
have a page write capability of two bytes", and "This device offers fast (1ms)
|
||||
byte write". Add 3ms of extra delay.
|
||||
|
||||
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
|
||||
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
|
||||
|
||||
commit c00125e07c1ebc125bab40e1e18bceed8be0c162
|
||||
Author: Bartlomiej Sieka <tur@semihalf.com>
|
||||
Date: Sun May 27 16:58:45 2007 +0200
|
||||
|
||||
MPC5XXX, Motion-PRO: Fix PHY initialization problem.
|
||||
|
||||
After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which
|
||||
networking does not function. This commit switches PHY to TX mode by clearing
|
||||
the FX_SEL bit of Mode Control Register. It also reverses commit
|
||||
008861a2f3ef2c062744d733787c7e530a1b8761, i.e., a temporary workaround.
|
||||
|
||||
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
|
||||
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
|
||||
|
||||
commit 93b78f534a6e708b4cf1a4ffb4d8438c67a007db
|
||||
Author: Bartlomiej Sieka <tur@semihalf.com>
|
||||
Date: Sun May 27 16:57:15 2007 +0200
|
||||
|
||||
Motion-PRO: Add support for the temperature sensor.
|
||||
|
||||
Signed-off-by: Piotr Kruszynski <ppk@semihalf.com>
|
||||
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
|
||||
|
||||
commit c75e639630cc132dc19cd1ecda5922c0db0bfbba
|
||||
Author: Bartlomiej Sieka <tur@semihalf.com>
|
||||
Date: Sun May 27 16:55:23 2007 +0200
|
||||
|
||||
Motion-PRO: Add displaying of CPLD revision information during boot.
|
||||
|
||||
Signed-off-by: Jan Wrobel <wrr@semihalf.com>
|
||||
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
|
||||
|
||||
commit c99512d6bd3973f01ca2fc4896d829b46e68f150
|
||||
Author: Bartlomiej Sieka <tur@semihalf.com>
|
||||
Date: Sun May 27 16:53:43 2007 +0200
|
||||
|
||||
MPC5xxx: Change names of defines related to IPB and PCI clocks.
|
||||
|
||||
Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining
|
||||
them does not cause PCI or IPB clocks to run at the specified speed.
|
||||
Instead, they configure divisors used to calculate said clocks. This
|
||||
patch renames the defines according to their real function.
|
||||
|
||||
Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
|
||||
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
|
||||
|
||||
commit a11c0b85dc3664bb3c1e781137118730c8f619ab
|
||||
Author: Bartlomiej Sieka <tur@semihalf.com>
|
||||
Date: Sun May 27 16:51:48 2007 +0200
|
||||
|
||||
Motion-PRO: Add LED support.
|
||||
|
||||
Signed-off-by: Jan Wrobel <wrr@semihalf.com>
|
||||
Signed-off-by: Marian Balakowicz <m8@semihalf.com>
|
||||
Acked-by: Bartlomiej Sieka <tur@semihalf.com>
|
||||
|
||||
commit d756894722c888d09a9fa1df8323753772d3dcce
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Thu May 24 09:49:00 2007 +0200
|
||||
|
||||
ppc4xx: Fix small 405EZ OCM initilization bug in start.S
|
||||
|
||||
As pointed out by Bruce Adler <bruce.adler@acm.org> this patch
|
||||
fixes a small bug in the 405EZ OCM initialization. Thanks for
|
||||
spotting.
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 5d4a179013d59a76446462e1eb0a969fba63eb81
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Thu May 24 08:22:09 2007 +0200
|
||||
|
||||
ppc4xx: Update AMCC Acadia support for board revision 1.1
|
||||
|
||||
This patch updates the Acadia (405EZ) support for the new 1.1 board
|
||||
revision. It also adds support for NAND FLASH via the 4xx NDFC.
|
||||
|
||||
Please note that the jumper J7 must be in position 2-3 for this
|
||||
NAND support. Position 1-2 is for NAND booting only. NAND booting
|
||||
support will follow later.
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 9f0077abd69f7a7c756a915b961037302be3e6f2
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Tue May 22 12:48:09 2007 +0200
|
||||
|
||||
ppc4xx: Use do { ... } while (0) for CPR & SDR access macros
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 6f3dfc139a838b0841c151efe00ad47db2366e79
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Tue May 22 12:46:10 2007 +0200
|
||||
|
||||
ppc4xx: Add 405 support to 4xx NAND driver ndfc.c
|
||||
|
||||
This patch adds support for 405 PPC's to the 4xx NAND driver
|
||||
ndfc.c. This is in preparation for the new AMCC 405EZ.
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 10603d76767426be803dadd4fb688b97eb69481c
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Mon May 21 07:41:22 2007 +0200
|
||||
|
||||
ppc4xx: Fix problem in 405EZ OCM initialization
|
||||
|
||||
As spotted by Bruce Adler this patch fixes an initialization problem
|
||||
for the 405EZ OCM.
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 3e3b956906eba9e4ad7931581ecedaad10eccce8
|
||||
Author: Peter Pearse <peter.pearse@arm.com>
|
||||
Date: Fri May 18 16:47:03 2007 +0100
|
||||
|
||||
Reduce line lengths to 80 characters max.
|
||||
|
||||
commit 93ef45c9ddfdd9fc17c4e74bd8e2f2456580eb72
|
||||
Author: Peter Pearse <peter.pearse@arm.com>
|
||||
Date: Fri May 18 14:34:07 2007 +0100
|
||||
|
||||
Makefile permissions
|
||||
|
||||
commit 1443a31457d68f7e8f0b9403e9832ec1e79dc59d
|
||||
Author: Peter Pearse <peter.pearse@arm.com>
|
||||
Date: Fri May 18 14:33:11 2007 +0100
|
||||
|
||||
Makefile permissions
|
||||
|
||||
commit 70124c2602ae2d4c5d3dba05b482d91548242de8
|
||||
Author: Stefano Babic <sbabic@denx.de>
|
||||
Date: Wed May 16 14:49:12 2007 +0200
|
||||
|
||||
Fix compile problem cause my Microblaze merge
|
||||
|
||||
Signed-off-by: Stefano Babic <sbabic@denx.de>
|
||||
|
||||
commit ada4697d0230d6da552867777f98a67ec3ba2579
|
||||
Author: Jeffrey Mann <mannj@embeddedplanet.com>
|
||||
Date: Wed May 16 13:23:10 2007 +0200
|
||||
|
||||
[PATCH] Run new sequoia boards with an EBC speed of 83MHz
|
||||
|
||||
Because the Sequoia board does not boot with an EBC faster than 66MHz,
|
||||
the clock divider are changed after the initial boot process.
|
||||
|
||||
This allows for maximum clocking speeds to be achieved on newer boards.
|
||||
Sequoia boards with 666.66 MHz processors require that the EBC divider
|
||||
be set to 3 in order to start the initial boot process at a slower EBC
|
||||
speed. After the initial boot process, the divider can be set back to 2,
|
||||
which will cause the boards to run at 83.333MHz. This is backward
|
||||
compatible with boards with 533.33 MHz processors, as these boards will
|
||||
already be set with an EBC divider of 2.
|
||||
|
||||
Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
|
||||
|
||||
commit a7676ea7732f3c596805079fed7e5c9fac652cfc
|
||||
Author: Wolfgang Denk <wd@denx.de>
|
||||
Date: Wed May 16 01:16:53 2007 +0200
|
||||
|
||||
Minor Coding Style cleanup, update CHANGELOG.
|
||||
|
||||
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
||||
|
||||
commit d62f64cc23a940eafe712c776b3249e4160753d1
|
||||
Author: Wolfgang Denk <wd@denx.de>
|
||||
Date: Wed May 16 00:13:33 2007 +0200
|
||||
|
||||
Coding Style Cleanup, new CHANGELOG
|
||||
|
||||
commit 61936667e86a250ae12fd2dc189d3588f0a59e0b
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Fri May 11 12:01:49 2007 +0200
|
||||
|
||||
ppc4xx: Add mtcpr/mfcpr access macros
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 343c48bd84606c4025c8a7c7263fda465d6e284c
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Fri May 11 12:01:06 2007 +0200
|
||||
|
||||
ppc4xx: Set bd->bi_pci_busfreq on 440EPx/GRx too
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 7d98ba770a7eaefa29ce927f31a0956df85bf650
|
||||
Author: Piotr Kruszynski <ppk@semihalf.com>
|
||||
Date: Thu May 10 16:55:52 2007 +0200
|
||||
|
@ -11,6 +440,48 @@ Date: Thu May 10 16:55:52 2007 +0200
|
|||
[Motion-PRO] Add MTD and JFFS2 support, also add default partition
|
||||
definition.
|
||||
|
||||
commit 65fb6a676e821f9570a2a376dc204bf611ce5f81
|
||||
Author: Peter Pearse <peter.pearse@arm.com>
|
||||
Date: Wed May 9 11:42:44 2007 +0100
|
||||
|
||||
Add the board directory for SMN42
|
||||
|
||||
commit 160131bf965785419626df6c388729fe0b597992
|
||||
Author: Peter Pearse <peter.pearse@arm.com>
|
||||
Date: Wed May 9 11:41:58 2007 +0100
|
||||
|
||||
Add the files for the SMN42 board
|
||||
|
||||
commit 5c6d2b5a500f8c49670de8910150b78a41f781fc
|
||||
Author: Peter Pearse <peter.pearse@arm.com>
|
||||
Date: Wed May 9 11:40:34 2007 +0100
|
||||
|
||||
Remove the deleted files for the SMN42 patch
|
||||
|
||||
commit b0d8f5bf0d215adc9424cb228b2484dbf07f7761
|
||||
Author: Peter Pearse <peter.pearse@arm.com>
|
||||
Date: Wed May 9 11:37:56 2007 +0100
|
||||
|
||||
New board SMN42 branch
|
||||
|
||||
commit 29f3be0caf0799ca6b89dfd9824c15619a50000f
|
||||
Author: Peter Pearse <peter.pearse@arm.com>
|
||||
Date: Wed May 9 10:24:38 2007 +0100
|
||||
|
||||
Makefile permissions
|
||||
|
||||
commit b84289b595731e8851df46e893845cc1322c9b9b
|
||||
Author: Ed Swarthout <Ed.Swarthout@freescale.com>
|
||||
Date: Tue May 8 14:17:07 2007 -0500
|
||||
|
||||
8641hpcn: Fix Makefile after moving pixis to board/freescale.
|
||||
|
||||
The OBJTREE != SRCTREE build scenario was broken.
|
||||
This fixes it.
|
||||
|
||||
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
|
||||
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
||||
|
||||
commit e69f66c6ebe82bbbd1da766bc4eda40ec7ee5af1
|
||||
Author: Michal Simek <monstr@monstr.eu>
|
||||
Date: Tue May 8 15:57:43 2007 +0200
|
||||
|
@ -93,6 +564,18 @@ Date: Mon May 7 19:43:10 2007 +0200
|
|||
|
||||
fix: read and write MSR - repair number of parameters
|
||||
|
||||
commit 193b4a3bb3acaddf798da8de0da05d94ba8774ee
|
||||
Author: Jeffrey Mann <mannj@embeddedplanet.com>
|
||||
Date: Mon May 7 19:42:49 2007 +0200
|
||||
|
||||
[PATCH] ppc4xx: Fix CONFIG_SYS_CLK_FREQ definition in Sequoia config file
|
||||
|
||||
A '3' got cut off in the formatting of the last patch to automatically
|
||||
change the clock speed of the system clock on sequoia board.
|
||||
|
||||
Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 19bf1fbad7f19d5a120be9b1daf136e052fcab39
|
||||
Author: Michal Simek <monstr@monstr.eu>
|
||||
Date: Mon May 7 19:33:51 2007 +0200
|
||||
|
|
35
MAKEALL
35
MAKEALL
|
@ -75,22 +75,23 @@ LIST_8xx=" \
|
|||
#########################################################################
|
||||
|
||||
LIST_4xx=" \
|
||||
acadia ADCIOP alpr AP1000 \
|
||||
AR405 ASH405 bamboo bubinga \
|
||||
CANBT CMS700 CPCI2DP CPCI405 \
|
||||
CPCI4052 CPCI405AB CPCI405DT CPCI440 \
|
||||
CPCIISER4 CRAYL1 csb272 csb472 \
|
||||
DASA_SIM DP405 DU405 ebony \
|
||||
ERIC EXBITGEN G2000 HH405 \
|
||||
HUB405 JSE KAREF katmai \
|
||||
luan METROBOX MIP405 MIP405T \
|
||||
ML2 ml300 ocotea OCRTC \
|
||||
ORSG p3p440 PCI405 pcs440ep \
|
||||
PIP405 PLU405 PMC405 PPChameleonEVB \
|
||||
sbc405 sc3 sequoia sequoia_nand \
|
||||
taishan VOH405 VOM405 W7OLMC \
|
||||
W7OLMG walnut WUH405 XPEDITE1K \
|
||||
yellowstone yosemite yucca \
|
||||
acadia acadia_nand ADCIOP alpr \
|
||||
AP1000 AR405 ASH405 bamboo \
|
||||
bamboo_nand bubinga CANBT CMS700 \
|
||||
CPCI2DP CPCI405 CPCI4052 CPCI405AB \
|
||||
CPCI405DT CPCI440 CPCIISER4 CRAYL1 \
|
||||
csb272 csb472 DASA_SIM DP405 \
|
||||
DU405 ebony ERIC EXBITGEN \
|
||||
G2000 HH405 HUB405 JSE \
|
||||
KAREF katmai luan METROBOX \
|
||||
MIP405 MIP405T ML2 ml300 \
|
||||
ocotea OCRTC ORSG p3p440 \
|
||||
PCI405 pcs440ep PIP405 PLU405 \
|
||||
PMC405 PPChameleonEVB sbc405 sc3 \
|
||||
sequoia sequoia_nand taishan VOH405 \
|
||||
VOM405 W7OLMC W7OLMG walnut \
|
||||
WUH405 XPEDITE1K yellowstone yosemite \
|
||||
yucca \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
|
@ -185,7 +186,7 @@ LIST_SA="assabet dnp1110 gcplus lart shannon"
|
|||
LIST_ARM7=" \
|
||||
armadillo B2 ep7312 evb4510 \
|
||||
impa7 integratorap ap7 ap720t \
|
||||
lpc2292sodimm modnet50 \
|
||||
lpc2292sodimm modnet50 SMN42 \
|
||||
"
|
||||
|
||||
#########################################################################
|
||||
|
|
38
Makefile
38
Makefile
|
@ -173,9 +173,6 @@ endif
|
|||
ifeq ($(CPU),mpc85xx)
|
||||
OBJS += cpu/$(CPU)/resetvec.o
|
||||
endif
|
||||
ifeq ($(CPU),mpc86xx)
|
||||
OBJS += cpu/$(CPU)/resetvec.o
|
||||
endif
|
||||
ifeq ($(CPU),bf533)
|
||||
OBJS += cpu/$(CPU)/start1.o cpu/$(CPU)/interrupt.o cpu/$(CPU)/cache.o
|
||||
OBJS += cpu/$(CPU)/flush.o cpu/$(CPU)/init_sdram.o
|
||||
|
@ -1017,6 +1014,15 @@ xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(
|
|||
acadia_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx acadia amcc
|
||||
|
||||
acadia_nand_config: unconfig
|
||||
@mkdir -p $(obj)include
|
||||
@mkdir -p $(obj)nand_spl
|
||||
@mkdir -p $(obj)board/amcc/acadia
|
||||
@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
|
||||
@$(MKCONFIG) -n $@ -a acadia ppc ppc4xx acadia amcc
|
||||
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/acadia/config.tmp
|
||||
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
|
||||
|
||||
ADCIOP_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd
|
||||
|
||||
|
@ -1038,6 +1044,15 @@ ASH405_config: unconfig
|
|||
bamboo_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx bamboo amcc
|
||||
|
||||
bamboo_nand_config: unconfig
|
||||
@mkdir -p $(obj)include
|
||||
@mkdir -p $(obj)nand_spl
|
||||
@mkdir -p $(obj)board/amcc/bamboo
|
||||
@echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h
|
||||
@$(MKCONFIG) -n $@ -a bamboo ppc ppc4xx bamboo amcc
|
||||
@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/bamboo/config.tmp
|
||||
@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
|
||||
|
||||
bubinga_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc ppc4xx bubinga amcc
|
||||
|
||||
|
@ -1792,8 +1807,16 @@ sbc8560_66_config: unconfig
|
|||
stxgp3_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3
|
||||
|
||||
stxssa_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc mpc85xx stxssa
|
||||
stxssa_config \
|
||||
stxssa_4M_config: unconfig
|
||||
@mkdir -p $(obj)include
|
||||
@if [ "$(findstring _4M_,$@)" ] ; then \
|
||||
echo "#define CONFIG_STXSSA_4M" >>$(obj)include/config.h ; \
|
||||
echo "... with 4 MiB flash memory" ; \
|
||||
else \
|
||||
>$(obj)include/config.h ; \
|
||||
fi
|
||||
@$(MKCONFIG) -a stxssa ppc mpc85xx stxssa
|
||||
|
||||
TQM8540_config \
|
||||
TQM8541_config \
|
||||
|
@ -2113,7 +2136,10 @@ evb4510_config : unconfig
|
|||
@$(MKCONFIG) $(@:_config=) arm arm720t evb4510
|
||||
|
||||
lpc2292sodimm_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm720t lpc2292sodimm
|
||||
@$(MKCONFIG) $(@:_config=) arm arm720t lpc2292sodimm NULL lpc2292
|
||||
|
||||
SMN42_config : unconfig
|
||||
@$(MKCONFIG) $(@:_config=) arm arm720t SMN42 siemens lpc2292
|
||||
|
||||
#########################################################################
|
||||
## XScale Systems
|
||||
|
|
|
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS = $(BOARD).o cpr.o memory.o
|
||||
COBJS = $(BOARD).o cmd_acadia.o cpr.o memory.o
|
||||
SOBJS =
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
|
|
|
@ -63,8 +63,14 @@ int board_early_init_f(void)
|
|||
acadia_gpio_init();
|
||||
|
||||
/* Configure 405EZ for NAND usage */
|
||||
mtsdr(sdrnand0, 0x80c00000);
|
||||
mtsdr(sdrultra0, 0x8d110000);
|
||||
mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
|
||||
mfsdr(sdrultra0, reg);
|
||||
reg &= ~SDR_ULTRA0_CSN_MASK;
|
||||
reg |= (SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS) |
|
||||
SDR_ULTRA0_NDGPIOBP |
|
||||
SDR_ULTRA0_EBCRDYEN |
|
||||
SDR_ULTRA0_NFSRSTEN;
|
||||
mtsdr(sdrultra0, reg);
|
||||
|
||||
/* USB Host core needs this bit set */
|
||||
mfsdr(sdrultra1, reg);
|
||||
|
|
101
board/amcc/acadia/cmd_acadia.c
Normal file
101
board/amcc/acadia/cmd_acadia.c
Normal file
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <i2c.h>
|
||||
|
||||
static u8 boot_267_nor[] = {
|
||||
0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8e, 0x00,
|
||||
0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
static u8 boot_267_nand[] = {
|
||||
0xd0, 0x38, 0xc3, 0x50, 0x13, 0x88, 0x8e, 0x00,
|
||||
0x14, 0xc0, 0x36, 0xcc, 0x00, 0x0c, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00
|
||||
};
|
||||
|
||||
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
u8 chip;
|
||||
u8 *buf;
|
||||
int cpu_freq;
|
||||
|
||||
if (argc < 3) {
|
||||
printf("Usage:\n%s\n", cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
|
||||
cpu_freq = simple_strtol(argv[1], NULL, 10);
|
||||
if (cpu_freq != 267) {
|
||||
printf("Unsupported cpu-frequency - only 267 supported\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* use 0x50 as I2C EEPROM address for now */
|
||||
chip = 0x50;
|
||||
|
||||
if ((strcmp(argv[2], "nor") != 0) &&
|
||||
(strcmp(argv[2], "nand") != 0)) {
|
||||
printf("Unsupported boot-device - only nor|nand support\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (strcmp(argv[2], "nand") == 0) {
|
||||
switch (cpu_freq) {
|
||||
case 267:
|
||||
buf = boot_267_nand;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
switch (cpu_freq) {
|
||||
case 267:
|
||||
buf = boot_267_nor;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (i2c_write(chip, 0, 1, buf, 16) != 0)
|
||||
printf("Error writing to EEPROM at address 0x%x\n", chip);
|
||||
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
|
||||
if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0)
|
||||
printf("Error2 writing to EEPROM at address 0x%x\n", chip);
|
||||
|
||||
printf("Done\n");
|
||||
printf("Please power-cycle the board for the changes to take effect\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
bootstrap, 3, 0, do_bootstrap,
|
||||
"bootstrap - program the I2C bootstrap EEPROM\n",
|
||||
"<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n"
|
||||
);
|
|
@ -21,6 +21,12 @@
|
|||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# AMCC 405EZ Reference Platform (Acadia) board
|
||||
#
|
||||
|
||||
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
||||
|
||||
ifndef TEXT_BASE
|
||||
TEXT_BASE = 0xFFFC0000
|
||||
endif
|
||||
|
|
|
@ -39,6 +39,7 @@ void sdram_init(void)
|
|||
return;
|
||||
}
|
||||
|
||||
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||
static void cram_bcr_write(u32 wr_val)
|
||||
{
|
||||
wr_val <<= 2;
|
||||
|
@ -62,9 +63,12 @@ static void cram_bcr_write(u32 wr_val)
|
|||
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||
int i;
|
||||
u32 val;
|
||||
|
||||
/* 1. EBC need to program READY, CLK, ADV for ASync mode */
|
||||
|
@ -92,7 +96,12 @@ long int initdram(int board_type)
|
|||
|
||||
/* Config EBC to use RDY */
|
||||
mfsdr(sdrultra0, val);
|
||||
mtsdr(sdrultra0, val | 0x04000000);
|
||||
mtsdr(sdrultra0, val | SDR_ULTRA0_EBCRDYEN);
|
||||
|
||||
/* Wait a short while, since for NAND booting this is too fast */
|
||||
for (i=0; i<200000; i++)
|
||||
;
|
||||
#endif
|
||||
|
||||
return (CFG_MBYTES_RAM << 20);
|
||||
}
|
||||
|
|
137
board/amcc/acadia/u-boot-nand.lds
Normal file
137
board/amcc/acadia/u-boot-nand.lds
Normal file
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
|
||||
/* Align to next NAND block */
|
||||
. = ALIGN(0x4000);
|
||||
common/environment.o (.ppcenv)
|
||||
/* Keep some space here for redundant env and potential bad env blocks */
|
||||
. = ALIGN(0x10000);
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# (C) Copyright 2002-2006
|
||||
# (C) Copyright 2002-2007
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
|
@ -33,7 +33,7 @@ OBJS := $(addprefix $(obj),$(COBJS))
|
|||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* (C) Copyright 2005-2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
@ -291,6 +291,7 @@ int checkboard(void)
|
|||
return (0);
|
||||
}
|
||||
|
||||
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
|
||||
/*************************************************************************
|
||||
*
|
||||
* init_spd_array -- Bamboo has one bank onboard sdram (plus DIMM)
|
||||
|
@ -345,10 +346,12 @@ static void init_spd_array(void)
|
|||
cfg_simulate_spd_eeprom[25] = 0x00; /* SDRAM Cycle Time (cas latency 1.5) = N.A */
|
||||
cfg_simulate_spd_eeprom[12] = 0x82; /* refresh Rate Type: Normal (15.625us) + Self refresh */
|
||||
}
|
||||
#endif
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
long dram_size = 0;
|
||||
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
|
||||
long dram_size;
|
||||
|
||||
/*
|
||||
* First write simulated values in eeprom array for onboard bank 0
|
||||
|
@ -358,6 +361,9 @@ long int initdram (int board_type)
|
|||
dram_size = spd_sdram();
|
||||
|
||||
return dram_size;
|
||||
#else
|
||||
return CFG_MBYTES_SDRAM << 20;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(CFG_DRAM_TEST)
|
||||
|
@ -881,11 +887,11 @@ void ext_bus_cntlr_init(void)
|
|||
/*------------------------------------------------------------------------- */
|
||||
case BOOT_FROM_NAND_FLASH0:
|
||||
/*------------------------------------------------------------------------- */
|
||||
ebc0_cs0_bnap_value = 0;
|
||||
ebc0_cs0_bncr_value = 0;
|
||||
ebc0_cs0_bnap_value = EBC0_BNAP_NAND_FLASH;
|
||||
ebc0_cs0_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
|
||||
|
||||
ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;
|
||||
ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;
|
||||
ebc0_cs1_bnap_value = 0;
|
||||
ebc0_cs1_bncr_value = 0;
|
||||
ebc0_cs2_bnap_value = 0;
|
||||
ebc0_cs2_bncr_value = 0;
|
||||
ebc0_cs3_bnap_value = 0;
|
||||
|
@ -1409,10 +1415,10 @@ void update_ndfc_ios(void)
|
|||
gpio_tab[GPIO0][6].in_out = GPIO_OUT; /* EBC_CS_N(1) */
|
||||
gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;
|
||||
|
||||
#if 0
|
||||
gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(2) */
|
||||
gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
|
||||
|
||||
#if 0
|
||||
gpio_tab[GPIO0][7].in_out = GPIO_OUT; /* EBC_CS_N(3) */
|
||||
gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;
|
||||
#endif
|
||||
|
@ -1900,12 +1906,21 @@ void configure_ppc440ep_pins(void)
|
|||
{
|
||||
update_ndfc_ios();
|
||||
|
||||
#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL))
|
||||
mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
|
||||
SDR0_CUST0_NDFC_ENABLE |
|
||||
SDR0_CUST0_NDFC_BW_8_BIT |
|
||||
SDR0_CUST0_NDFC_ARE_MASK |
|
||||
SDR0_CUST0_CHIPSELGAT_EN1 |
|
||||
SDR0_CUST0_CHIPSELGAT_EN2);
|
||||
#else
|
||||
mtsdr(sdr_cust0, SDR0_CUST0_MUX_NDFC_SEL |
|
||||
SDR0_CUST0_NDFC_ENABLE |
|
||||
SDR0_CUST0_NDFC_BW_8_BIT |
|
||||
SDR0_CUST0_NDFC_ARE_MASK |
|
||||
SDR0_CUST0_CHIPSELGAT_EN0 |
|
||||
SDR0_CUST0_CHIPSELGAT_EN2);
|
||||
#endif
|
||||
|
||||
ndfc_selection_in_fpga();
|
||||
}
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# (C) Copyright 2002-2006
|
||||
# (C) Copyright 2002-2007
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
|
@ -21,7 +21,11 @@
|
|||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
|
||||
|
||||
ifndef TEXT_BASE
|
||||
TEXT_BASE = 0xFFFA0000
|
||||
endif
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
|
|
|
@ -53,7 +53,7 @@ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
|||
static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
|
||||
{0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
|
||||
{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
|
||||
{0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash */
|
||||
{0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash */
|
||||
{0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
|
||||
{0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
|
||||
{0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */
|
||||
|
@ -134,10 +134,10 @@ unsigned long flash_init(void)
|
|||
flash_info[i].size = 0;
|
||||
|
||||
/* check whether the address is 0 */
|
||||
if (flash_addr_table[index][i] == 0) {
|
||||
if (flash_addr_table[index][i] == 0)
|
||||
continue;
|
||||
}
|
||||
|
||||
DEBUGF("Detection bank %d...\n", i);
|
||||
/* call flash_get_size() to initialize sector address */
|
||||
size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
|
||||
&flash_info[i]);
|
||||
|
|
|
@ -1,74 +1,31 @@
|
|||
/*
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <config.h>
|
||||
|
||||
/* General */
|
||||
#define TLB_VALID 0x00000200
|
||||
|
||||
/* Supported page sizes */
|
||||
|
||||
#define SZ_1K 0x00000000
|
||||
#define SZ_4K 0x00000010
|
||||
#define SZ_16K 0x00000020
|
||||
#define SZ_64K 0x00000030
|
||||
#define SZ_256K 0x00000040
|
||||
#define SZ_1M 0x00000050
|
||||
#define SZ_8M 0x00000060
|
||||
#define SZ_16M 0x00000070
|
||||
#define SZ_256M 0x00000090
|
||||
|
||||
/* Storage attributes */
|
||||
#define SA_W 0x00000800 /* Write-through */
|
||||
#define SA_I 0x00000400 /* Caching inhibited */
|
||||
#define SA_M 0x00000200 /* Memory coherence */
|
||||
#define SA_G 0x00000100 /* Guarded */
|
||||
#define SA_E 0x00000080 /* Endian */
|
||||
|
||||
/* Access control */
|
||||
#define AC_X 0x00000024 /* Execute */
|
||||
#define AC_W 0x00000012 /* Write */
|
||||
#define AC_R 0x00000009 /* Read */
|
||||
|
||||
/* Some handy macros */
|
||||
|
||||
#define EPN(e) ((e) & 0xfffffc00)
|
||||
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
|
||||
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
|
||||
#define TLB2(a) ( (a)&0x00000fbf )
|
||||
|
||||
#define tlbtab_start\
|
||||
mflr r1 ;\
|
||||
bl 0f ;
|
||||
|
||||
#define tlbtab_end\
|
||||
.long 0, 0, 0 ; \
|
||||
0: mflr r0 ; \
|
||||
mtlr r1 ; \
|
||||
blr ;
|
||||
|
||||
#define tlbentry(epn,sz,rpn,erpn,attr)\
|
||||
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
|
||||
|
||||
#include <asm-ppc/mmu.h>
|
||||
|
||||
/**************************************************************************
|
||||
* TLB TABLE
|
||||
|
@ -80,34 +37,68 @@
|
|||
* Pointer to the table is returned in r1
|
||||
*
|
||||
*************************************************************************/
|
||||
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
.section .bootpg,"ax"
|
||||
.globl tlbtab
|
||||
|
||||
tlbtab:
|
||||
tlbtab_start
|
||||
tlbtab_start
|
||||
|
||||
/*
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
|
||||
/*
|
||||
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
|
||||
* speed up boot process. It is patched after relocation to enable SA_I
|
||||
*/
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
|
||||
#else
|
||||
tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
|
||||
#endif
|
||||
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
|
||||
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
|
||||
tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
|
||||
|
||||
tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
|
||||
tlbentry( CFG_NAND_ADDR, SZ_256M, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
|
||||
tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
|
||||
/* PCI */
|
||||
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
/* PCI base & peripherals */
|
||||
tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
|
||||
|
||||
/* USB 2.0 Device */
|
||||
tlbentry( CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I )
|
||||
tlbentry(CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
|
||||
tlbentry(CFG_NAND_ADDR, SZ_4K, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
|
||||
|
||||
tlbtab_end
|
||||
/* PCI */
|
||||
tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I)
|
||||
tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I)
|
||||
|
||||
/* USB 2.0 Device */
|
||||
tlbentry(CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I)
|
||||
|
||||
tlbtab_end
|
||||
|
||||
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
/*
|
||||
* For NAND booting the first TLB has to be reconfigured to full size
|
||||
* and with caching disabled after running from RAM!
|
||||
*/
|
||||
#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
|
||||
#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 0)
|
||||
#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
|
||||
|
||||
.globl reconfig_tlb0
|
||||
reconfig_tlb0:
|
||||
sync
|
||||
isync
|
||||
addi r4,r0,0x0000 /* TLB entry #0 */
|
||||
lis r5,TLB00@h
|
||||
ori r5,r5,TLB00@l
|
||||
tlbwe r5,r4,0x0000 /* Save it out */
|
||||
lis r5,TLB01@h
|
||||
ori r5,r5,TLB01@l
|
||||
tlbwe r5,r4,0x0001 /* Save it out */
|
||||
lis r5,TLB02@h
|
||||
ori r5,r5,TLB02@l
|
||||
tlbwe r5,r4,0x0002 /* Save it out */
|
||||
sync
|
||||
isync
|
||||
blr
|
||||
#endif
|
||||
|
|
137
board/amcc/bamboo/u-boot-nand.lds
Normal file
137
board/amcc/bamboo/u-boot-nand.lds
Normal file
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
/* WARNING - the following is hand-optimized to fit within */
|
||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||
|
||||
cpu/ppc4xx/start.o (.text)
|
||||
|
||||
/* Align to next NAND block */
|
||||
. = ALIGN(0x4000);
|
||||
common/environment.o (.ppcenv)
|
||||
/* Keep some space here for redundant env and potential bad env blocks */
|
||||
. = ALIGN(0x10000);
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
|
@ -387,7 +387,11 @@ void denali_core_search_data_eye(unsigned long memory_size)
|
|||
long int initdram (int board_type)
|
||||
{
|
||||
#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
|
||||
#if !defined(CONFIG_NAND_SPL)
|
||||
ulong speed = get_bus_freq(0);
|
||||
#else
|
||||
ulong speed = 133333333; /* 133MHz is on the safe side */
|
||||
#endif
|
||||
|
||||
mtsdram(DDR0_02, 0x00000000);
|
||||
|
||||
|
|
|
@ -132,12 +132,6 @@ int board_early_init_f(void)
|
|||
(0x80000000 >> (28 + CFG_NAND_CS));
|
||||
mtsdr(SDR0_CUST0, sdr0_cust0);
|
||||
|
||||
/* Update EBC speed after booting from i2c bootstrap settings
|
||||
* on newer boards with 33.333 MHZ Clocks
|
||||
*/
|
||||
if (in8(CFG_BCSR_BASE + 3) & 0x80)
|
||||
mtcpr(0xe0, 0x02000000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -1,7 +1,6 @@
|
|||
#
|
||||
# (C) Copyright 2002
|
||||
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
# Marius Groeger <mgroeger@sysgo.de>
|
||||
# (C) Copyright 2007
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
|
@ -24,35 +23,29 @@
|
|||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = lib$(BOARD).a
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
OBJS := lpc2292sodimm.o flash.o mmc.o spi.o mmc_hw.o eth.o
|
||||
SOBJS := lowlevel_init.o iap_entry.o
|
||||
COBJS := flash.o lpc2292sodimm.o
|
||||
SOBJTS := lowlevel_init.o
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
SRCS := $(SOBJTS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJTS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) crv $@ $(OBJS) $(SOBJS)
|
||||
|
||||
# this MUST be compiled as thumb code!
|
||||
iap_entry.o:
|
||||
arm-linux-gcc -D__ASSEMBLY__ -g -Os -fno-strict-aliasing \
|
||||
-fno-common -ffixed-r8 -msoft-float -D__KERNEL__ \
|
||||
-DTEXT_BASE=0x81500000 -I/home/garyj/proj/LPC/u-boot/include \
|
||||
-fno-builtin -ffreestanding -nostdinc -isystem \
|
||||
/opt/eldk/arm/usr/bin/../lib/gcc/arm-linux/4.0.0/include -pipe \
|
||||
-DCONFIG_ARM -D__ARM__ -march=armv4t -mtune=arm7tdmi -mabi=apcs-gnu \
|
||||
-c -o iap_entry.o iap_entry.S
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
-include .depend
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
|
|
@ -1,6 +1,9 @@
|
|||
/*
|
||||
* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
|
||||
*
|
||||
* Modified to use the routines in cpu/arm720t/lpc2292/flash.c by
|
||||
* Gary Jennejohn <garyj@denx,de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
|
@ -20,84 +23,16 @@
|
|||
#include <common.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
/* IAP commands use 32 bytes at the top of CPU internal sram, we
|
||||
use 512 bytes below that */
|
||||
#define COPY_BUFFER_LOCATION 0x40003de0
|
||||
|
||||
#define IAP_LOCATION 0x7ffffff1
|
||||
#define IAP_CMD_PREPARE 50
|
||||
#define IAP_CMD_COPY 51
|
||||
#define IAP_CMD_ERASE 52
|
||||
#define IAP_CMD_CHECK 53
|
||||
#define IAP_CMD_ID 54
|
||||
#define IAP_CMD_VERSION 55
|
||||
#define IAP_CMD_COMPARE 56
|
||||
|
||||
#define IAP_RET_CMD_SUCCESS 0
|
||||
|
||||
#define SST_BASEADDR 0x80000000
|
||||
#define SST_ADDR1 ((volatile ushort*)(SST_BASEADDR + (0x5555 << 1)))
|
||||
#define SST_ADDR2 ((volatile ushort*)(SST_BASEADDR + (0x2AAA << 1)))
|
||||
|
||||
|
||||
static unsigned long command[5];
|
||||
static unsigned long result[2];
|
||||
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
|
||||
|
||||
extern void iap_entry(unsigned long * command, unsigned long * result);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
int get_flash_sector(flash_info_t * info, ulong flash_addr)
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i=1; i < (info->sector_count); i++) {
|
||||
if (flash_addr < (info->start[i]))
|
||||
break;
|
||||
}
|
||||
|
||||
return (i-1);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* This function assumes that flash_addr is aligned on 512 bytes boundary
|
||||
* in flash. This function also assumes that prepare have been called
|
||||
* for the sector in question.
|
||||
*/
|
||||
int copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
|
||||
{
|
||||
int first_sector;
|
||||
int last_sector;
|
||||
|
||||
first_sector = get_flash_sector(info, flash_addr);
|
||||
last_sector = get_flash_sector(info, flash_addr + 512 - 1);
|
||||
|
||||
/* prepare sectors for write */
|
||||
command[0] = IAP_CMD_PREPARE;
|
||||
command[1] = first_sector;
|
||||
command[2] = last_sector;
|
||||
iap_entry(command, result);
|
||||
if (result[0] != IAP_RET_CMD_SUCCESS) {
|
||||
printf("IAP prepare failed\n");
|
||||
return ERR_PROG_ERROR;
|
||||
}
|
||||
|
||||
command[0] = IAP_CMD_COPY;
|
||||
command[1] = flash_addr;
|
||||
command[2] = COPY_BUFFER_LOCATION;
|
||||
command[3] = 512;
|
||||
command[4] = CFG_SYS_CLK_FREQ >> 10;
|
||||
iap_entry(command, result);
|
||||
if (result[0] != IAP_RET_CMD_SUCCESS) {
|
||||
printf("IAP copy failed\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
extern int lpc2292_copy_buffer_to_flash(flash_info_t *, ulong);
|
||||
extern int lpc2292_flash_erase(flash_info_t *, int, int);
|
||||
extern int lpc2292_write_buff (flash_info_t *, uchar *, ulong, ulong);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
|
@ -220,56 +155,6 @@ void flash_print_info (flash_info_t * info)
|
|||
printf ("\n");
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int flash_erase_philips (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
int flag;
|
||||
int prot;
|
||||
int sect;
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
if (prot)
|
||||
return ERR_PROTECTED;
|
||||
|
||||
|
||||
flag = disable_interrupts();
|
||||
|
||||
printf ("Erasing %d sectors starting at sector %2d.\n"
|
||||
"This make take some time ... ",
|
||||
s_last - s_first + 1, s_first);
|
||||
|
||||
command[0] = IAP_CMD_PREPARE;
|
||||
command[1] = s_first;
|
||||
command[2] = s_last;
|
||||
iap_entry(command, result);
|
||||
if (result[0] != IAP_RET_CMD_SUCCESS) {
|
||||
printf("IAP prepare failed\n");
|
||||
return ERR_PROTECTED;
|
||||
}
|
||||
|
||||
command[0] = IAP_CMD_ERASE;
|
||||
command[1] = s_first;
|
||||
command[2] = s_last;
|
||||
command[3] = CFG_SYS_CLK_FREQ >> 10;
|
||||
iap_entry(command, result);
|
||||
if (result[0] != IAP_RET_CMD_SUCCESS) {
|
||||
printf("IAP erase failed\n");
|
||||
return ERR_PROTECTED;
|
||||
}
|
||||
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
int flash_erase_sst (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
int i;
|
||||
|
@ -294,7 +179,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
|
|||
case (SST_MANUFACT & FLASH_VENDMASK):
|
||||
return flash_erase_sst(info, s_first, s_last);
|
||||
case (PHILIPS_LPC2292 & FLASH_VENDMASK):
|
||||
return flash_erase_philips(info, s_first, s_last);
|
||||
return lpc2292_flash_erase(info, s_first, s_last);
|
||||
default:
|
||||
return ERR_PROTECTED;
|
||||
}
|
||||
|
@ -353,122 +238,13 @@ int write_buff_sst (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
|||
return ret;
|
||||
}
|
||||
|
||||
int write_buff_philips (flash_info_t * info,
|
||||
uchar * src,
|
||||
ulong addr,
|
||||
ulong cnt)
|
||||
{
|
||||
int first_copy_size;
|
||||
int last_copy_size;
|
||||
int first_block;
|
||||
int last_block;
|
||||
int nbr_mid_blocks;
|
||||
uchar memmap_value;
|
||||
ulong i;
|
||||
uchar* src_org;
|
||||
uchar* dst_org;
|
||||
int ret = ERR_OK;
|
||||
|
||||
src_org = src;
|
||||
dst_org = (uchar*)addr;
|
||||
|
||||
first_block = addr / 512;
|
||||
last_block = (addr + cnt) / 512;
|
||||
nbr_mid_blocks = last_block - first_block - 1;
|
||||
|
||||
first_copy_size = 512 - (addr % 512);
|
||||
last_copy_size = (addr + cnt) % 512;
|
||||
|
||||
#if 0
|
||||
printf("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
|
||||
"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
|
||||
(ulong)(first_block * 512),
|
||||
(ulong)COPY_BUFFER_LOCATION,
|
||||
(ulong)src,
|
||||
(ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
|
||||
first_copy_size,
|
||||
(ulong)COPY_BUFFER_LOCATION,
|
||||
(ulong)(first_block * 512));
|
||||
#endif
|
||||
|
||||
/* copy first block */
|
||||
memcpy((void*)COPY_BUFFER_LOCATION,
|
||||
(void*)(first_block * 512), 512);
|
||||
memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
|
||||
src, first_copy_size);
|
||||
copy_buffer_to_flash(info, first_block * 512);
|
||||
src += first_copy_size;
|
||||
addr += first_copy_size;
|
||||
|
||||
/* copy middle blocks */
|
||||
for (i = 0; i < nbr_mid_blocks; i++) {
|
||||
#if 0
|
||||
printf("copy middle block: %lX -> %lX 512 bytes, "
|
||||
"%lX -> %lX 512 bytes\n",
|
||||
(ulong)src,
|
||||
(ulong)COPY_BUFFER_LOCATION,
|
||||
(ulong)COPY_BUFFER_LOCATION,
|
||||
(ulong)addr);
|
||||
#endif
|
||||
memcpy((void*)COPY_BUFFER_LOCATION, src, 512);
|
||||
copy_buffer_to_flash(info, addr);
|
||||
src += 512;
|
||||
addr += 512;
|
||||
}
|
||||
|
||||
|
||||
if (last_copy_size > 0) {
|
||||
#if 0
|
||||
printf("copy last block: (1) %lX -> %lX 0x200 bytes, "
|
||||
"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
|
||||
(ulong)(last_block * 512),
|
||||
(ulong)COPY_BUFFER_LOCATION,
|
||||
(ulong)src,
|
||||
(ulong)(COPY_BUFFER_LOCATION),
|
||||
last_copy_size,
|
||||
(ulong)COPY_BUFFER_LOCATION,
|
||||
(ulong)addr);
|
||||
#endif
|
||||
/* copy last block */
|
||||
memcpy((void*)COPY_BUFFER_LOCATION,
|
||||
(void*)(last_block * 512), 512);
|
||||
memcpy((void*)COPY_BUFFER_LOCATION,
|
||||
src, last_copy_size);
|
||||
copy_buffer_to_flash(info, addr);
|
||||
}
|
||||
|
||||
/* verify write */
|
||||
memmap_value = GET8(MEMMAP);
|
||||
|
||||
disable_interrupts();
|
||||
|
||||
PUT8(MEMMAP, 01); /* we must make sure that initial 64
|
||||
bytes are taken from flash when we
|
||||
do the compare */
|
||||
|
||||
for (i = 0; i < cnt; i++) {
|
||||
if (*dst_org != *src_org){
|
||||
printf("Write failed. Byte %lX differs\n", i);
|
||||
ret = ERR_PROG_ERROR;
|
||||
break;
|
||||
}
|
||||
dst_org++;
|
||||
src_org++;
|
||||
}
|
||||
|
||||
PUT8(MEMMAP, memmap_value);
|
||||
enable_interrupts();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case (SST_MANUFACT & FLASH_VENDMASK):
|
||||
return write_buff_sst(info, src, addr, cnt);
|
||||
case (PHILIPS_LPC2292 & FLASH_VENDMASK):
|
||||
return write_buff_philips(info, src, addr, cnt);
|
||||
return lpc2292_write_buff(info, src, addr, cnt);
|
||||
default:
|
||||
return ERR_PROG_ERROR;
|
||||
}
|
||||
|
|
|
@ -23,6 +23,10 @@
|
|||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
ifneq ($(OBJTREE),$(SRCTREE))
|
||||
$(shell mkdir -p $(obj)../freescale/common)
|
||||
endif
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o sys_eeprom.o \
|
||||
|
|
|
@ -25,7 +25,7 @@
|
|||
# default CCSRBAR is at 0xff700000
|
||||
# assume U-Boot is less than 0.5MB
|
||||
#
|
||||
TEXT_BASE = 0xfff01000
|
||||
TEXT_BASE = 0xfff00000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 -maltivec -mabi=altivec -msoft-float
|
||||
|
|
|
@ -1,7 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2004, Freescale, Inc.
|
||||
* (C) Copyright 2002,2003, Motorola,Inc.
|
||||
* Jeff Brown
|
||||
* Copyright 2006, 2007 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -23,24 +21,11 @@
|
|||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xFFF00100 :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
.bootpg 0xFFF70000 :
|
||||
{
|
||||
cpu/mpc86xx/start.o (.bootpg)
|
||||
board/mpc8641hpcn/init.o (.bootpg)
|
||||
} = 0xffff
|
||||
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + 1024;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
|
@ -66,7 +51,7 @@ SECTIONS
|
|||
.text :
|
||||
{
|
||||
cpu/mpc86xx/start.o (.text)
|
||||
board/mpc8641hpcn/init.o (.text)
|
||||
board/mpc8641hpcn/init.o (.bootpg)
|
||||
cpu/mpc86xx/traps.o (.text)
|
||||
cpu/mpc86xx/interrupts.o (.text)
|
||||
cpu/mpc86xx/cpu_init.o (.text)
|
||||
|
@ -88,6 +73,7 @@ SECTIONS
|
|||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
*(.eh_frame)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
|
|
51
board/siemens/SMN42/Makefile
Normal file
51
board/siemens/SMN42/Makefile
Normal file
|
@ -0,0 +1,51 @@
|
|||
#
|
||||
# (C) Copyright 2007
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := flash.o smn42.o
|
||||
SOBJTS := lowlevel_init.o
|
||||
|
||||
SRCS := $(SOBJTS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJTS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) crv $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
30
board/siemens/SMN42/config.mk
Normal file
30
board/siemens/SMN42/config.mk
Normal file
|
@ -0,0 +1,30 @@
|
|||
#
|
||||
# (C) Copyright 2000
|
||||
# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
# Marius Groeger <mgroeger@sysgo.de>
|
||||
#
|
||||
# (C) Copyright 2000
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#address where u-boot will be relocated
|
||||
#TEXT_BASE = 0x0
|
||||
TEXT_BASE = 0x81500000
|
475
board/siemens/SMN42/flash.c
Executable file
475
board/siemens/SMN42/flash.c
Executable file
|
@ -0,0 +1,475 @@
|
|||
/*
|
||||
* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
|
||||
*
|
||||
* (C) Copyright 2007 Gary Jennejohn garyj@denx.de
|
||||
* Modified to use the routines in cpu/arm720t/lpc2292/flash.c.
|
||||
* Heavily modified to support the SMN42 board from Siemens
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
static unsigned long flash_addr_table[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
|
||||
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
|
||||
|
||||
extern int lpc2292_copy_buffer_to_flash(flash_info_t *, ulong);
|
||||
extern int lpc2292_flash_erase(flash_info_t *, int, int);
|
||||
extern int lpc2292_write_buff (flash_info_t *, uchar *, ulong, ulong);
|
||||
static unsigned long ext_flash_init(void);
|
||||
static int ext_flash_erase(flash_info_t *, int, int);
|
||||
static int ext_write_buff(flash_info_t *, uchar *, ulong, ulong);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
ulong flash_init (void)
|
||||
{
|
||||
int j, k;
|
||||
ulong size = 0;
|
||||
ulong flashbase = 0;
|
||||
|
||||
flash_info[0].flash_id = PHILIPS_LPC2292;
|
||||
flash_info[0].size = 0x003E000; /* 256 - 8 KB */
|
||||
flash_info[0].sector_count = 17;
|
||||
memset (flash_info[0].protect, 0, 17);
|
||||
flashbase = 0x00000000;
|
||||
for (j = 0, k = 0; j < 8; j++, k++) {
|
||||
flash_info[0].start[k] = flashbase;
|
||||
flashbase += 0x00002000;
|
||||
}
|
||||
for (j = 0; j < 2; j++, k++) {
|
||||
flash_info[0].start[k] = flashbase;
|
||||
flashbase += 0x00010000;
|
||||
}
|
||||
for (j = 0; j < 7; j++, k++) {
|
||||
flash_info[0].start[k] = flashbase;
|
||||
flashbase += 0x00002000;
|
||||
}
|
||||
size += flash_info[0].size;
|
||||
|
||||
/* Protect monitor and environment sectors */
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
0x0,
|
||||
0x0 + monitor_flash_len - 1,
|
||||
&flash_info[0]);
|
||||
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CFG_ENV_ADDR,
|
||||
CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
|
||||
&flash_info[0]);
|
||||
|
||||
size += ext_flash_init();
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
int erased = 0;
|
||||
unsigned long j;
|
||||
unsigned long count;
|
||||
unsigned char *p;
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case (PHILIPS_LPC2292 & FLASH_VENDMASK):
|
||||
printf("Philips: ");
|
||||
break;
|
||||
case FLASH_MAN_AMD:
|
||||
printf("AMD: ");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case (PHILIPS_LPC2292 & FLASH_TYPEMASK):
|
||||
printf("LPC2292 internal flash\n");
|
||||
break;
|
||||
case FLASH_S29GL128N:
|
||||
printf ("S29GL128N (128 Mbit, uniform sector size)\n");
|
||||
break;
|
||||
default:
|
||||
printf("Unknown Chip Type\n");
|
||||
return;
|
||||
}
|
||||
|
||||
printf (" Size: %ld KB in %d Sectors\n",
|
||||
info->size >> 10, info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
if ((i % 5) == 0) {
|
||||
printf ("\n ");
|
||||
}
|
||||
if (i < (info->sector_count - 1)) {
|
||||
count = info->start[i+1] - info->start[i];
|
||||
}
|
||||
else {
|
||||
count = info->start[0] + info->size - info->start[i];
|
||||
}
|
||||
p = (unsigned char*)(info->start[i]);
|
||||
erased = 1;
|
||||
for (j = 0; j < count; j++) {
|
||||
if (*p != 0xFF) {
|
||||
erased = 0;
|
||||
break;
|
||||
}
|
||||
p++;
|
||||
}
|
||||
printf (" %08lX%s%s", info->start[i], info->protect[i] ? " RO" : " ",
|
||||
erased ? " E" : " ");
|
||||
}
|
||||
printf ("\n");
|
||||
}
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case (PHILIPS_LPC2292 & FLASH_TYPEMASK):
|
||||
return lpc2292_flash_erase(info, s_first, s_last);
|
||||
case FLASH_S29GL128N:
|
||||
return ext_flash_erase(info, s_first, s_last);
|
||||
default:
|
||||
return ERR_PROTECTED;
|
||||
}
|
||||
return ERR_PROTECTED;
|
||||
}
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case (PHILIPS_LPC2292 & FLASH_TYPEMASK):
|
||||
return lpc2292_write_buff(info, src, addr, cnt);
|
||||
case FLASH_S29GL128N:
|
||||
return ext_write_buff(info, src, addr, cnt);
|
||||
default:
|
||||
return ERR_PROG_ERROR;
|
||||
}
|
||||
return ERR_PROG_ERROR;
|
||||
}
|
||||
|
||||
/*--------------------------------------------------------------------------
|
||||
* From here on is code for the external S29GL128N taken from cam5200_flash.c
|
||||
*/
|
||||
|
||||
#define CFG_FLASH_WORD_SIZE unsigned short
|
||||
|
||||
static int wait_for_DQ7_32(flash_info_t * info, int sect)
|
||||
{
|
||||
ulong start, now, last;
|
||||
volatile CFG_FLASH_WORD_SIZE *addr =
|
||||
(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
|
||||
|
||||
start = get_timer(0);
|
||||
last = start;
|
||||
while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
|
||||
(CFG_FLASH_WORD_SIZE) 0x00800080) {
|
||||
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
|
||||
printf("Timeout\n");
|
||||
return -1;
|
||||
}
|
||||
/* show that we're waiting */
|
||||
if ((now - last) > 1000) { /* every second */
|
||||
putc('.');
|
||||
last = now;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ext_flash_erase(flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
|
||||
volatile CFG_FLASH_WORD_SIZE *addr2;
|
||||
int flag, prot, sect, l_sect, ret;
|
||||
|
||||
ret = 0;
|
||||
if ((s_first < 0) || (s_first > s_last)) {
|
||||
if (info->flash_id == FLASH_UNKNOWN)
|
||||
printf("- missing\n");
|
||||
else
|
||||
printf("- no sectors to erase\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN) {
|
||||
printf("Can't erase unknown flash type - aborted\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect])
|
||||
prot++;
|
||||
}
|
||||
|
||||
if (prot)
|
||||
printf("- Warning: %d protected sectors will not be erased!", prot);
|
||||
|
||||
printf("\n");
|
||||
|
||||
l_sect = -1;
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
/* Start erase on unprotected sectors */
|
||||
for (sect = s_first; sect <= s_last; sect++) {
|
||||
if (info->protect[sect] == 0) { /* not protected */
|
||||
addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
|
||||
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
|
||||
addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
|
||||
|
||||
l_sect = sect;
|
||||
/*
|
||||
* Wait for each sector to complete, it's more
|
||||
* reliable. According to AMD Spec, you must
|
||||
* issue all erase commands within a specified
|
||||
* timeout. This has been seen to fail, especially
|
||||
* if printf()s are included (for debug)!!
|
||||
*/
|
||||
ret = wait_for_DQ7_32(info, sect);
|
||||
if (ret) {
|
||||
ret = ERR_PROTECTED;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* wait at least 80us - let's wait 1 ms */
|
||||
udelay(1000);
|
||||
|
||||
/* reset to read mode */
|
||||
addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
|
||||
addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
|
||||
|
||||
if (ret)
|
||||
printf(" error\n");
|
||||
else
|
||||
printf(" done\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
static ulong flash_get_size(vu_long * addr, flash_info_t * info)
|
||||
{
|
||||
short i;
|
||||
CFG_FLASH_WORD_SIZE value;
|
||||
ulong base = (ulong) addr;
|
||||
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
|
||||
|
||||
/* Write auto select command: read Manufacturer ID */
|
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
|
||||
udelay(1000);
|
||||
|
||||
value = addr2[0];
|
||||
|
||||
switch (value) {
|
||||
case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
|
||||
info->flash_id = FLASH_MAN_AMD;
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
info->sector_count = 0;
|
||||
info->size = 0;
|
||||
return (0); /* no or unknown flash */
|
||||
}
|
||||
|
||||
value = addr2[1]; /* device ID */
|
||||
|
||||
switch (value) {
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_MIRROR:
|
||||
value = addr2[14];
|
||||
switch(value) {
|
||||
case (CFG_FLASH_WORD_SIZE)AMD_ID_GL128N_2:
|
||||
value = addr2[15];
|
||||
if (value != (CFG_FLASH_WORD_SIZE)AMD_ID_GL128N_3) {
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
} else {
|
||||
info->flash_id += FLASH_S29GL128N;
|
||||
info->sector_count = 128;
|
||||
info->size = 0x01000000;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return(0);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
info->flash_id = FLASH_UNKNOWN;
|
||||
return (0); /* => no or unknown flash */
|
||||
}
|
||||
|
||||
/* set up sector start address table */
|
||||
for (i = 0; i < info->sector_count; i++)
|
||||
info->start[i] = base + (i * 0x00020000);
|
||||
|
||||
/* check for protected sectors */
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
||||
/* D0 = 1 if protected */
|
||||
addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
|
||||
|
||||
info->protect[i] = addr2[2] & 1;
|
||||
}
|
||||
|
||||
/* issue bank reset to return to read mode */
|
||||
addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
|
||||
|
||||
return (info->size);
|
||||
}
|
||||
|
||||
static unsigned long ext_flash_init(void)
|
||||
{
|
||||
unsigned long total_b = 0;
|
||||
unsigned long size_b[CFG_MAX_FLASH_BANKS];
|
||||
int i;
|
||||
|
||||
/* Init: no FLASHes known */
|
||||
for (i = 1; i < CFG_MAX_FLASH_BANKS; ++i) {
|
||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
||||
flash_info[i].sector_count = -1;
|
||||
flash_info[i].size = 0;
|
||||
|
||||
/* call flash_get_size() to initialize sector address */
|
||||
size_b[i] = flash_get_size((vu_long *) flash_addr_table[i],
|
||||
&flash_info[i]);
|
||||
|
||||
flash_info[i].size = size_b[i];
|
||||
|
||||
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
|
||||
printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
|
||||
i+1, size_b[i], size_b[i] << 20);
|
||||
flash_info[i].sector_count = -1;
|
||||
flash_info[i].size = 0;
|
||||
}
|
||||
|
||||
total_b += flash_info[i].size;
|
||||
}
|
||||
|
||||
return total_b;
|
||||
}
|
||||
|
||||
static int write_word(flash_info_t * info, ulong dest, ushort data)
|
||||
{
|
||||
volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
|
||||
volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
|
||||
volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) &data;
|
||||
ulong start;
|
||||
int flag;
|
||||
|
||||
/* Check if Flash is (sufficiently) erased */
|
||||
if ((*dest2 & *data2) != *data2) {
|
||||
return (2);
|
||||
}
|
||||
|
||||
/* Disable interrupts which might cause a timeout here */
|
||||
flag = disable_interrupts();
|
||||
|
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
|
||||
addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
|
||||
addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
|
||||
*dest2 = *data2;
|
||||
|
||||
/* re-enable interrupts if necessary */
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
/* data polling for D7 */
|
||||
start = get_timer(0);
|
||||
while ((*dest2 & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
|
||||
(*data2 & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
|
||||
|
||||
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
|
||||
printf("WRITE_TOUT\n");
|
||||
return (1);
|
||||
}
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* This is taken from the original flash.c for the LPC2292 SODIMM board
|
||||
* and modified to suit.
|
||||
*/
|
||||
|
||||
int ext_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
ushort tmp;
|
||||
ulong i;
|
||||
uchar* src_org;
|
||||
uchar* dst_org;
|
||||
ulong cnt_org = cnt;
|
||||
int ret = ERR_OK;
|
||||
|
||||
src_org = src;
|
||||
dst_org = (uchar*)addr;
|
||||
|
||||
if (addr & 1) { /* if odd address */
|
||||
tmp = *((uchar*)(addr - 1)); /* little endian */
|
||||
tmp |= (*src << 8);
|
||||
if (write_word(info, addr - 1, tmp))
|
||||
return ERR_PROG_ERROR;
|
||||
addr += 1;
|
||||
cnt -= 1;
|
||||
src++;
|
||||
}
|
||||
while (cnt > 1) {
|
||||
tmp = ((*(src+1)) << 8) + (*src); /* little endian */
|
||||
if (write_word(info, addr, tmp))
|
||||
return ERR_PROG_ERROR;
|
||||
addr += 2;
|
||||
src += 2;
|
||||
cnt -= 2;
|
||||
}
|
||||
if (cnt > 0) {
|
||||
tmp = (*((uchar*)(addr + 1))) << 8;
|
||||
tmp |= *src;
|
||||
if (write_word(info, addr, tmp))
|
||||
return ERR_PROG_ERROR;
|
||||
}
|
||||
|
||||
for (i = 0; i < cnt_org; i++) {
|
||||
if (*dst_org != *src_org) {
|
||||
printf("Write failed. Byte %lX differs\n", i);
|
||||
ret = ERR_PROG_ERROR;
|
||||
break;
|
||||
}
|
||||
dst_org++;
|
||||
src_org++;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
123
board/siemens/SMN42/lowlevel_init.S
Normal file
123
board/siemens/SMN42/lowlevel_init.S
Normal file
|
@ -0,0 +1,123 @@
|
|||
/*
|
||||
* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
|
||||
*
|
||||
* Slight modifications made to support the SMN42 board from Siemens.
|
||||
* 2007 Gary Jennejohn garyj@denx.de
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
/* some parameters for the board */
|
||||
/* setting up the CPU-internal memory */
|
||||
#define SRAM_START 0x40000000
|
||||
#define SRAM_SIZE 0x00004000
|
||||
#define BCFG0_VALUE 0x1000ffef
|
||||
#define BCFG1_VALUE 0x10005D2F
|
||||
#define BCFG2_VALUE 0x10005D2F
|
||||
/*
|
||||
* For P0.18 to set ZZ to the SRAMs to 1. Also set P0.2 (SCL) and P0.3 (SDA)
|
||||
* for the bit-banger I2C driver correctly.
|
||||
*/
|
||||
#define IO0_VALUE 0x4000C
|
||||
|
||||
_TEXT_BASE:
|
||||
.word TEXT_BASE
|
||||
MEMMAP_ADR:
|
||||
.word MEMMAP
|
||||
BCFG0_ADR:
|
||||
.word BCFG0
|
||||
_BCFG0_VALUE:
|
||||
.word BCFG0_VALUE
|
||||
BCFG1_ADR:
|
||||
.word BCFG1
|
||||
_BCFG1_VALUE:
|
||||
.word BCFG1_VALUE
|
||||
BCFG2_ADR:
|
||||
.word BCFG2
|
||||
_BCFG2_VALUE:
|
||||
.word BCFG2_VALUE
|
||||
IO0DIR_ADR:
|
||||
.word IO0DIR
|
||||
_IO0DIR_VALUE:
|
||||
.word IO0_VALUE
|
||||
IO0SET_ADR:
|
||||
.word IO0SET
|
||||
_IO0SET_VALUE:
|
||||
.word IO0_VALUE
|
||||
PINSEL2_ADR:
|
||||
.word PINSEL2
|
||||
PINSEL2_MASK:
|
||||
.word 0x00000000
|
||||
PINSEL2_VALUE:
|
||||
.word 0x0F804914
|
||||
|
||||
.extern _start
|
||||
|
||||
.globl lowlevel_init
|
||||
lowlevel_init:
|
||||
/* set up memory control register for bank 0 */
|
||||
ldr r0, _BCFG0_VALUE
|
||||
ldr r1, BCFG0_ADR
|
||||
str r0, [r1]
|
||||
|
||||
/* set up memory control register for bank 1 */
|
||||
ldr r0, _BCFG1_VALUE
|
||||
ldr r1, BCFG1_ADR
|
||||
str r0, [r1]
|
||||
|
||||
/* set up memory control register for bank 2 */
|
||||
ldr r0, _BCFG2_VALUE
|
||||
ldr r1, BCFG2_ADR
|
||||
str r0, [r1]
|
||||
|
||||
/* set IO0DIR to make P0.2, P0.3 and P0.18 outputs */
|
||||
ldr r0, _IO0DIR_VALUE
|
||||
ldr r1, IO0DIR_ADR
|
||||
str r0, [r1]
|
||||
|
||||
/* set P0.18 to 1 */
|
||||
ldr r0, _IO0SET_VALUE
|
||||
ldr r1, IO0SET_ADR
|
||||
str r0, [r1]
|
||||
|
||||
/* set up PINSEL2 for bus-pins */
|
||||
ldr r0, PINSEL2_ADR
|
||||
ldr r1, [r0]
|
||||
ldr r2, PINSEL2_MASK
|
||||
ldr r3, PINSEL2_VALUE
|
||||
and r1, r1, r2
|
||||
orr r1, r1, r3
|
||||
str r1, [r0]
|
||||
|
||||
/* move vectors to beginning of SRAM */
|
||||
mov r2, #SRAM_START
|
||||
mov r0, #0 /*_start*/
|
||||
ldmneia r0!, {r3-r10}
|
||||
stmneia r2!, {r3-r10}
|
||||
ldmneia r0, {r3-r9}
|
||||
stmneia r2, {r3-r9}
|
||||
|
||||
/* Set-up MEMMAP register, so vectors are taken from SRAM */
|
||||
ldr r0, MEMMAP_ADR
|
||||
mov r1, #0x02 /* vectors re-mapped to static RAM */
|
||||
str r1, [r0]
|
||||
|
||||
/* everything is fine now */
|
||||
mov pc, lr
|
62
board/siemens/SMN42/smn42.c
Normal file
62
board/siemens/SMN42/smn42.c
Normal file
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com>
|
||||
* Armadillo board HT1070
|
||||
*
|
||||
* (C) Copyright 2007 Gary Jennejohn <garyj@denx.de>
|
||||
* Siemens board SMN42
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clps7111.h>
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
|
||||
/*
|
||||
* Miscellaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
int board_init (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* arch number MACH_TYPE_ARMADILLO - not official*/
|
||||
gd->bd->bi_arch_number = 83;
|
||||
|
||||
/* location of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x00000100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
||||
|
||||
return (0);
|
||||
}
|
55
board/siemens/SMN42/u-boot.lds
Normal file
55
board/siemens/SMN42/u-boot.lds
Normal file
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_start)
|
||||
SECTIONS
|
||||
{
|
||||
. = 0x00000000;
|
||||
|
||||
. = ALIGN(4);
|
||||
.text :
|
||||
{
|
||||
cpu/arm720t/start.o (.text)
|
||||
*(.text)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
.rodata : { *(.rodata) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.data : { *(.data) }
|
||||
|
||||
. = ALIGN(4);
|
||||
.got : { *(.got) }
|
||||
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_start = .;
|
||||
.bss : { *(.bss) }
|
||||
_end = .;
|
||||
}
|
|
@ -22,13 +22,12 @@
|
|||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
#
|
||||
# default CCARBAR is at 0xff700000
|
||||
# assume U-Boot is less than 0.5MB
|
||||
# U-Boot is less than 256K, so push
|
||||
# it further up into the flash
|
||||
#
|
||||
TEXT_BASE = 0xfffC0000
|
||||
TEXT_BASE = 0xFFFC0000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_E500=1
|
||||
|
|
|
@ -690,7 +690,7 @@ U_BOOT_CMD(
|
|||
);
|
||||
|
||||
U_BOOT_CMD(
|
||||
erase, 3, 1, do_flerase,
|
||||
erase, 3, 0, do_flerase,
|
||||
"erase - erase FLASH memory\n",
|
||||
"start end\n"
|
||||
" - erase FLASH from addr 'start' to addr 'end'\n"
|
||||
|
@ -704,7 +704,7 @@ U_BOOT_CMD(
|
|||
);
|
||||
|
||||
U_BOOT_CMD(
|
||||
protect, 4, 1, do_protect,
|
||||
protect, 4, 0, do_protect,
|
||||
"protect - enable or disable FLASH write protection\n",
|
||||
"on start end\n"
|
||||
" - protect FLASH from addr 'start' to addr 'end'\n"
|
||||
|
|
|
@ -514,11 +514,11 @@ void ide_init (void)
|
|||
unsigned char c;
|
||||
int i, bus;
|
||||
#if defined(CONFIG_AMIGAONEG3SE) || defined(CONFIG_SC3)
|
||||
unsigned int ata_reset_time;
|
||||
unsigned int ata_reset_time = ATA_RESET_TIME;
|
||||
char *s;
|
||||
#endif
|
||||
#ifdef CONFIG_AMIGAONEG3SE
|
||||
unsigned int max_bus_scan;
|
||||
char *s;
|
||||
#endif
|
||||
#ifdef CONFIG_IDE_8xx_PCCARD
|
||||
extern int pcmcia_on (void);
|
||||
|
|
|
@ -63,7 +63,7 @@ U_BOOT_CMD(
|
|||
#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */
|
||||
|
||||
U_BOOT_CMD(
|
||||
sleep , 2, 2, do_sleep,
|
||||
sleep , 2, 1, do_sleep,
|
||||
"sleep - delay execution for some time\n",
|
||||
"N\n"
|
||||
" - delay execution for N seconds (N is _decimal_ !!!)\n"
|
||||
|
|
|
@ -87,7 +87,7 @@ int do_pinit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
pinit, 2, 1, do_pinit,
|
||||
pinit, 2, 0, do_pinit,
|
||||
"pinit - PCMCIA sub-system\n",
|
||||
"on - power on PCMCIA socket\n"
|
||||
"pinit off - power off PCMCIA socket\n"
|
||||
|
|
|
@ -1336,7 +1336,7 @@ int run_command (const char *cmd, int flag)
|
|||
|
||||
/* Did the user stop this? */
|
||||
if (had_ctrlc ())
|
||||
return 0; /* if stopped then not repeatable */
|
||||
return -1; /* if stopped then not repeatable */
|
||||
}
|
||||
|
||||
return rc ? rc : repeatable;
|
||||
|
|
|
@ -36,6 +36,9 @@
|
|||
#ifdef CONFIG_IXP425 /* only valid for IXP425 */
|
||||
#include <asm/arch/ixp425.h>
|
||||
#endif
|
||||
#ifdef CONFIG_LPC2292
|
||||
#include <asm/arch/hardware.h>
|
||||
#endif
|
||||
#include <i2c.h>
|
||||
|
||||
#if defined(CONFIG_SOFT_I2C)
|
||||
|
|
50
cpu/arm720t/lpc2292/Makefile
Normal file
50
cpu/arm720t/lpc2292/Makefile
Normal file
|
@ -0,0 +1,50 @@
|
|||
#
|
||||
# (C) Copyright 2000-2007
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(SOC).a
|
||||
|
||||
COBJS = flash.o mmc.o mmc_hw.o spi.o
|
||||
SOBJS = $(obj)iap_entry.o
|
||||
|
||||
SRCS := $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
|
||||
all: $(obj).depend $(LIB)
|
||||
|
||||
$(LIB): $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
# this MUST be compiled as thumb code!
|
||||
$(SOBJS):
|
||||
$(CC) $(AFLAGS) -march=armv4t -c -o $(SOBJS) iap_entry.S
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
249
cpu/arm720t/lpc2292/flash.c
Normal file
249
cpu/arm720t/lpc2292/flash.c
Normal file
|
@ -0,0 +1,249 @@
|
|||
/*
|
||||
* (C) Copyright 2006 Embedded Artists AB <www.embeddedartists.com>
|
||||
*
|
||||
* Modified to remove all but the IAP-command related code by
|
||||
* Gary Jennejohn <garyj@denx.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
/* IAP commands use 32 bytes at the top of CPU internal sram, we
|
||||
use 512 bytes below that */
|
||||
#define COPY_BUFFER_LOCATION 0x40003de0
|
||||
|
||||
#define IAP_LOCATION 0x7ffffff1
|
||||
#define IAP_CMD_PREPARE 50
|
||||
#define IAP_CMD_COPY 51
|
||||
#define IAP_CMD_ERASE 52
|
||||
#define IAP_CMD_CHECK 53
|
||||
#define IAP_CMD_ID 54
|
||||
#define IAP_CMD_VERSION 55
|
||||
#define IAP_CMD_COMPARE 56
|
||||
|
||||
#define IAP_RET_CMD_SUCCESS 0
|
||||
|
||||
static unsigned long command[5];
|
||||
static unsigned long result[2];
|
||||
|
||||
extern void iap_entry(unsigned long * command, unsigned long * result);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
static int get_flash_sector(flash_info_t * info, ulong flash_addr)
|
||||
{
|
||||
int i;
|
||||
|
||||
for(i = 1; i < (info->sector_count); i++) {
|
||||
if (flash_addr < (info->start[i]))
|
||||
break;
|
||||
}
|
||||
|
||||
return (i-1);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* This function assumes that flash_addr is aligned on 512 bytes boundary
|
||||
* in flash. This function also assumes that prepare have been called
|
||||
* for the sector in question.
|
||||
*/
|
||||
int lpc2292_copy_buffer_to_flash(flash_info_t * info, ulong flash_addr)
|
||||
{
|
||||
int first_sector;
|
||||
int last_sector;
|
||||
|
||||
first_sector = get_flash_sector(info, flash_addr);
|
||||
last_sector = get_flash_sector(info, flash_addr + 512 - 1);
|
||||
|
||||
/* prepare sectors for write */
|
||||
command[0] = IAP_CMD_PREPARE;
|
||||
command[1] = first_sector;
|
||||
command[2] = last_sector;
|
||||
iap_entry(command, result);
|
||||
if (result[0] != IAP_RET_CMD_SUCCESS) {
|
||||
printf("IAP prepare failed\n");
|
||||
return ERR_PROG_ERROR;
|
||||
}
|
||||
|
||||
command[0] = IAP_CMD_COPY;
|
||||
command[1] = flash_addr;
|
||||
command[2] = COPY_BUFFER_LOCATION;
|
||||
command[3] = 512;
|
||||
command[4] = CFG_SYS_CLK_FREQ >> 10;
|
||||
iap_entry(command, result);
|
||||
if (result[0] != IAP_RET_CMD_SUCCESS) {
|
||||
printf("IAP copy failed\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
int lpc2292_flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
int flag;
|
||||
int prot;
|
||||
int sect;
|
||||
|
||||
prot = 0;
|
||||
for (sect = s_first; sect <= s_last; ++sect) {
|
||||
if (info->protect[sect]) {
|
||||
prot++;
|
||||
}
|
||||
}
|
||||
if (prot)
|
||||
return ERR_PROTECTED;
|
||||
|
||||
|
||||
flag = disable_interrupts();
|
||||
|
||||
printf ("Erasing %d sectors starting at sector %2d.\n"
|
||||
"This make take some time ... ",
|
||||
s_last - s_first + 1, s_first);
|
||||
|
||||
command[0] = IAP_CMD_PREPARE;
|
||||
command[1] = s_first;
|
||||
command[2] = s_last;
|
||||
iap_entry(command, result);
|
||||
if (result[0] != IAP_RET_CMD_SUCCESS) {
|
||||
printf("IAP prepare failed\n");
|
||||
return ERR_PROTECTED;
|
||||
}
|
||||
|
||||
command[0] = IAP_CMD_ERASE;
|
||||
command[1] = s_first;
|
||||
command[2] = s_last;
|
||||
command[3] = CFG_SYS_CLK_FREQ >> 10;
|
||||
iap_entry(command, result);
|
||||
if (result[0] != IAP_RET_CMD_SUCCESS) {
|
||||
printf("IAP erase failed\n");
|
||||
return ERR_PROTECTED;
|
||||
}
|
||||
|
||||
if (flag)
|
||||
enable_interrupts();
|
||||
|
||||
return ERR_OK;
|
||||
}
|
||||
|
||||
int lpc2292_write_buff (flash_info_t * info, uchar * src, ulong addr,
|
||||
ulong cnt)
|
||||
{
|
||||
int first_copy_size;
|
||||
int last_copy_size;
|
||||
int first_block;
|
||||
int last_block;
|
||||
int nbr_mid_blocks;
|
||||
uchar memmap_value;
|
||||
ulong i;
|
||||
uchar* src_org;
|
||||
uchar* dst_org;
|
||||
int ret = ERR_OK;
|
||||
|
||||
src_org = src;
|
||||
dst_org = (uchar*)addr;
|
||||
|
||||
first_block = addr / 512;
|
||||
last_block = (addr + cnt) / 512;
|
||||
nbr_mid_blocks = last_block - first_block - 1;
|
||||
|
||||
first_copy_size = 512 - (addr % 512);
|
||||
last_copy_size = (addr + cnt) % 512;
|
||||
|
||||
debug("\ncopy first block: (1) %lX -> %lX 0x200 bytes, "
|
||||
"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX 0x200 bytes\n",
|
||||
(ulong)(first_block * 512),
|
||||
(ulong)COPY_BUFFER_LOCATION,
|
||||
(ulong)src,
|
||||
(ulong)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
|
||||
first_copy_size,
|
||||
(ulong)COPY_BUFFER_LOCATION,
|
||||
(ulong)(first_block * 512));
|
||||
|
||||
/* copy first block */
|
||||
memcpy((void*)COPY_BUFFER_LOCATION,
|
||||
(void*)(first_block * 512), 512);
|
||||
memcpy((void*)(COPY_BUFFER_LOCATION + 512 - first_copy_size),
|
||||
src, first_copy_size);
|
||||
lpc2292_copy_buffer_to_flash(info, first_block * 512);
|
||||
src += first_copy_size;
|
||||
addr += first_copy_size;
|
||||
|
||||
/* copy middle blocks */
|
||||
for (i = 0; i < nbr_mid_blocks; i++) {
|
||||
debug("copy middle block: %lX -> %lX 512 bytes, "
|
||||
"%lX -> %lX 512 bytes\n",
|
||||
(ulong)src,
|
||||
(ulong)COPY_BUFFER_LOCATION,
|
||||
(ulong)COPY_BUFFER_LOCATION,
|
||||
(ulong)addr);
|
||||
|
||||
memcpy((void*)COPY_BUFFER_LOCATION, src, 512);
|
||||
lpc2292_copy_buffer_to_flash(info, addr);
|
||||
src += 512;
|
||||
addr += 512;
|
||||
}
|
||||
|
||||
|
||||
if (last_copy_size > 0) {
|
||||
debug("copy last block: (1) %lX -> %lX 0x200 bytes, "
|
||||
"(2) %lX -> %lX 0x%X bytes, (3) %lX -> %lX x200 bytes\n",
|
||||
(ulong)(last_block * 512),
|
||||
(ulong)COPY_BUFFER_LOCATION,
|
||||
(ulong)src,
|
||||
(ulong)(COPY_BUFFER_LOCATION),
|
||||
last_copy_size,
|
||||
(ulong)COPY_BUFFER_LOCATION,
|
||||
(ulong)addr);
|
||||
|
||||
/* copy last block */
|
||||
memcpy((void*)COPY_BUFFER_LOCATION,
|
||||
(void*)(last_block * 512), 512);
|
||||
memcpy((void*)COPY_BUFFER_LOCATION,
|
||||
src, last_copy_size);
|
||||
lpc2292_copy_buffer_to_flash(info, addr);
|
||||
}
|
||||
|
||||
/* verify write */
|
||||
memmap_value = GET8(MEMMAP);
|
||||
|
||||
disable_interrupts();
|
||||
|
||||
PUT8(MEMMAP, 01); /* we must make sure that initial 64
|
||||
bytes are taken from flash when we
|
||||
do the compare */
|
||||
|
||||
for (i = 0; i < cnt; i++) {
|
||||
if (*dst_org != *src_org){
|
||||
printf("Write failed. Byte %lX differs\n", i);
|
||||
ret = ERR_PROG_ERROR;
|
||||
break;
|
||||
}
|
||||
dst_org++;
|
||||
src_org++;
|
||||
}
|
||||
|
||||
PUT8(MEMMAP, memmap_value);
|
||||
enable_interrupts();
|
||||
|
||||
return ret;
|
||||
}
|
|
@ -23,7 +23,7 @@
|
|||
#include <part.h>
|
||||
#include <fat.h>
|
||||
#include "mmc_hw.h"
|
||||
#include "spi.h"
|
||||
#include <asm/arch/spi.h>
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
|
||||
|
@ -44,7 +44,7 @@ block_dev_desc_t * mmc_get_dev(int dev)
|
|||
unsigned long mmc_block_read(int dev,
|
||||
unsigned long start,
|
||||
lbaint_t blkcnt,
|
||||
unsigned long *buffer)
|
||||
void *buffer)
|
||||
{
|
||||
unsigned long rc = 0;
|
||||
unsigned char *p = (unsigned char *)buffer;
|
||||
|
@ -101,6 +101,9 @@ int mmc_init(int verbose)
|
|||
printf("mmc_init\n");
|
||||
|
||||
spi_init();
|
||||
/* this meeds to be done twice */
|
||||
mmc_hw_init();
|
||||
udelay(1000);
|
||||
mmc_hw_init();
|
||||
|
||||
mmc_hw_get_parameters();
|
|
@ -20,7 +20,7 @@
|
|||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include "spi.h"
|
||||
#include <asm/arch/spi.h>
|
||||
|
||||
#define MMC_Enable() PUT32(IO1CLR, 1l << 22)
|
||||
#define MMC_Disable() PUT32(IO1SET, 1l << 22)
|
|
@ -21,7 +21,7 @@
|
|||
#include <common.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include "spi.h"
|
||||
#include <asm/arch/spi.h>
|
||||
|
||||
unsigned long spi_flags;
|
||||
unsigned char spi_idle = 0x00;
|
|
@ -1,2 +0,0 @@
|
|||
.section .resetvec,"ax"
|
||||
b _start
|
|
@ -380,7 +380,7 @@ void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
|
|||
pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
|
||||
}
|
||||
|
||||
#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SOLIDCARD3))
|
||||
#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
|
||||
|
||||
/*
|
||||
*As is these functs get called out of flash Not a horrible
|
||||
|
|
|
@ -20,7 +20,7 @@
|
|||
* Jun Gu, Artesyn Technology, jung@artesyncp.com
|
||||
* Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
|
||||
*
|
||||
* (C) Copyright 2005
|
||||
* (C) Copyright 2005-2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
|
@ -42,6 +42,11 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/* define DEBUG for debugging output (obviously ;-)) */
|
||||
#if 0
|
||||
#define DEBUG
|
||||
#endif
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <i2c.h>
|
||||
|
@ -246,25 +251,6 @@
|
|||
#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
|
||||
#endif
|
||||
|
||||
const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
|
||||
{0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF},
|
||||
{0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000},
|
||||
{0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||
0x55555555, 0x55555555},
|
||||
{0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||
0xAAAAAAAA, 0xAAAAAAAA},
|
||||
{0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
|
||||
0x5A5A5A5A, 0x5A5A5A5A},
|
||||
{0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
|
||||
0xA5A5A5A5, 0xA5A5A5A5},
|
||||
{0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
|
||||
0x55AA55AA, 0x55AA55AA},
|
||||
{0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
|
||||
0xAA55AA55, 0xAA55AA55}
|
||||
};
|
||||
|
||||
/* bank_parms is used to sort the bank sizes by descending order */
|
||||
struct bank_param {
|
||||
unsigned long cr;
|
||||
|
@ -278,46 +264,37 @@ extern unsigned char cfg_simulate_spd_eeprom[128];
|
|||
#endif
|
||||
void program_tlb(u32 start, u32 size, u32 tlb_word2_i_value);
|
||||
|
||||
unsigned char spd_read(uchar chip, uint addr);
|
||||
static unsigned char spd_read(uchar chip, uint addr);
|
||||
static void get_spd_info(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
static void check_mem_type(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
static void check_volt_type(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
static void program_cfg0(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
static void program_cfg1(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
static void program_rtr(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
static void program_tr0(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
static void program_tr1(void);
|
||||
|
||||
void get_spd_info(unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
static void program_ecc(unsigned long num_bytes);
|
||||
#endif
|
||||
|
||||
void check_mem_type
|
||||
(unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
|
||||
void check_volt_type
|
||||
(unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
|
||||
void program_cfg0(unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
|
||||
void program_cfg1(unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
|
||||
void program_rtr (unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
|
||||
void program_tr0 (unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
|
||||
void program_tr1 (void);
|
||||
|
||||
void program_ecc (unsigned long num_bytes);
|
||||
|
||||
unsigned
|
||||
long program_bxcr(unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
static unsigned long program_bxcr(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks);
|
||||
|
||||
/*
|
||||
* This function is reading data from the DIMM module EEPROM over the SPD bus
|
||||
|
@ -328,7 +305,6 @@ long program_bxcr(unsigned long* dimm_populated,
|
|||
* BUG: Don't handle ECC memory
|
||||
* BUG: A few values in the TR register is currently hardcoded
|
||||
*/
|
||||
|
||||
long int spd_sdram(void) {
|
||||
unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
|
||||
unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
|
||||
|
@ -421,9 +397,8 @@ long int spd_sdram(void) {
|
|||
*/
|
||||
while (1) {
|
||||
mfsdram(mem_mcsts, mcsts);
|
||||
if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
|
||||
if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -431,14 +406,17 @@ long int spd_sdram(void) {
|
|||
*/
|
||||
program_tr1();
|
||||
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
/*
|
||||
* if ECC is enabled, initialize parity bits
|
||||
* If ecc is enabled, initialize the parity bits.
|
||||
*/
|
||||
program_ecc(total_size);
|
||||
#endif
|
||||
|
||||
return total_size;
|
||||
}
|
||||
|
||||
unsigned char spd_read(uchar chip, uint addr)
|
||||
static unsigned char spd_read(uchar chip, uint addr)
|
||||
{
|
||||
unsigned char data[2];
|
||||
|
||||
|
@ -460,9 +438,9 @@ unsigned char spd_read(uchar chip, uint addr)
|
|||
return 0;
|
||||
}
|
||||
|
||||
void get_spd_info(unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
static void get_spd_info(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
{
|
||||
unsigned long dimm_num;
|
||||
unsigned long dimm_found;
|
||||
|
@ -480,14 +458,10 @@ void get_spd_info(unsigned long* dimm_populated,
|
|||
if ((num_of_bytes != 0) && (total_size != 0)) {
|
||||
dimm_populated[dimm_num] = TRUE;
|
||||
dimm_found = TRUE;
|
||||
#if 0
|
||||
printf("DIMM slot %lu: populated\n", dimm_num);
|
||||
#endif
|
||||
debug("DIMM slot %lu: populated\n", dimm_num);
|
||||
} else {
|
||||
dimm_populated[dimm_num] = FALSE;
|
||||
#if 0
|
||||
printf("DIMM slot %lu: Not populated\n", dimm_num);
|
||||
#endif
|
||||
debug("DIMM slot %lu: Not populated\n", dimm_num);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -497,9 +471,9 @@ void get_spd_info(unsigned long* dimm_populated,
|
|||
}
|
||||
}
|
||||
|
||||
void check_mem_type(unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
static void check_mem_type(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
{
|
||||
unsigned long dimm_num;
|
||||
unsigned char dimm_type;
|
||||
|
@ -509,9 +483,7 @@ void check_mem_type(unsigned long* dimm_populated,
|
|||
dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
|
||||
switch (dimm_type) {
|
||||
case 7:
|
||||
#if 0
|
||||
printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
|
||||
#endif
|
||||
debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
|
||||
break;
|
||||
default:
|
||||
printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
|
||||
|
@ -525,10 +497,9 @@ void check_mem_type(unsigned long* dimm_populated,
|
|||
}
|
||||
}
|
||||
|
||||
|
||||
void check_volt_type(unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
static void check_volt_type(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
{
|
||||
unsigned long dimm_num;
|
||||
unsigned long voltage_type;
|
||||
|
@ -541,18 +512,16 @@ void check_volt_type(unsigned long* dimm_populated,
|
|||
dimm_num);
|
||||
hang();
|
||||
} else {
|
||||
#if 0
|
||||
printf("DIMM %lu voltage level supported.\n", dimm_num);
|
||||
#endif
|
||||
debug("DIMM %lu voltage level supported.\n", dimm_num);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void program_cfg0(unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
static void program_cfg0(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
{
|
||||
unsigned long dimm_num;
|
||||
unsigned long cfg0;
|
||||
|
@ -640,9 +609,9 @@ void program_cfg0(unsigned long* dimm_populated,
|
|||
mtsdram(mem_cfg0, cfg0);
|
||||
}
|
||||
|
||||
void program_cfg1(unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
static void program_cfg1(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
{
|
||||
unsigned long cfg1;
|
||||
mfsdram(mem_cfg1, cfg1);
|
||||
|
@ -658,9 +627,9 @@ void program_cfg1(unsigned long* dimm_populated,
|
|||
mtsdram(mem_cfg1, cfg1);
|
||||
}
|
||||
|
||||
void program_rtr (unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
static void program_rtr(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
{
|
||||
unsigned long dimm_num;
|
||||
unsigned long bus_period_x_10;
|
||||
|
@ -676,7 +645,6 @@ void program_rtr (unsigned long* dimm_populated,
|
|||
get_sys_info(&sys_info);
|
||||
bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
|
||||
|
||||
|
||||
for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
|
||||
if (dimm_populated[dimm_num] == TRUE) {
|
||||
refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
|
||||
|
@ -719,9 +687,9 @@ void program_rtr (unsigned long* dimm_populated,
|
|||
mtsdram(mem_rtr, sdram_rtr);
|
||||
}
|
||||
|
||||
void program_tr0 (unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
static void program_tr0(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
{
|
||||
unsigned long dimm_num;
|
||||
unsigned long tr0;
|
||||
|
@ -1001,13 +969,73 @@ void program_tr0 (unsigned long* dimm_populated,
|
|||
break;
|
||||
}
|
||||
|
||||
#if 0
|
||||
printf("tr0: %x\n", tr0);
|
||||
#endif
|
||||
debug("tr0: %x\n", tr0);
|
||||
mtsdram(mem_tr0, tr0);
|
||||
}
|
||||
|
||||
void program_tr1 (void)
|
||||
static int short_mem_test(void)
|
||||
{
|
||||
unsigned long i, j;
|
||||
unsigned long bxcr_num;
|
||||
unsigned long *membase;
|
||||
const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
|
||||
{0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||
0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
|
||||
{0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
|
||||
0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
|
||||
{0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
|
||||
0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
|
||||
{0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
|
||||
0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
|
||||
{0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
|
||||
0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
|
||||
{0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
|
||||
0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
|
||||
{0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
|
||||
0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
|
||||
{0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
|
||||
0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
|
||||
|
||||
for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
|
||||
mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
|
||||
if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
|
||||
/* Bank is enabled */
|
||||
membase = (unsigned long*)
|
||||
(mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
|
||||
|
||||
/*
|
||||
* Run the short memory test
|
||||
*/
|
||||
for (i = 0; i < NUMMEMTESTS; i++) {
|
||||
for (j = 0; j < NUMMEMWORDS; j++) {
|
||||
membase[j] = test[i][j];
|
||||
ppcDcbf((unsigned long)&(membase[j]));
|
||||
}
|
||||
|
||||
for (j = 0; j < NUMMEMWORDS; j++) {
|
||||
if (membase[j] != test[i][j]) {
|
||||
ppcDcbf((unsigned long)&(membase[j]));
|
||||
return 0;
|
||||
}
|
||||
ppcDcbf((unsigned long)&(membase[j]));
|
||||
}
|
||||
|
||||
if (j < NUMMEMWORDS)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* see if the rdclt value passed
|
||||
*/
|
||||
if (i < NUMMEMTESTS)
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void program_tr1(void)
|
||||
{
|
||||
unsigned long tr0;
|
||||
unsigned long tr1;
|
||||
|
@ -1015,8 +1043,7 @@ void program_tr1 (void)
|
|||
unsigned long ecc_temp;
|
||||
unsigned long dlycal;
|
||||
unsigned long dly_val;
|
||||
unsigned long i, j, k;
|
||||
unsigned long bxcr_num;
|
||||
unsigned long k;
|
||||
unsigned long max_pass_length;
|
||||
unsigned long current_pass_length;
|
||||
unsigned long current_fail_length;
|
||||
|
@ -1029,7 +1056,6 @@ void program_tr1 (void)
|
|||
unsigned char window_found;
|
||||
unsigned char fail_found;
|
||||
unsigned char pass_found;
|
||||
unsigned long * membase;
|
||||
PPC440_SYS_INFO sys_info;
|
||||
|
||||
/*
|
||||
|
@ -1079,55 +1105,16 @@ void program_tr1 (void)
|
|||
window_found = FALSE;
|
||||
fail_found = FALSE;
|
||||
pass_found = FALSE;
|
||||
#ifdef DEBUG
|
||||
printf("Starting memory test ");
|
||||
#endif
|
||||
debug("Starting memory test ");
|
||||
|
||||
for (k = 0; k < NUMHALFCYCLES; k++) {
|
||||
for (rdclt = 0; rdclt < dly_val; rdclt++) {
|
||||
for (rdclt = 0; rdclt < dly_val; rdclt++) {
|
||||
/*
|
||||
* Set the timing reg for the test.
|
||||
*/
|
||||
mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
|
||||
|
||||
for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
|
||||
mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
|
||||
if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
|
||||
/* Bank is enabled */
|
||||
membase = (unsigned long*)
|
||||
(mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
|
||||
|
||||
/*
|
||||
* Run the short memory test
|
||||
*/
|
||||
for (i = 0; i < NUMMEMTESTS; i++) {
|
||||
for (j = 0; j < NUMMEMWORDS; j++) {
|
||||
membase[j] = test[i][j];
|
||||
ppcDcbf((unsigned long)&(membase[j]));
|
||||
}
|
||||
|
||||
for (j = 0; j < NUMMEMWORDS; j++) {
|
||||
if (membase[j] != test[i][j]) {
|
||||
ppcDcbf((unsigned long)&(membase[j]));
|
||||
break;
|
||||
}
|
||||
ppcDcbf((unsigned long)&(membase[j]));
|
||||
}
|
||||
|
||||
if (j < NUMMEMWORDS) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* see if the rdclt value passed
|
||||
*/
|
||||
if (i < NUMMEMTESTS) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (bxcr_num == MAXBXCR) {
|
||||
if (short_mem_test()) {
|
||||
if (fail_found == TRUE) {
|
||||
pass_found = TRUE;
|
||||
if (current_pass_length == 0) {
|
||||
|
@ -1157,9 +1144,8 @@ void program_tr1 (void)
|
|||
}
|
||||
}
|
||||
}
|
||||
#ifdef DEBUG
|
||||
printf(".");
|
||||
#endif
|
||||
debug(".");
|
||||
|
||||
if (window_found == TRUE) {
|
||||
break;
|
||||
}
|
||||
|
@ -1167,9 +1153,7 @@ void program_tr1 (void)
|
|||
tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
|
||||
rdclt_offset += dly_val;
|
||||
}
|
||||
#ifdef DEBUG
|
||||
printf("\n");
|
||||
#endif
|
||||
debug("\n");
|
||||
|
||||
/*
|
||||
* make sure we find the window
|
||||
|
@ -1218,18 +1202,17 @@ void program_tr1 (void)
|
|||
}
|
||||
tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
|
||||
|
||||
#if 0
|
||||
printf("tr1: %x\n", tr1);
|
||||
#endif
|
||||
debug("tr1: %x\n", tr1);
|
||||
|
||||
/*
|
||||
* program SDRAM Timing Register 1 TR1
|
||||
*/
|
||||
mtsdram(mem_tr1, tr1);
|
||||
}
|
||||
|
||||
unsigned long program_bxcr(unsigned long* dimm_populated,
|
||||
unsigned char* iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
static unsigned long program_bxcr(unsigned long *dimm_populated,
|
||||
unsigned char *iic0_dimm_addr,
|
||||
unsigned long num_dimm_banks)
|
||||
{
|
||||
unsigned long dimm_num;
|
||||
unsigned long bank_base_addr;
|
||||
|
@ -1262,8 +1245,8 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
|
|||
#ifdef CONFIG_BAMBOO
|
||||
/*
|
||||
* This next section is hardware dependent and must be programmed
|
||||
* to match the hardware. For bammboo, the following holds...
|
||||
* 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0
|
||||
* to match the hardware. For bamboo, the following holds...
|
||||
* 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard)
|
||||
* 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
|
||||
* 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
|
||||
* 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
|
||||
|
@ -1273,10 +1256,12 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
|
|||
ctrl_bank_num[1] = 1;
|
||||
ctrl_bank_num[2] = 3;
|
||||
#else
|
||||
/*
|
||||
* Ocotea, Ebony and the other IBM/AMCC eval boards have
|
||||
* 2 DIMM slots with each max 2 banks
|
||||
*/
|
||||
ctrl_bank_num[0] = 0;
|
||||
ctrl_bank_num[1] = 1;
|
||||
ctrl_bank_num[2] = 2;
|
||||
ctrl_bank_num[3] = 3;
|
||||
ctrl_bank_num[1] = 2;
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
@ -1290,6 +1275,8 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
|
|||
num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
|
||||
num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
|
||||
bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
|
||||
debug("DIMM%d: row=%d col=%d banks=%d\n", dimm_num,
|
||||
num_row_addr, num_col_addr, num_banks);
|
||||
|
||||
/*
|
||||
* Set the SDRAM0_BxCR regs
|
||||
|
@ -1354,9 +1341,12 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
|
|||
cr |= SDRAM_BXCR_SDBE;
|
||||
|
||||
for (i = 0; i < num_banks; i++) {
|
||||
bank_parms[ctrl_bank_num[dimm_num]+i+dimm_num].bank_size_bytes =
|
||||
(4 * 1024 * 1024) * bank_size_id;
|
||||
bank_parms[ctrl_bank_num[dimm_num]+i+dimm_num].cr = cr;
|
||||
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
|
||||
(4 << 20) * bank_size_id;
|
||||
bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
|
||||
debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
|
||||
dimm_num, i, ctrl_bank_num[dimm_num]+i,
|
||||
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -1400,13 +1390,15 @@ unsigned long program_bxcr(unsigned long* dimm_populated,
|
|||
bank_parms[sorted_bank_num[bx_cr_num]].cr;
|
||||
mtdcr(memcfgd, temp);
|
||||
bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
|
||||
debug("SDRAM0_B%dCR=0x%08lx\n", sorted_bank_num[bx_cr_num], temp);
|
||||
}
|
||||
}
|
||||
|
||||
return(bank_base_addr);
|
||||
}
|
||||
|
||||
void program_ecc (unsigned long num_bytes)
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
static void program_ecc(unsigned long num_bytes)
|
||||
{
|
||||
unsigned long bank_base_addr;
|
||||
unsigned long current_address;
|
||||
|
@ -1425,14 +1417,12 @@ void program_ecc (unsigned long num_bytes)
|
|||
bank_base_addr = CFG_SDRAM_BASE;
|
||||
|
||||
if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
|
||||
mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
|
||||
SDRAM_CFG0_MCHK_GEN);
|
||||
mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN);
|
||||
|
||||
if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
|
||||
if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32)
|
||||
address_increment = 4;
|
||||
} else {
|
||||
else
|
||||
address_increment = 8;
|
||||
}
|
||||
|
||||
current_address = (unsigned long)(bank_base_addr);
|
||||
end_address = (unsigned long)(bank_base_addr) + num_bytes;
|
||||
|
@ -1446,4 +1436,5 @@ void program_ecc (unsigned long num_bytes)
|
|||
SDRAM_CFG0_MCHK_CHK);
|
||||
}
|
||||
}
|
||||
#endif /* CONFIG_DDR_ECC */
|
||||
#endif /* CONFIG_SPD_EEPROM */
|
||||
|
|
|
@ -465,7 +465,11 @@ long int initdram(int board_type)
|
|||
* Set the SDRAM Clock Timing Register
|
||||
*-----------------------------------------------------------------*/
|
||||
mfsdram(SDRAM_CLKTR, val);
|
||||
#ifdef CFG_44x_DDR2_CKTR_180
|
||||
mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_180_DEG_ADV);
|
||||
#else
|
||||
mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) | SDRAM_CLKTR_CLKP_0_DEG);
|
||||
#endif
|
||||
|
||||
/*------------------------------------------------------------------
|
||||
* Program the BxCF registers.
|
||||
|
@ -1117,7 +1121,8 @@ static void program_codt(unsigned long *dimm_populated,
|
|||
modt3 = 0x00000000;
|
||||
}
|
||||
if (total_rank == 4) {
|
||||
codt |= CALC_ODT_R(0) | CALC_ODT_R(1) | CALC_ODT_R(2) | CALC_ODT_R(3);
|
||||
codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
|
||||
CALC_ODT_R(2) | CALC_ODT_R(3);
|
||||
modt0 = CALC_ODT_RW(2);
|
||||
modt1 = 0x00000000;
|
||||
modt2 = CALC_ODT_RW(0);
|
||||
|
|
|
@ -139,6 +139,7 @@ static char *bootstrap_str[] = {
|
|||
"Reserved",
|
||||
"I2C (Addr 0x50)",
|
||||
};
|
||||
static char bootstrap_char[] = { 'A', 'B', 'C', 'B', 'D', 'E', 'x', 'F' };
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
|
||||
|
@ -149,6 +150,7 @@ static char *bootstrap_str[] = {
|
|||
"I2C (Addr 0x54)",
|
||||
"I2C (Addr 0x50)",
|
||||
};
|
||||
static char bootstrap_char[] = { 'A', 'B', 'C', 'D'};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
|
||||
|
@ -163,6 +165,7 @@ static char *bootstrap_str[] = {
|
|||
"PCI",
|
||||
"I2C (Addr 0x52)",
|
||||
};
|
||||
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
|
@ -177,6 +180,7 @@ static char *bootstrap_str[] = {
|
|||
"PCI",
|
||||
"I2C (Addr 0x52)",
|
||||
};
|
||||
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_405EZ)
|
||||
|
@ -199,6 +203,8 @@ static char *bootstrap_str[] = {
|
|||
"SPI (slow)",
|
||||
"I2C (Addr 0x50)",
|
||||
};
|
||||
static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', \
|
||||
'I', 'x', 'K', 'L', 'M', 'N', 'O', 'P' };
|
||||
#endif
|
||||
|
||||
#if defined(SDR0_PINSTP_SHIFT)
|
||||
|
@ -427,7 +433,7 @@ int checkcpu (void)
|
|||
printf (" I2C boot EEPROM %sabled\n", i2c_bootrom_enabled() ? "en" : "dis");
|
||||
#endif /* I2C_BOOTROM */
|
||||
#if defined(SDR0_PINSTP_SHIFT)
|
||||
printf (" Bootstrap Option %c - ", (char)bootstrap_option() + 'A');
|
||||
printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
|
||||
printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]);
|
||||
#endif /* SDR0_PINSTP_SHIFT */
|
||||
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
* Platform independend driver for NDFC (NanD Flash Controller)
|
||||
* integrated into EP440 cores
|
||||
*
|
||||
* (C) Copyright 2006
|
||||
* (C) Copyright 2006-2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* Based on original work by
|
||||
|
@ -38,7 +38,9 @@
|
|||
|
||||
#include <nand.h>
|
||||
#include <linux/mtd/ndfc.h>
|
||||
#include <linux/mtd/nand_ecc.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
#include <ppc4xx.h>
|
||||
|
||||
static u8 hwctl = 0;
|
||||
|
@ -70,11 +72,11 @@ static void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte)
|
|||
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
|
||||
|
||||
if (hwctl & 0x1)
|
||||
out8(base + NDFC_CMD, byte);
|
||||
out_8((u8 *)(base + NDFC_CMD), byte);
|
||||
else if (hwctl & 0x2)
|
||||
out8(base + NDFC_ALE, byte);
|
||||
out_8((u8 *)(base + NDFC_ALE), byte);
|
||||
else
|
||||
out8(base + NDFC_DATA, byte);
|
||||
out_8((u8 *)(base + NDFC_DATA), byte);
|
||||
}
|
||||
|
||||
static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
|
||||
|
@ -82,7 +84,7 @@ static u_char ndfc_read_byte(struct mtd_info *mtdinfo)
|
|||
struct nand_chip *this = mtdinfo->priv;
|
||||
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
|
||||
|
||||
return (in8(base + NDFC_DATA));
|
||||
return (in_8((u8 *)(base + NDFC_DATA)));
|
||||
}
|
||||
|
||||
static int ndfc_dev_ready(struct mtd_info *mtdinfo)
|
||||
|
@ -90,17 +92,41 @@ static int ndfc_dev_ready(struct mtd_info *mtdinfo)
|
|||
struct nand_chip *this = mtdinfo->priv;
|
||||
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
|
||||
|
||||
while (!(in32(base + NDFC_STAT) & NDFC_STAT_IS_READY))
|
||||
while (!(in_be32((u32 *)(base + NDFC_STAT)) & NDFC_STAT_IS_READY))
|
||||
;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
/*
|
||||
* Don't use these speedup functions in NAND boot image, since the image
|
||||
* has to fit into 4kByte.
|
||||
*/
|
||||
static void ndfc_enable_hwecc(struct mtd_info *mtdinfo, int mode)
|
||||
{
|
||||
struct nand_chip *this = mtdinfo->priv;
|
||||
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
|
||||
u32 ccr;
|
||||
|
||||
ccr = in_be32((u32 *)(base + NDFC_CCR));
|
||||
ccr |= NDFC_CCR_RESET_ECC;
|
||||
out_be32((u32 *)(base + NDFC_CCR), ccr);
|
||||
}
|
||||
|
||||
static int ndfc_calculate_ecc(struct mtd_info *mtdinfo,
|
||||
const u_char *dat, u_char *ecc_code)
|
||||
{
|
||||
struct nand_chip *this = mtdinfo->priv;
|
||||
ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc;
|
||||
u32 ecc;
|
||||
u8 *p = (u8 *)&ecc;
|
||||
|
||||
ecc = in_be32((u32 *)(base + NDFC_ECC));
|
||||
|
||||
/* The NDFC uses Smart Media (SMC) bytes order
|
||||
*/
|
||||
ecc_code[0] = p[2];
|
||||
ecc_code[1] = p[1];
|
||||
ecc_code[2] = p[3];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Speedups for buffer read/write/verify
|
||||
|
@ -116,9 +142,14 @@ static void ndfc_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
|
|||
uint32_t *p = (uint32_t *) buf;
|
||||
|
||||
for (;len > 0; len -= 4)
|
||||
*p++ = in32(base + NDFC_DATA);
|
||||
*p++ = in_be32((u32 *)(base + NDFC_DATA));
|
||||
}
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
/*
|
||||
* Don't use these speedup functions in NAND boot image, since the image
|
||||
* has to fit into 4kByte.
|
||||
*/
|
||||
static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
|
||||
{
|
||||
struct nand_chip *this = mtdinfo->priv;
|
||||
|
@ -126,7 +157,7 @@ static void ndfc_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
|
|||
uint32_t *p = (uint32_t *) buf;
|
||||
|
||||
for (; len > 0; len -= 4)
|
||||
out32(base + NDFC_DATA, *p++);
|
||||
out_be32((u32 *)(base + NDFC_DATA), *p++);
|
||||
}
|
||||
|
||||
static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
|
||||
|
@ -136,7 +167,7 @@ static int ndfc_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len
|
|||
uint32_t *p = (uint32_t *) buf;
|
||||
|
||||
for (; len > 0; len -= 4)
|
||||
if (*p++ != in32(base + NDFC_DATA))
|
||||
if (*p++ != in_be32((u32 *)(base + NDFC_DATA)))
|
||||
return -1;
|
||||
|
||||
return 0;
|
||||
|
@ -153,8 +184,8 @@ void board_nand_select_device(struct nand_chip *nand, int chip)
|
|||
ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
|
||||
|
||||
/* Set NandFlash Core Configuration Register */
|
||||
/* 1col x 2 rows */
|
||||
out32(base + NDFC_CCR, 0x00000000 | (cs << 24));
|
||||
/* 1 col x 2 rows */
|
||||
out_be32((u32 *)(base + NDFC_CCR), 0x00000000 | (cs << 24));
|
||||
}
|
||||
|
||||
int board_nand_init(struct nand_chip *nand)
|
||||
|
@ -162,16 +193,19 @@ int board_nand_init(struct nand_chip *nand)
|
|||
int cs = (ulong)nand->IO_ADDR_W & 0x00000003;
|
||||
ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc;
|
||||
|
||||
nand->eccmode = NAND_ECC_SOFT;
|
||||
|
||||
nand->hwcontrol = ndfc_hwcontrol;
|
||||
nand->read_byte = ndfc_read_byte;
|
||||
nand->read_buf = ndfc_read_buf;
|
||||
nand->write_byte = ndfc_write_byte;
|
||||
nand->dev_ready = ndfc_dev_ready;
|
||||
|
||||
nand->eccmode = NAND_ECC_HW3_256;
|
||||
nand->enable_hwecc = ndfc_enable_hwecc;
|
||||
nand->calculate_ecc = ndfc_calculate_ecc;
|
||||
nand->correct_data = nand_correct_data;
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
nand->write_buf = ndfc_write_buf;
|
||||
nand->read_buf = ndfc_read_buf;
|
||||
nand->verify_buf = ndfc_verify_buf;
|
||||
#else
|
||||
/*
|
||||
|
@ -187,7 +221,7 @@ int board_nand_init(struct nand_chip *nand)
|
|||
* Select required NAND chip in NDFC
|
||||
*/
|
||||
board_nand_select_device(nand, cs);
|
||||
out32(base + NDFC_BCFG0 + (cs << 2), 0x80002222);
|
||||
out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), 0x80002222);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -110,6 +110,13 @@
|
|||
# endif
|
||||
#endif /* CFG_INIT_DCACHE_CS */
|
||||
|
||||
#define function_prolog(func_name) .text; \
|
||||
.align 2; \
|
||||
.globl func_name; \
|
||||
func_name:
|
||||
#define function_epilog(func_name) .type func_name,@function; \
|
||||
.size func_name,.-func_name
|
||||
|
||||
/* We don't want the MMU yet.
|
||||
*/
|
||||
#undef MSR_KERNEL
|
||||
|
@ -148,7 +155,9 @@
|
|||
* NAND U-Boot image is started from offset 0
|
||||
*/
|
||||
.text
|
||||
#if defined(CONFIG_440)
|
||||
bl reconfig_tlb0
|
||||
#endif
|
||||
GET_GOT
|
||||
bl cpu_init_f /* run low-level CPU init code (from Flash) */
|
||||
bl board_init_f
|
||||
|
@ -388,8 +397,9 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
|
|||
2:
|
||||
|
||||
#if defined(CONFIG_NAND_SPL)
|
||||
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
|
||||
/*
|
||||
* Enable internal SRAM
|
||||
* Enable internal SRAM (only on 440EPx/GRx, 440EP/GR have no OCM)
|
||||
*/
|
||||
lis r2,0x7fff
|
||||
ori r2,r2,0xffff
|
||||
|
@ -399,6 +409,45 @@ rsttlb: tlbwe r0,r1,0x0000 /* Invalidate all entries (V=0)*/
|
|||
mfdcr r1,isram0_pmeg
|
||||
and r1,r1,r2 /* Disable pwr mgmt */
|
||||
mtdcr isram0_pmeg,r1
|
||||
#endif
|
||||
#if defined(CONFIG_440EP)
|
||||
/*
|
||||
* On 440EP with no internal SRAM, we setup SDRAM very early
|
||||
* and copy the NAND_SPL to SDRAM and jump to it
|
||||
*/
|
||||
/* Clear Dcache to use as RAM */
|
||||
addis r3,r0,CFG_INIT_RAM_ADDR@h
|
||||
ori r3,r3,CFG_INIT_RAM_ADDR@l
|
||||
addis r4,r0,CFG_INIT_RAM_END@h
|
||||
ori r4,r4,CFG_INIT_RAM_END@l
|
||||
rlwinm. r5,r4,0,27,31
|
||||
rlwinm r5,r4,27,5,31
|
||||
beq ..d_ran3
|
||||
addi r5,r5,0x0001
|
||||
..d_ran3:
|
||||
mtctr r5
|
||||
..d_ag3:
|
||||
dcbz r0,r3
|
||||
addi r3,r3,32
|
||||
bdnz ..d_ag3
|
||||
/*----------------------------------------------------------------*/
|
||||
/* Setup the stack in internal SRAM */
|
||||
/*----------------------------------------------------------------*/
|
||||
lis r1,CFG_INIT_RAM_ADDR@h
|
||||
ori r1,r1,CFG_INIT_SP_OFFSET@l
|
||||
li r0,0
|
||||
stwu r0,-4(r1)
|
||||
stwu r0,-4(r1) /* Terminate call chain */
|
||||
|
||||
stwu r1,-8(r1) /* Save back chain and move SP */
|
||||
lis r0,RESET_VECTOR@h /* Address of reset vector */
|
||||
ori r0,r0, RESET_VECTOR@l
|
||||
stwu r1,-8(r1) /* Save back chain and move SP */
|
||||
stw r0,+12(r1) /* Save return addr (underflow vect) */
|
||||
sync
|
||||
bl early_sdram_init
|
||||
sync
|
||||
#endif /* CONFIG_440EP */
|
||||
|
||||
/*
|
||||
* Copy SPL from cache into internal SRAM
|
||||
|
@ -429,7 +478,7 @@ spl_loop:
|
|||
start_ram:
|
||||
sync
|
||||
isync
|
||||
#endif
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
|
||||
bl 3f
|
||||
b _start
|
||||
|
@ -810,6 +859,38 @@ _start:
|
|||
#endif /* CONFIG_405EZ */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
/*
|
||||
* Copy SPL from cache into internal SRAM
|
||||
*/
|
||||
li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1
|
||||
mtctr r4
|
||||
lis r2,CFG_NAND_BOOT_SPL_SRC@h
|
||||
ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l
|
||||
lis r3,CFG_NAND_BOOT_SPL_DST@h
|
||||
ori r3,r3,CFG_NAND_BOOT_SPL_DST@l
|
||||
spl_loop:
|
||||
lwzu r4,4(r2)
|
||||
stwu r4,4(r3)
|
||||
bdnz spl_loop
|
||||
|
||||
/*
|
||||
* Jump to code in RAM
|
||||
*/
|
||||
bl 00f
|
||||
00: mflr r10
|
||||
lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h
|
||||
ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l
|
||||
sub r10,r10,r3
|
||||
addi r10,r10,28
|
||||
mtlr r10
|
||||
blr
|
||||
|
||||
start_ram:
|
||||
sync
|
||||
isync
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
|
||||
/*----------------------------------------------------------------------- */
|
||||
/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
|
||||
/*----------------------------------------------------------------------- */
|
||||
|
@ -920,12 +1001,16 @@ _start:
|
|||
stw r0, +12(r1) /* Save return addr (underflow vect) */
|
||||
#endif /* !(CFG_INIT_DCACHE_CS || !CFG_TEM_STACK_OCM) */
|
||||
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
bl nand_boot /* will not return */
|
||||
#else
|
||||
GET_GOT /* initialize GOT access */
|
||||
|
||||
bl cpu_init_f /* run low-level CPU init code (from Flash) */
|
||||
|
||||
/* NEVER RETURNS! */
|
||||
bl board_init_f /* run first part of init code (from Flash) */
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
|
||||
#endif /* CONFIG_405GP || CONFIG_405CR || CONFIG_405 || CONFIG_405EP */
|
||||
/*----------------------------------------------------------------------- */
|
||||
|
@ -1137,27 +1222,9 @@ crit_return:
|
|||
lwz r1,GPR1(r1)
|
||||
SYNC
|
||||
rfci
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
|
||||
/* Cache functions.
|
||||
*/
|
||||
invalidate_icache:
|
||||
iccci r0,r0 /* for 405, iccci invalidates the */
|
||||
blr /* entire I cache */
|
||||
|
||||
invalidate_dcache:
|
||||
addi r6,0,0x0000 /* clear GPR 6 */
|
||||
/* Do loop for # of dcache congruence classes. */
|
||||
lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
|
||||
ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
|
||||
/* NOTE: dccci invalidates both */
|
||||
mtctr r7 /* ways in the D cache */
|
||||
..dcloop:
|
||||
dccci 0,r6 /* invalidate line */
|
||||
addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
|
||||
bdnz ..dcloop
|
||||
blr
|
||||
|
||||
flush_dcache:
|
||||
addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
|
||||
ori r9,r9,0x8000
|
||||
|
@ -1254,24 +1321,6 @@ wr_tcr:
|
|||
mtspr tcr, r3
|
||||
blr
|
||||
|
||||
/*------------------------------------------------------------------------------- */
|
||||
/* Function: in8 */
|
||||
/* Description: Input 8 bits */
|
||||
/*------------------------------------------------------------------------------- */
|
||||
.globl in8
|
||||
in8:
|
||||
lbz r3,0x0000(r3)
|
||||
blr
|
||||
|
||||
/*------------------------------------------------------------------------------- */
|
||||
/* Function: out8 */
|
||||
/* Description: Output 8 bits */
|
||||
/*------------------------------------------------------------------------------- */
|
||||
.globl out8
|
||||
out8:
|
||||
stb r4,0x0000(r3)
|
||||
blr
|
||||
|
||||
/*------------------------------------------------------------------------------- */
|
||||
/* Function: out16 */
|
||||
/* Description: Output 16 bits */
|
||||
|
@ -1290,15 +1339,6 @@ out16r:
|
|||
sthbrx r4,r0,r3
|
||||
blr
|
||||
|
||||
/*------------------------------------------------------------------------------- */
|
||||
/* Function: out32 */
|
||||
/* Description: Output 32 bits */
|
||||
/*------------------------------------------------------------------------------- */
|
||||
.globl out32
|
||||
out32:
|
||||
stw r4,0x0000(r3)
|
||||
blr
|
||||
|
||||
/*------------------------------------------------------------------------------- */
|
||||
/* Function: out32r */
|
||||
/* Description: Byte reverse and output 32 bits */
|
||||
|
@ -1326,15 +1366,6 @@ in16r:
|
|||
lhbrx r3,r0,r3
|
||||
blr
|
||||
|
||||
/*------------------------------------------------------------------------------- */
|
||||
/* Function: in32 */
|
||||
/* Description: Input 32 bits */
|
||||
/*------------------------------------------------------------------------------- */
|
||||
.globl in32
|
||||
in32:
|
||||
lwz 3,0x0000(3)
|
||||
blr
|
||||
|
||||
/*------------------------------------------------------------------------------- */
|
||||
/* Function: in32r */
|
||||
/* Description: Input 32 bits and byte reverse */
|
||||
|
@ -1377,9 +1408,6 @@ ppcSync:
|
|||
sync
|
||||
blr
|
||||
|
||||
/*------------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
/*
|
||||
* void relocate_code (addr_sp, gd, addr_moni)
|
||||
*
|
||||
|
@ -1644,8 +1672,105 @@ trap_reloc:
|
|||
stw r0, 4(r7)
|
||||
|
||||
blr
|
||||
|
||||
#if defined(CONFIG_440)
|
||||
/*----------------------------------------------------------------------------+
|
||||
| dcbz_area.
|
||||
+----------------------------------------------------------------------------*/
|
||||
function_prolog(dcbz_area)
|
||||
rlwinm. r5,r4,0,27,31
|
||||
rlwinm r5,r4,27,5,31
|
||||
beq ..d_ra2
|
||||
addi r5,r5,0x0001
|
||||
..d_ra2:mtctr r5
|
||||
..d_ag2:dcbz r0,r3
|
||||
addi r3,r3,32
|
||||
bdnz ..d_ag2
|
||||
sync
|
||||
blr
|
||||
function_epilog(dcbz_area)
|
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| dflush. Assume 32K at vector address is cachable.
|
||||
+----------------------------------------------------------------------------*/
|
||||
function_prolog(dflush)
|
||||
mfmsr r9
|
||||
rlwinm r8,r9,0,15,13
|
||||
rlwinm r8,r8,0,17,15
|
||||
mtmsr r8
|
||||
addi r3,r0,0x0000
|
||||
mtspr dvlim,r3
|
||||
mfspr r3,ivpr
|
||||
addi r4,r0,1024
|
||||
mtctr r4
|
||||
..dflush_loop:
|
||||
lwz r6,0x0(r3)
|
||||
addi r3,r3,32
|
||||
bdnz ..dflush_loop
|
||||
addi r3,r3,-32
|
||||
mtctr r4
|
||||
..ag: dcbf r0,r3
|
||||
addi r3,r3,-32
|
||||
bdnz ..ag
|
||||
sync
|
||||
mtmsr r9
|
||||
blr
|
||||
function_epilog(dflush)
|
||||
#endif /* CONFIG_440 */
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
|
||||
/*------------------------------------------------------------------------------- */
|
||||
/* Function: in8 */
|
||||
/* Description: Input 8 bits */
|
||||
/*------------------------------------------------------------------------------- */
|
||||
.globl in8
|
||||
in8:
|
||||
lbz r3,0x0000(r3)
|
||||
blr
|
||||
|
||||
/*------------------------------------------------------------------------------- */
|
||||
/* Function: out8 */
|
||||
/* Description: Output 8 bits */
|
||||
/*------------------------------------------------------------------------------- */
|
||||
.globl out8
|
||||
out8:
|
||||
stb r4,0x0000(r3)
|
||||
blr
|
||||
|
||||
/*------------------------------------------------------------------------------- */
|
||||
/* Function: out32 */
|
||||
/* Description: Output 32 bits */
|
||||
/*------------------------------------------------------------------------------- */
|
||||
.globl out32
|
||||
out32:
|
||||
stw r4,0x0000(r3)
|
||||
blr
|
||||
|
||||
/*------------------------------------------------------------------------------- */
|
||||
/* Function: in32 */
|
||||
/* Description: Input 32 bits */
|
||||
/*------------------------------------------------------------------------------- */
|
||||
.globl in32
|
||||
in32:
|
||||
lwz 3,0x0000(3)
|
||||
blr
|
||||
|
||||
invalidate_icache:
|
||||
iccci r0,r0 /* for 405, iccci invalidates the */
|
||||
blr /* entire I cache */
|
||||
|
||||
invalidate_dcache:
|
||||
addi r6,0,0x0000 /* clear GPR 6 */
|
||||
/* Do loop for # of dcache congruence classes. */
|
||||
lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */
|
||||
ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l
|
||||
/* NOTE: dccci invalidates both */
|
||||
mtctr r7 /* ways in the D cache */
|
||||
..dcloop:
|
||||
dccci 0,r6 /* invalidate line */
|
||||
addi r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
|
||||
bdnz ..dcloop
|
||||
blr
|
||||
|
||||
/**************************************************************************/
|
||||
/* PPC405EP specific stuff */
|
||||
|
@ -1892,13 +2017,6 @@ pll_wait:
|
|||
#endif /* CONFIG_405EP */
|
||||
|
||||
#if defined(CONFIG_440)
|
||||
#define function_prolog(func_name) .text; \
|
||||
.align 2; \
|
||||
.globl func_name; \
|
||||
func_name:
|
||||
#define function_epilog(func_name) .type func_name,@function; \
|
||||
.size func_name,.-func_name
|
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| mttlb3.
|
||||
+----------------------------------------------------------------------------*/
|
||||
|
@ -1946,47 +2064,4 @@ pll_wait:
|
|||
TLBRE(3,3,0)
|
||||
blr
|
||||
function_epilog(mftlb1)
|
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| dcbz_area.
|
||||
+----------------------------------------------------------------------------*/
|
||||
function_prolog(dcbz_area)
|
||||
rlwinm. r5,r4,0,27,31
|
||||
rlwinm r5,r4,27,5,31
|
||||
beq ..d_ra2
|
||||
addi r5,r5,0x0001
|
||||
..d_ra2:mtctr r5
|
||||
..d_ag2:dcbz r0,r3
|
||||
addi r3,r3,32
|
||||
bdnz ..d_ag2
|
||||
sync
|
||||
blr
|
||||
function_epilog(dcbz_area)
|
||||
|
||||
/*----------------------------------------------------------------------------+
|
||||
| dflush. Assume 32K at vector address is cachable.
|
||||
+----------------------------------------------------------------------------*/
|
||||
function_prolog(dflush)
|
||||
mfmsr r9
|
||||
rlwinm r8,r9,0,15,13
|
||||
rlwinm r8,r8,0,17,15
|
||||
mtmsr r8
|
||||
addi r3,r0,0x0000
|
||||
mtspr dvlim,r3
|
||||
mfspr r3,ivpr
|
||||
addi r4,r0,1024
|
||||
mtctr r4
|
||||
..dflush_loop:
|
||||
lwz r6,0x0(r3)
|
||||
addi r3,r3,32
|
||||
bdnz ..dflush_loop
|
||||
addi r3,r3,-32
|
||||
mtctr r4
|
||||
..ag: dcbf r0,r3
|
||||
addi r3,r3,-32
|
||||
bdnz ..ag
|
||||
sync
|
||||
mtmsr r9
|
||||
blr
|
||||
function_epilog(dflush)
|
||||
#endif /* CONFIG_440 */
|
||||
|
|
7
disk/part.c
Normal file → Executable file
7
disk/part.c
Normal file → Executable file
|
@ -180,6 +180,7 @@ void dev_print (block_dev_desc_t *dev_desc)
|
|||
(CONFIG_COMMANDS & CFG_CMD_SCSI) || \
|
||||
(CONFIG_COMMANDS & CFG_CMD_USB) || \
|
||||
defined(CONFIG_MMC) || \
|
||||
(defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \
|
||||
defined(CONFIG_SYSTEMACE) )
|
||||
|
||||
#if defined(CONFIG_MAC_PARTITION) || \
|
||||
|
@ -219,7 +220,8 @@ void init_part (block_dev_desc_t * dev_desc)
|
|||
}
|
||||
|
||||
|
||||
int get_partition_info (block_dev_desc_t *dev_desc, int part, disk_partition_t *info)
|
||||
int get_partition_info (block_dev_desc_t *dev_desc, int part
|
||||
, disk_partition_t *info)
|
||||
{
|
||||
switch (dev_desc->part_type) {
|
||||
#ifdef CONFIG_MAC_PARTITION
|
||||
|
@ -325,7 +327,8 @@ void print_part (block_dev_desc_t * dev_desc)
|
|||
|
||||
|
||||
#else /* neither MAC nor DOS nor ISO partition configured */
|
||||
# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION nor CONFIG_ISO_PARTITION configured!
|
||||
# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION
|
||||
# error nor CONFIG_ISO_PARTITION configured!
|
||||
#endif
|
||||
|
||||
#endif /* (CONFIG_COMMANDS & CFG_CMD_IDE) || CONFIG_COMMANDS & CFG_CMD_SCSI) */
|
||||
|
|
|
@ -96,14 +96,17 @@ To Flash U-Boot into the booting bank (0xFFC00000 - 0xFFFFFFFF):
|
|||
|
||||
tftp 1000000 u-boot.bin
|
||||
protect off all
|
||||
erase fff00000 ffffffff
|
||||
cp.b 1000000 fff00100 80000
|
||||
erase fff00000 +$filesize
|
||||
cp.b 1000000 fff00000 $filesize
|
||||
|
||||
or use tftpflash command:
|
||||
run tftpflash
|
||||
|
||||
To Flash U-boot into the alternative bank (0xFF800000 - 0xFFBFFFFF):
|
||||
|
||||
tftp 1000000 u-boot.bin
|
||||
erase ffb00000 ffbfffff
|
||||
cp.b 1000000 ffb00100 80000
|
||||
erase ffb00000 +$filesize
|
||||
cp.b 1000000 ffb00000 $filesize
|
||||
|
||||
|
||||
4. Memory Map
|
||||
|
|
|
@ -30,7 +30,7 @@ LIB = $(obj)libdrivers.a
|
|||
COBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \
|
||||
bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
|
||||
cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
|
||||
e1000.o eepro100.o \
|
||||
e1000.o eepro100.o enc28j60.o \
|
||||
i8042.o inca-ip_sw.o keyboard.o \
|
||||
lan91c96.o macb.o \
|
||||
natsemi.o ne2000.o netarm_eth.o netconsole.o \
|
||||
|
|
236
board/lpc2292sodimm/eth.c → drivers/enc28j60.c
Normal file → Executable file
236
board/lpc2292sodimm/eth.c → drivers/enc28j60.c
Normal file → Executable file
|
@ -17,9 +17,10 @@
|
|||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#ifdef CONFIG_ENC28J60
|
||||
#include <net.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include "spi.h"
|
||||
#include <asm/arch/spi.h>
|
||||
|
||||
/*
|
||||
* Control Registers in Bank 0
|
||||
|
@ -36,7 +37,7 @@
|
|||
#define CTL_REG_ERXSTL 0x08
|
||||
#define CTL_REG_ERXSTH 0x09
|
||||
#define CTL_REG_ERXNDL 0x0A
|
||||
#define CTL_REG_ERXNDA 0x0B
|
||||
#define CTL_REG_ERXNDH 0x0B
|
||||
#define CTL_REG_ERXRDPTL 0x0C
|
||||
#define CTL_REG_ERXRDPTH 0x0D
|
||||
#define CTL_REG_ERXWRPTL 0x0E
|
||||
|
@ -137,7 +138,10 @@
|
|||
|
||||
#define PHY_REG_PHID1 0x02
|
||||
#define PHY_REG_PHID2 0x03
|
||||
|
||||
/* taken from the Linux driver */
|
||||
#define PHY_REG_PHCON1 0x00
|
||||
#define PHY_REG_PHCON2 0x10
|
||||
#define PHY_REG_PHLCON 0x14
|
||||
|
||||
/*
|
||||
* Receive Filter Register (ERXFCON) bits
|
||||
|
@ -274,6 +278,9 @@
|
|||
/* Use the lower memory for receiver buffer. See errata pt. 5 */
|
||||
#define ENC_RX_BUF_START 0x0000
|
||||
#define ENC_TX_BUF_START 0x1800
|
||||
/* taken from the Linux driver */
|
||||
#define ENC_RX_BUF_END 0x17ff
|
||||
#define ENC_TX_BUF_END 0x1fff
|
||||
|
||||
/* maximum frame length */
|
||||
#define ENC_MAX_FRM_LEN 1518
|
||||
|
@ -293,6 +300,7 @@ static void encBitClr (unsigned char regNo, unsigned char data);
|
|||
static void encReset (void);
|
||||
static void encInit (unsigned char *pEthAddr);
|
||||
static unsigned short phyRead (unsigned char addr);
|
||||
static void phyWrite(unsigned char, unsigned short);
|
||||
static void encPoll (void);
|
||||
static void encRx (void);
|
||||
|
||||
|
@ -318,10 +326,12 @@ static int rxResetCounter = 0;
|
|||
#define RX_RESET_COUNTER 1000;
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Returns 0 when failes otherwize 1
|
||||
* Always returns 0
|
||||
*/
|
||||
int eth_init (bd_t * bis)
|
||||
{
|
||||
unsigned char estatVal;
|
||||
|
||||
/* configure GPIO */
|
||||
(*((volatile unsigned long *) IO1DIR)) |= ENC_SPI_SLAVE_CS;
|
||||
(*((volatile unsigned long *) IO1DIR)) |= ENC_RESET;
|
||||
|
@ -332,6 +342,14 @@ int eth_init (bd_t * bis)
|
|||
|
||||
spi_init ();
|
||||
|
||||
/* taken from the Linux driver - dangerous stuff here! */
|
||||
/* Wait for CLKRDY to become set (i.e., check that we can communicate with
|
||||
the ENC) */
|
||||
do
|
||||
{
|
||||
estatVal = m_nic_read(CTL_REG_ESTAT);
|
||||
} while ((estatVal & 0x08) || (~estatVal & ENC_ESTAT_CLKRDY));
|
||||
|
||||
/* initialize controller */
|
||||
encReset ();
|
||||
encInit (bis->bi_enetaddr);
|
||||
|
@ -353,6 +371,10 @@ int eth_send (volatile void *packet, int length)
|
|||
m_nic_write (CTL_REG_EWRPTL, (ENC_TX_BUF_START & 0xff));
|
||||
m_nic_write (CTL_REG_EWRPTH, (ENC_TX_BUF_START >> 8));
|
||||
|
||||
/* set ETXND */
|
||||
m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
|
||||
m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
|
||||
|
||||
/* set ETXST */
|
||||
m_nic_write (CTL_REG_ETXSTL, ENC_TX_BUF_START & 0xFF);
|
||||
m_nic_write (CTL_REG_ETXSTH, ENC_TX_BUF_START >> 8);
|
||||
|
@ -360,9 +382,15 @@ int eth_send (volatile void *packet, int length)
|
|||
/* write packet */
|
||||
m_nic_write_data (length, (unsigned char *) packet);
|
||||
|
||||
/* set ETXND */
|
||||
m_nic_write (CTL_REG_ETXNDL, (length + ENC_TX_BUF_START) & 0xFF);
|
||||
m_nic_write (CTL_REG_ETXNDH, (length + ENC_TX_BUF_START) >> 8);
|
||||
/* taken from the Linux driver */
|
||||
/* Verify that the internal transmit logic has not been altered by excessive
|
||||
collisions. See Errata B4 12 and 14.
|
||||
*/
|
||||
if (m_nic_read(CTL_REG_EIR) & ENC_EIR_TXERIF) {
|
||||
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_TXRST);
|
||||
m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_TXRST);
|
||||
}
|
||||
m_nic_bfc(CTL_REG_EIR, (ENC_EIR_TXERIF | ENC_EIR_TXIF));
|
||||
|
||||
/* set ECON1.TXRTS */
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_TXRTS);
|
||||
|
@ -423,8 +451,10 @@ static void encPoll (void)
|
|||
volatile unsigned char estat_reg;
|
||||
unsigned char pkt_cnt;
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* clear global interrupt enable bit in enc28j60 */
|
||||
m_nic_bfc (CTL_REG_EIE, ENC_EIE_INTIE);
|
||||
#endif
|
||||
estat_reg = m_nic_read (CTL_REG_ESTAT);
|
||||
|
||||
eir_reg = m_nic_read (CTL_REG_EIR);
|
||||
|
@ -462,8 +492,10 @@ static void encPoll (void)
|
|||
m_nic_bfc (CTL_REG_EIR, ENC_EIR_TXERIF);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* set global interrupt enable bit in enc28j60 */
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void encRx (void)
|
||||
|
@ -473,6 +505,7 @@ static void encRx (void)
|
|||
unsigned short status;
|
||||
unsigned char eir_reg;
|
||||
unsigned char pkt_cnt = 0;
|
||||
unsigned short rxbuf_rdpt;
|
||||
|
||||
/* switch to bank 0 */
|
||||
m_nic_bfc (CTL_REG_ECON1, (ENC_ECON1_BSEL1 | ENC_ECON1_BSEL0));
|
||||
|
@ -489,18 +522,19 @@ static void encRx (void)
|
|||
status = buffer[4];
|
||||
status |= (unsigned short) buffer[5] << 8;
|
||||
|
||||
if (pkt_len <= ENC_MAX_FRM_LEN) {
|
||||
if (pkt_len <= ENC_MAX_FRM_LEN)
|
||||
copy_len = pkt_len;
|
||||
} else {
|
||||
else
|
||||
copy_len = 0;
|
||||
/* p_priv->stats.rx_dropped++; */
|
||||
/* we will drop this packet */
|
||||
}
|
||||
|
||||
if ((status & (1L << 7)) == 0) { /* check Received Ok bit */
|
||||
if ((status & (1L << 7)) == 0) /* check Received Ok bit */
|
||||
copy_len = 0;
|
||||
|
||||
/* taken from the Linux driver */
|
||||
/* check if next pointer is resonable */
|
||||
if ((((unsigned int)next_pointer_msb << 8) |
|
||||
(unsigned int)next_pointer_lsb) >= ENC_TX_BUF_START)
|
||||
copy_len = 0;
|
||||
/* p_priv->stats.rx_errors++; */
|
||||
}
|
||||
|
||||
if (copy_len > 0) {
|
||||
m_nic_read_data (copy_len, buffer);
|
||||
|
@ -513,6 +547,22 @@ static void encRx (void)
|
|||
/* decrease packet counter */
|
||||
m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_PKTDEC);
|
||||
|
||||
/* taken from the Linux driver */
|
||||
/* Only odd values should be written to ERXRDPTL,
|
||||
* see errata B4 pt.13
|
||||
*/
|
||||
rxbuf_rdpt = (next_pointer_msb << 8 | next_pointer_lsb) - 1;
|
||||
if ((rxbuf_rdpt < (m_nic_read(CTL_REG_ERXSTH) << 8 |
|
||||
m_nic_read(CTL_REG_ERXSTL))) || (rxbuf_rdpt >
|
||||
(m_nic_read(CTL_REG_ERXNDH) << 8 |
|
||||
m_nic_read(CTL_REG_ERXNDL)))) {
|
||||
m_nic_write(CTL_REG_ERXRDPTL, m_nic_read(CTL_REG_ERXNDL));
|
||||
m_nic_write(CTL_REG_ERXRDPTH, m_nic_read(CTL_REG_ERXNDH));
|
||||
} else {
|
||||
m_nic_write(CTL_REG_ERXRDPTL, rxbuf_rdpt & 0xFF);
|
||||
m_nic_write(CTL_REG_ERXRDPTH, rxbuf_rdpt >> 8);
|
||||
}
|
||||
|
||||
/* move to bank 1 */
|
||||
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
|
@ -535,8 +585,6 @@ static void encRx (void)
|
|||
|
||||
eir_reg = m_nic_read (CTL_REG_EIR);
|
||||
} while (pkt_cnt); /* Use EPKTCNT not EIR.PKTIF flag, see errata pt. 6 */
|
||||
m_nic_write (CTL_REG_ERXRDPTL, next_pointer_lsb);
|
||||
m_nic_write (CTL_REG_ERXRDPTH, next_pointer_msb);
|
||||
}
|
||||
|
||||
static void encWriteReg (unsigned char regNo, unsigned char data)
|
||||
|
@ -700,12 +748,6 @@ static void encReset (void)
|
|||
|
||||
/* sleep 1 ms. See errata pt. 2 */
|
||||
udelay (1000);
|
||||
|
||||
#if 0
|
||||
(*((volatile unsigned long *) IO1CLR)) &= ENC_RESET;
|
||||
mdelay (5);
|
||||
(*((volatile unsigned long *) IO1SET)) &= ENC_RESET;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void encInit (unsigned char *pEthAddr)
|
||||
|
@ -720,44 +762,21 @@ static void encInit (unsigned char *pEthAddr)
|
|||
* Setup the buffer space. The reset values are valid for the
|
||||
* other pointers.
|
||||
*/
|
||||
#if 0
|
||||
/* We shall not write to ERXST, see errata pt. 5. Instead we
|
||||
have to make sure that ENC_RX_BUS_START is 0. */
|
||||
m_nic_write_retry (CTL_REG_ERXSTL, (ENC_RX_BUF_START & 0xFF), 1);
|
||||
m_nic_write_retry (CTL_REG_ERXSTH, (ENC_RX_BUF_START >> 8), 1);
|
||||
#endif
|
||||
|
||||
/* taken from the Linux driver */
|
||||
m_nic_write_retry (CTL_REG_ERXNDL, (ENC_RX_BUF_END & 0xFF), 1);
|
||||
m_nic_write_retry (CTL_REG_ERXNDH, (ENC_RX_BUF_END >> 8), 1);
|
||||
|
||||
m_nic_write_retry (CTL_REG_ERDPTL, (ENC_RX_BUF_START & 0xFF), 1);
|
||||
m_nic_write_retry (CTL_REG_ERDPTH, (ENC_RX_BUF_START >> 8), 1);
|
||||
|
||||
next_pointer_lsb = (ENC_RX_BUF_START & 0xFF);
|
||||
next_pointer_msb = (ENC_RX_BUF_START >> 8);
|
||||
|
||||
/*
|
||||
* For tracking purposes, the ERXRDPT registers should be programmed with
|
||||
* the same value. This is the read pointer.
|
||||
*/
|
||||
m_nic_write (CTL_REG_ERXRDPTL, (ENC_RX_BUF_START & 0xFF));
|
||||
m_nic_write_retry (CTL_REG_ERXRDPTH, (ENC_RX_BUF_START >> 8), 1);
|
||||
|
||||
/* Setup receive filters. */
|
||||
|
||||
/* move to bank 1 */
|
||||
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
|
||||
/* OR-filtering, Unicast, CRC-check and broadcast */
|
||||
m_nic_write_retry (CTL_REG_ERXFCON,
|
||||
(ENC_RFR_UCEN | ENC_RFR_CRCEN | ENC_RFR_BCEN), 1);
|
||||
|
||||
/* Wait for Oscillator Start-up Timer (OST). */
|
||||
while ((m_nic_read (CTL_REG_ESTAT) & ENC_ESTAT_CLKRDY) == 0) {
|
||||
static int cnt = 0;
|
||||
|
||||
if (cnt++ >= 1000) {
|
||||
cnt = 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* verify identification */
|
||||
phid1 = phyRead (PHY_REG_PHID1);
|
||||
phid2 = phyRead (PHY_REG_PHID2);
|
||||
|
@ -780,16 +799,34 @@ static void encInit (unsigned char *pEthAddr)
|
|||
/* switch to bank 2 */
|
||||
m_nic_bfc (CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
m_nic_bfs (CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
/* clear MAC reset bits */
|
||||
m_nic_write_retry (CTL_REG_MACON2, 0, 1);
|
||||
|
||||
/* enable MAC to receive frames */
|
||||
m_nic_write_retry (CTL_REG_MACON1, ENC_MACON1_MARXEN, 10);
|
||||
/* added some bits from the Linux driver */
|
||||
m_nic_write_retry (CTL_REG_MACON1
|
||||
,(ENC_MACON1_MARXEN | ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS)
|
||||
,10);
|
||||
|
||||
/* configure pad, tx-crc and duplex */
|
||||
/* TODO maybe enable FRMLNEN */
|
||||
m_nic_write_retry (CTL_REG_MACON3,
|
||||
(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN), 10);
|
||||
/* added a bit from the Linux driver */
|
||||
m_nic_write_retry (CTL_REG_MACON3
|
||||
,(ENC_MACON3_PADCFG0 | ENC_MACON3_TXCRCEN | ENC_MACON3_FRMLNEN)
|
||||
,10);
|
||||
|
||||
/* added 4 new lines from the Linux driver */
|
||||
/* Allow infinite deferals if the medium is continously busy */
|
||||
m_nic_write_retry(CTL_REG_MACON4, (1<<6) /*ENC_MACON4_DEFER*/, 10);
|
||||
|
||||
/* Late collisions occur beyond 63 bytes */
|
||||
m_nic_write_retry(CTL_REG_MACLCON2, 63, 10);
|
||||
|
||||
/* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
|
||||
m_nic_write_retry(CTL_REG_MAIPGL, 0x12, 10);
|
||||
|
||||
/*
|
||||
* Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
|
||||
* 0x0c for half-duplex. Nothing for full-duplex
|
||||
*/
|
||||
m_nic_write_retry(CTL_REG_MAIPGH, 0x0C, 10);
|
||||
|
||||
/* set maximum frame length */
|
||||
m_nic_write_retry (CTL_REG_MAMXFLL, (ENC_MAX_FRM_LEN & 0xff), 10);
|
||||
|
@ -801,15 +838,6 @@ static void encInit (unsigned char *pEthAddr)
|
|||
*/
|
||||
m_nic_write_retry (CTL_REG_MABBIPG, 0x12, 10);
|
||||
|
||||
/* Set (low byte) Non-Back-to_Back Inter-Packet Gap. Recommended 0x12 */
|
||||
m_nic_write_retry (CTL_REG_MAIPGL, 0x12, 10);
|
||||
|
||||
/*
|
||||
* Set (high byte) Non-Back-to_Back Inter-Packet Gap. Recommended
|
||||
* 0x0c for half-duplex. Nothing for full-duplex
|
||||
*/
|
||||
m_nic_write_retry (CTL_REG_MAIPGH, 0x0C, 10);
|
||||
|
||||
/* set MAC address */
|
||||
|
||||
/* switch to bank 3 */
|
||||
|
@ -822,19 +850,36 @@ static void encInit (unsigned char *pEthAddr)
|
|||
m_nic_write_retry (CTL_REG_MAADR4, pEthAddr[1], 1);
|
||||
m_nic_write_retry (CTL_REG_MAADR5, pEthAddr[0], 1);
|
||||
|
||||
/*
|
||||
* PHY Initialization taken from the Linux driver
|
||||
*/
|
||||
|
||||
/* Prevent automatic loopback of data beeing transmitted by setting
|
||||
ENC_PHCON2_HDLDIS */
|
||||
phyWrite(PHY_REG_PHCON2, (1<<8));
|
||||
|
||||
/* LEDs configuration
|
||||
* LEDA: LACFG = 0100 -> display link status
|
||||
* LEDB: LBCFG = 0111 -> display TX & RX activity
|
||||
* STRCH = 1 -> LED pulses
|
||||
*/
|
||||
phyWrite(PHY_REG_PHLCON, 0x0472);
|
||||
|
||||
/* Reset PDPXMD-bit => half duplex */
|
||||
phyWrite(PHY_REG_PHCON1, 0);
|
||||
|
||||
/*
|
||||
* Receive settings
|
||||
*/
|
||||
|
||||
/* auto-increment RX-pointer when reading a received packet */
|
||||
m_nic_bfs (CTL_REG_ECON2, ENC_ECON2_AUTOINC);
|
||||
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
/* enable interrupts */
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_PKTIE);
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXIE);
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_RXERIE);
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_TXERIE);
|
||||
m_nic_bfs (CTL_REG_EIE, ENC_EIE_INTIE);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
|
@ -864,6 +909,11 @@ static unsigned short phyRead (unsigned char addr)
|
|||
/* set MICMD.MIIRD */
|
||||
m_nic_write (CTL_REG_MICMD, ENC_MICMD_MIIRD);
|
||||
|
||||
/* taken from the Linux driver */
|
||||
/* move to bank 3 */
|
||||
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
|
||||
/* poll MISTAT.BUSY bit until operation is complete */
|
||||
while ((m_nic_read (CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
|
||||
static int cnt = 0;
|
||||
|
@ -875,6 +925,11 @@ static unsigned short phyRead (unsigned char addr)
|
|||
}
|
||||
}
|
||||
|
||||
/* taken from the Linux driver */
|
||||
/* move to bank 2 */
|
||||
m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
|
||||
/* clear MICMD.MIIRD */
|
||||
m_nic_write (CTL_REG_MICMD, 0);
|
||||
|
||||
|
@ -883,3 +938,46 @@ static unsigned short phyRead (unsigned char addr)
|
|||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*****************************************************************************
|
||||
*
|
||||
* Taken from the Linux driver.
|
||||
* Description:
|
||||
* Write PHY registers.
|
||||
*
|
||||
* NOTE! This function will change to Bank 3.
|
||||
*
|
||||
* Params:
|
||||
* [in] addr address of the register to write to
|
||||
* [in] data to be written
|
||||
*
|
||||
* Returns:
|
||||
* None
|
||||
*/
|
||||
static void phyWrite(unsigned char addr, unsigned short data)
|
||||
{
|
||||
/* move to bank 2 */
|
||||
m_nic_bfc(CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
|
||||
/* write address to MIREGADR */
|
||||
m_nic_write(CTL_REG_MIREGADR, addr);
|
||||
|
||||
m_nic_write(CTL_REG_MIWRL, data & 0xff);
|
||||
m_nic_write(CTL_REG_MIWRH, data >> 8);
|
||||
|
||||
/* move to bank 3 */
|
||||
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL0);
|
||||
m_nic_bfs(CTL_REG_ECON1, ENC_ECON1_BSEL1);
|
||||
|
||||
/* poll MISTAT.BUSY bit until operation is complete */
|
||||
while((m_nic_read(CTL_REG_MISTAT) & ENC_MISTAT_BUSY) != 0) {
|
||||
static int cnt = 0;
|
||||
|
||||
if(cnt++ >= 1000) {
|
||||
cnt = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ENC28J60 */
|
|
@ -40,6 +40,13 @@
|
|||
#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
|
||||
|
||||
#include<linux/mtd/mtd.h>
|
||||
|
||||
/*
|
||||
* NAND-SPL has no sofware ECC for now, so don't include nand_calculate_ecc(),
|
||||
* only nand_correct_data() is needed
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
/*
|
||||
* Pre-calculated 256-way 1 byte column parity
|
||||
*/
|
||||
|
@ -62,90 +69,75 @@ static const u_char nand_ecc_precalc_table[] = {
|
|||
0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
|
||||
};
|
||||
|
||||
|
||||
/**
|
||||
* nand_trans_result - [GENERIC] create non-inverted ECC
|
||||
* @reg2: line parity reg 2
|
||||
* @reg3: line parity reg 3
|
||||
* @ecc_code: ecc
|
||||
*
|
||||
* Creates non-inverted ECC code from line parity
|
||||
*/
|
||||
static void nand_trans_result(u_char reg2, u_char reg3,
|
||||
u_char *ecc_code)
|
||||
{
|
||||
u_char a, b, i, tmp1, tmp2;
|
||||
|
||||
/* Initialize variables */
|
||||
a = b = 0x80;
|
||||
tmp1 = tmp2 = 0;
|
||||
|
||||
/* Calculate first ECC byte */
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */
|
||||
tmp1 |= b;
|
||||
b >>= 1;
|
||||
if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */
|
||||
tmp1 |= b;
|
||||
b >>= 1;
|
||||
a >>= 1;
|
||||
}
|
||||
|
||||
/* Calculate second ECC byte */
|
||||
b = 0x80;
|
||||
for (i = 0; i < 4; i++) {
|
||||
if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */
|
||||
tmp2 |= b;
|
||||
b >>= 1;
|
||||
if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */
|
||||
tmp2 |= b;
|
||||
b >>= 1;
|
||||
a >>= 1;
|
||||
}
|
||||
|
||||
/* Store two of the ECC bytes */
|
||||
ecc_code[0] = tmp1;
|
||||
ecc_code[1] = tmp2;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_calculate_ecc - [NAND Interface] Calculate 3 byte ECC code for 256 byte block
|
||||
* nand_calculate_ecc - [NAND Interface] Calculate 3-byte ECC for 256-byte block
|
||||
* @mtd: MTD block structure
|
||||
* @dat: raw data
|
||||
* @ecc_code: buffer for ECC
|
||||
*/
|
||||
int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
|
||||
int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
|
||||
u_char *ecc_code)
|
||||
{
|
||||
u_char idx, reg1, reg2, reg3;
|
||||
int j;
|
||||
uint8_t idx, reg1, reg2, reg3, tmp1, tmp2;
|
||||
int i;
|
||||
|
||||
/* Initialize variables */
|
||||
reg1 = reg2 = reg3 = 0;
|
||||
ecc_code[0] = ecc_code[1] = ecc_code[2] = 0;
|
||||
|
||||
/* Build up column parity */
|
||||
for(j = 0; j < 256; j++) {
|
||||
|
||||
for(i = 0; i < 256; i++) {
|
||||
/* Get CP0 - CP5 from table */
|
||||
idx = nand_ecc_precalc_table[dat[j]];
|
||||
idx = nand_ecc_precalc_table[*dat++];
|
||||
reg1 ^= (idx & 0x3f);
|
||||
|
||||
/* All bit XOR = 1 ? */
|
||||
if (idx & 0x40) {
|
||||
reg3 ^= (u_char) j;
|
||||
reg2 ^= ~((u_char) j);
|
||||
reg3 ^= (uint8_t) i;
|
||||
reg2 ^= ~((uint8_t) i);
|
||||
}
|
||||
}
|
||||
|
||||
/* Create non-inverted ECC code from line parity */
|
||||
nand_trans_result(reg2, reg3, ecc_code);
|
||||
tmp1 = (reg3 & 0x80) >> 0; /* B7 -> B7 */
|
||||
tmp1 |= (reg2 & 0x80) >> 1; /* B7 -> B6 */
|
||||
tmp1 |= (reg3 & 0x40) >> 1; /* B6 -> B5 */
|
||||
tmp1 |= (reg2 & 0x40) >> 2; /* B6 -> B4 */
|
||||
tmp1 |= (reg3 & 0x20) >> 2; /* B5 -> B3 */
|
||||
tmp1 |= (reg2 & 0x20) >> 3; /* B5 -> B2 */
|
||||
tmp1 |= (reg3 & 0x10) >> 3; /* B4 -> B1 */
|
||||
tmp1 |= (reg2 & 0x10) >> 4; /* B4 -> B0 */
|
||||
|
||||
tmp2 = (reg3 & 0x08) << 4; /* B3 -> B7 */
|
||||
tmp2 |= (reg2 & 0x08) << 3; /* B3 -> B6 */
|
||||
tmp2 |= (reg3 & 0x04) << 3; /* B2 -> B5 */
|
||||
tmp2 |= (reg2 & 0x04) << 2; /* B2 -> B4 */
|
||||
tmp2 |= (reg3 & 0x02) << 2; /* B1 -> B3 */
|
||||
tmp2 |= (reg2 & 0x02) << 1; /* B1 -> B2 */
|
||||
tmp2 |= (reg3 & 0x01) << 1; /* B0 -> B1 */
|
||||
tmp2 |= (reg2 & 0x01) << 0; /* B7 -> B0 */
|
||||
|
||||
/* Calculate final ECC code */
|
||||
ecc_code[0] = ~ecc_code[0];
|
||||
ecc_code[1] = ~ecc_code[1];
|
||||
#ifdef CONFIG_MTD_NAND_ECC_SMC
|
||||
ecc_code[0] = ~tmp2;
|
||||
ecc_code[1] = ~tmp1;
|
||||
#else
|
||||
ecc_code[0] = ~tmp1;
|
||||
ecc_code[1] = ~tmp2;
|
||||
#endif
|
||||
ecc_code[2] = ((~reg1) << 2) | 0x03;
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_NAND_SPL */
|
||||
|
||||
static inline int countbits(uint32_t byte)
|
||||
{
|
||||
int res = 0;
|
||||
|
||||
for (;byte; byte >>= 1)
|
||||
res += byte & 0x01;
|
||||
return res;
|
||||
}
|
||||
|
||||
/**
|
||||
* nand_correct_data - [NAND Interface] Detect and correct bit error(s)
|
||||
|
@ -156,88 +148,52 @@ int nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code
|
|||
*
|
||||
* Detect and correct a 1 bit error for 256 byte block
|
||||
*/
|
||||
int nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
|
||||
int nand_correct_data(struct mtd_info *mtd, u_char *dat,
|
||||
u_char *read_ecc, u_char *calc_ecc)
|
||||
{
|
||||
u_char a, b, c, d1, d2, d3, add, bit, i;
|
||||
uint8_t s0, s1, s2;
|
||||
|
||||
/* Do error detection */
|
||||
d1 = calc_ecc[0] ^ read_ecc[0];
|
||||
d2 = calc_ecc[1] ^ read_ecc[1];
|
||||
d3 = calc_ecc[2] ^ read_ecc[2];
|
||||
|
||||
if ((d1 | d2 | d3) == 0) {
|
||||
/* No errors */
|
||||
#ifdef CONFIG_MTD_NAND_ECC_SMC
|
||||
s0 = calc_ecc[0] ^ read_ecc[0];
|
||||
s1 = calc_ecc[1] ^ read_ecc[1];
|
||||
s2 = calc_ecc[2] ^ read_ecc[2];
|
||||
#else
|
||||
s1 = calc_ecc[0] ^ read_ecc[0];
|
||||
s0 = calc_ecc[1] ^ read_ecc[1];
|
||||
s2 = calc_ecc[2] ^ read_ecc[2];
|
||||
#endif
|
||||
if ((s0 | s1 | s2) == 0)
|
||||
return 0;
|
||||
}
|
||||
else {
|
||||
a = (d1 ^ (d1 >> 1)) & 0x55;
|
||||
b = (d2 ^ (d2 >> 1)) & 0x55;
|
||||
c = (d3 ^ (d3 >> 1)) & 0x54;
|
||||
|
||||
/* Found and will correct single bit error in the data */
|
||||
if ((a == 0x55) && (b == 0x55) && (c == 0x54)) {
|
||||
c = 0x80;
|
||||
add = 0;
|
||||
a = 0x80;
|
||||
for (i=0; i<4; i++) {
|
||||
if (d1 & c)
|
||||
add |= a;
|
||||
c >>= 2;
|
||||
a >>= 1;
|
||||
}
|
||||
c = 0x80;
|
||||
for (i=0; i<4; i++) {
|
||||
if (d2 & c)
|
||||
add |= a;
|
||||
c >>= 2;
|
||||
a >>= 1;
|
||||
}
|
||||
bit = 0;
|
||||
b = 0x04;
|
||||
c = 0x80;
|
||||
for (i=0; i<3; i++) {
|
||||
if (d3 & c)
|
||||
bit |= b;
|
||||
c >>= 2;
|
||||
b >>= 1;
|
||||
}
|
||||
b = 0x01;
|
||||
a = dat[add];
|
||||
a ^= (b << bit);
|
||||
dat[add] = a;
|
||||
return 1;
|
||||
} else {
|
||||
i = 0;
|
||||
while (d1) {
|
||||
if (d1 & 0x01)
|
||||
++i;
|
||||
d1 >>= 1;
|
||||
}
|
||||
while (d2) {
|
||||
if (d2 & 0x01)
|
||||
++i;
|
||||
d2 >>= 1;
|
||||
}
|
||||
while (d3) {
|
||||
if (d3 & 0x01)
|
||||
++i;
|
||||
d3 >>= 1;
|
||||
}
|
||||
if (i == 1) {
|
||||
/* ECC Code Error Correction */
|
||||
read_ecc[0] = calc_ecc[0];
|
||||
read_ecc[1] = calc_ecc[1];
|
||||
read_ecc[2] = calc_ecc[2];
|
||||
return 2;
|
||||
}
|
||||
else {
|
||||
/* Uncorrectable Error */
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
/* Check for a single bit error */
|
||||
if( ((s0 ^ (s0 >> 1)) & 0x55) == 0x55 &&
|
||||
((s1 ^ (s1 >> 1)) & 0x55) == 0x55 &&
|
||||
((s2 ^ (s2 >> 1)) & 0x54) == 0x54) {
|
||||
|
||||
uint32_t byteoffs, bitnum;
|
||||
|
||||
byteoffs = (s1 << 0) & 0x80;
|
||||
byteoffs |= (s1 << 1) & 0x40;
|
||||
byteoffs |= (s1 << 2) & 0x20;
|
||||
byteoffs |= (s1 << 3) & 0x10;
|
||||
|
||||
byteoffs |= (s0 >> 4) & 0x08;
|
||||
byteoffs |= (s0 >> 3) & 0x04;
|
||||
byteoffs |= (s0 >> 2) & 0x02;
|
||||
byteoffs |= (s0 >> 1) & 0x01;
|
||||
|
||||
bitnum = (s2 >> 5) & 0x04;
|
||||
bitnum |= (s2 >> 4) & 0x02;
|
||||
bitnum |= (s2 >> 3) & 0x01;
|
||||
|
||||
dat[byteoffs] ^= (1 << bitnum);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/* Should never happen */
|
||||
if(countbits(s0 | ((uint32_t)s1 << 8) | ((uint32_t)s2 <<16)) == 1)
|
||||
return 1;
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
|
13
fs/fat/fat.c
Normal file → Executable file
13
fs/fat/fat.c
Normal file → Executable file
|
@ -59,7 +59,8 @@ int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr)
|
|||
if (cur_dev == NULL)
|
||||
return -1;
|
||||
if (cur_dev->block_read) {
|
||||
return cur_dev->block_read (cur_dev->dev, startblock, getsize, (unsigned long *)bufptr);
|
||||
return cur_dev->block_read (cur_dev->dev
|
||||
, startblock, getsize, (unsigned long *)bufptr);
|
||||
}
|
||||
return -1;
|
||||
}
|
||||
|
@ -89,8 +90,11 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no)
|
|||
part_offset=0;
|
||||
}
|
||||
else {
|
||||
#if (CONFIG_COMMANDS & CFG_CMD_IDE) || (CONFIG_COMMANDS & CFG_CMD_SCSI) || \
|
||||
(CONFIG_COMMANDS & CFG_CMD_USB) || defined(CONFIG_SYSTEMACE)
|
||||
#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \
|
||||
(CONFIG_COMMANDS & CFG_CMD_SCSI) || \
|
||||
(CONFIG_COMMANDS & CFG_CMD_USB) || \
|
||||
(defined(CONFIG_MMC) && defined(CONFIG_LPC2292)) || \
|
||||
defined(CONFIG_SYSTEMACE) )
|
||||
disk_partition_t info;
|
||||
if(!get_partition_info(dev_desc, part_no, &info)) {
|
||||
part_offset = info.start;
|
||||
|
@ -993,7 +997,8 @@ file_fat_detectfs(void)
|
|||
memcpy (vol_label, volinfo.volume_label, 11);
|
||||
vol_label[11] = '\0';
|
||||
volinfo.fs_type[5]='\0';
|
||||
printf("Partition %d: Filesystem: %s \"%s\"\n",cur_part,volinfo.fs_type,vol_label);
|
||||
printf("Partition %d: Filesystem: %s \"%s\"\n"
|
||||
,cur_part,volinfo.fs_type,vol_label);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -36,8 +36,6 @@
|
|||
/* include armadillo specific hardware file if there was one */
|
||||
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
|
||||
/* include IntegratorCP/CM720T specific hardware file if there was one */
|
||||
#elif defined(CONFIG_LPC2292)
|
||||
#include <asm-arm/arch-arm720t/lpc2292_registers.h>
|
||||
#else
|
||||
#error No hardware file defined for this configuration
|
||||
#endif
|
||||
|
|
33
include/asm-arm/arch-lpc2292/hardware.h
Normal file
33
include/asm-arm/arch-lpc2292/hardware.h
Normal file
|
@ -0,0 +1,33 @@
|
|||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
/*
|
||||
* Copyright (c) 2004 Cucy Systems (http://www.cucy.com)
|
||||
* Curt Brune <curt@cucy.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_LPC2292)
|
||||
#include <asm-arm/arch-lpc2292/lpc2292_registers.h>
|
||||
#else
|
||||
#error No hardware file defined for this configuration
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_ARCH_HARDWARE_H */
|
|
@ -105,6 +105,11 @@ static inline void sync(void)
|
|||
__asm__ __volatile__ ("sync" : : : "memory");
|
||||
}
|
||||
|
||||
static inline void isync(void)
|
||||
{
|
||||
__asm__ __volatile__ ("isync" : : : "memory");
|
||||
}
|
||||
|
||||
/* Enforce in-order execution of data I/O.
|
||||
* No distinction between read/write on PPC; use eieio for all three.
|
||||
*/
|
||||
|
@ -114,74 +119,90 @@ static inline void sync(void)
|
|||
|
||||
/*
|
||||
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
|
||||
*
|
||||
* Read operations have additional twi & isync to make sure the read
|
||||
* is actually performed (i.e. the data has come back) before we start
|
||||
* executing any following instructions.
|
||||
*/
|
||||
extern inline int in_8(volatile u8 *addr)
|
||||
#define __iomem
|
||||
extern inline int in_8(const volatile unsigned char __iomem *addr)
|
||||
{
|
||||
int ret;
|
||||
int ret;
|
||||
|
||||
__asm__ __volatile__("lbz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
|
||||
return ret;
|
||||
__asm__ __volatile__(
|
||||
"sync; lbz%U1%X1 %0,%1;\n"
|
||||
"twi 0,%0,0;\n"
|
||||
"isync" : "=r" (ret) : "m" (*addr));
|
||||
return ret;
|
||||
}
|
||||
|
||||
extern inline void out_8(volatile u8 *addr, int val)
|
||||
extern inline void out_8(volatile unsigned char __iomem *addr, int val)
|
||||
{
|
||||
__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
|
||||
__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
|
||||
}
|
||||
|
||||
extern inline int in_le16(volatile u16 *addr)
|
||||
extern inline int in_le16(const volatile unsigned short __iomem *addr)
|
||||
{
|
||||
int ret;
|
||||
int ret;
|
||||
|
||||
__asm__ __volatile__("lhbrx %0,0,%1; eieio" : "=r" (ret) :
|
||||
"r" (addr), "m" (*addr));
|
||||
return ret;
|
||||
__asm__ __volatile__("sync; lhbrx %0,0,%1;\n"
|
||||
"twi 0,%0,0;\n"
|
||||
"isync" : "=r" (ret) :
|
||||
"r" (addr), "m" (*addr));
|
||||
return ret;
|
||||
}
|
||||
|
||||
extern inline int in_be16(volatile u16 *addr)
|
||||
extern inline int in_be16(const volatile unsigned short __iomem *addr)
|
||||
{
|
||||
int ret;
|
||||
int ret;
|
||||
|
||||
__asm__ __volatile__("lhz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
|
||||
return ret;
|
||||
__asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n"
|
||||
"twi 0,%0,0;\n"
|
||||
"isync" : "=r" (ret) : "m" (*addr));
|
||||
return ret;
|
||||
}
|
||||
|
||||
extern inline void out_le16(volatile u16 *addr, int val)
|
||||
extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
|
||||
{
|
||||
__asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
|
||||
"r" (val), "r" (addr));
|
||||
__asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) :
|
||||
"r" (val), "r" (addr));
|
||||
}
|
||||
|
||||
extern inline void out_be16(volatile u16 *addr, int val)
|
||||
extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
|
||||
{
|
||||
__asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
|
||||
__asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
|
||||
}
|
||||
|
||||
extern inline unsigned in_le32(volatile u32 *addr)
|
||||
extern inline unsigned in_le32(const volatile unsigned __iomem *addr)
|
||||
{
|
||||
unsigned ret;
|
||||
unsigned ret;
|
||||
|
||||
__asm__ __volatile__("lwbrx %0,0,%1; eieio" : "=r" (ret) :
|
||||
"r" (addr), "m" (*addr));
|
||||
return ret;
|
||||
__asm__ __volatile__("sync; lwbrx %0,0,%1;\n"
|
||||
"twi 0,%0,0;\n"
|
||||
"isync" : "=r" (ret) :
|
||||
"r" (addr), "m" (*addr));
|
||||
return ret;
|
||||
}
|
||||
|
||||
extern inline unsigned in_be32(volatile u32 *addr)
|
||||
extern inline unsigned in_be32(const volatile unsigned __iomem *addr)
|
||||
{
|
||||
unsigned ret;
|
||||
unsigned ret;
|
||||
|
||||
__asm__ __volatile__("lwz%U1%X1 %0,%1; eieio" : "=r" (ret) : "m" (*addr));
|
||||
return ret;
|
||||
__asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n"
|
||||
"twi 0,%0,0;\n"
|
||||
"isync" : "=r" (ret) : "m" (*addr));
|
||||
return ret;
|
||||
}
|
||||
|
||||
extern inline void out_le32(volatile unsigned *addr, int val)
|
||||
extern inline void out_le32(volatile unsigned __iomem *addr, int val)
|
||||
{
|
||||
__asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
|
||||
"r" (val), "r" (addr));
|
||||
__asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) :
|
||||
"r" (val), "r" (addr));
|
||||
}
|
||||
|
||||
extern inline void out_be32(volatile unsigned *addr, int val)
|
||||
extern inline void out_be32(volatile unsigned __iomem *addr, int val)
|
||||
{
|
||||
__asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
|
||||
__asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
@ -577,6 +577,7 @@
|
|||
#define CONFIG_HOSTNAME unknown
|
||||
#define CONFIG_ROOTPATH /opt/nfsroot
|
||||
#define CONFIG_BOOTFILE uImage
|
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
|
||||
|
||||
#define CONFIG_SERVERIP 192.168.1.1
|
||||
#define CONFIG_GATEWAYIP 192.168.1.1
|
||||
|
@ -592,10 +593,17 @@
|
|||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
|
||||
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
|
||||
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=your.ramdisk.u-boot\0" \
|
||||
"dtbaddr=400000\0" \
|
||||
"dtbaddr=c00000\0" \
|
||||
"dtbfile=mpc8641_hpcn.dtb\0" \
|
||||
"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
|
||||
"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
|
||||
|
|
199
include/configs/SMN42.h
Executable file
199
include/configs/SMN42.h
Executable file
|
@ -0,0 +1,199 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Configuation settings for the SMN42 board from Siemens.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* If we are developing, we might want to start u-boot from ram
|
||||
* so we MUST NOT initialize critical regs like mem-timing ...
|
||||
*/
|
||||
#undef CONFIG_INIT_CRITICAL /* undef for developing */
|
||||
|
||||
#undef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#undef CONFIG_SKIP_RELOCATE_UBOOT
|
||||
|
||||
/*
|
||||
* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
|
||||
#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
|
||||
#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
|
||||
#define CONFIG_LPC2292
|
||||
#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
|
||||
|
||||
#undef CONFIG_USE_IRQ /* don't need them anymore */
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
|
||||
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* select serial console configuration
|
||||
*/
|
||||
#define CONFIG_SERIAL1 1 /* we use Serial line 1 */
|
||||
|
||||
/* allow to overwrite serial and ethaddr */
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
|
||||
|
||||
/* enable I2C and select the hardware/software driver */
|
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
||||
/* this would be 0xAE if E0, E1 and E2 were pulled high */
|
||||
#define CFG_I2C_SLAVE 0xA0
|
||||
#define CFG_I2C_EEPROM_ADDR (0xA0 >> 1)
|
||||
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* 16 bit address */
|
||||
#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes per write */
|
||||
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
|
||||
/* not used but required by devices.c */
|
||||
#define CFG_I2C_SPEED 10000
|
||||
|
||||
#ifdef CONFIG_SOFT_I2C
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
#define SCL 0x00000004 /* P0.2 */
|
||||
#define SDA 0x00000008 /* P0.3 */
|
||||
|
||||
#define I2C_READ ((GET32(IO0PIN) & SDA) ? 1 : 0)
|
||||
#define I2C_SDA(x) { if (x) PUT32(IO0SET, SDA); else PUT32(IO0CLR, SDA); }
|
||||
#define I2C_SCL(x) { if (x) PUT32(IO0SET, SCL); else PUT32(IO0CLR, SCL); }
|
||||
#define I2C_DELAY { udelay(100); }
|
||||
#define I2C_ACTIVE { unsigned int i2ctmp; \
|
||||
i2ctmp = GET32(IO0DIR); \
|
||||
i2ctmp |= SDA; \
|
||||
PUT32(IO0DIR, i2ctmp); }
|
||||
#define I2C_TRISTATE { unsigned int i2ctmp; \
|
||||
i2ctmp = GET32(IO0DIR); \
|
||||
i2ctmp &= ~SDA; \
|
||||
PUT32(IO0DIR, i2ctmp); }
|
||||
#endif /* CONFIG_SOFT_I2C */
|
||||
|
||||
/*
|
||||
* Supported commands
|
||||
*/
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_MMC | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_PING)
|
||||
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CFG_LONGHELP /* undef to save memory */
|
||||
#define CFG_PROMPT "SMN42 # " /* Monitor Command Prompt */
|
||||
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CFG_MAXARGS 16 /* max number of command args */
|
||||
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||
|
||||
#define CFG_MEMTEST_START 0x81800000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x83000000 /* 24 MB in SRAM */
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x81000000 /* default load address */
|
||||
/* for uClinux img is here*/
|
||||
|
||||
#define CFG_SYS_CLK_FREQ 58982400 /* Hz */
|
||||
#define CFG_HZ 2048 /* decrementer freq in Hz */
|
||||
|
||||
/* valid baudrates */
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Stack sizes
|
||||
*
|
||||
* The stack sizes are set up in start.S using the settings below
|
||||
*/
|
||||
#define CONFIG_STACKSIZE (128*1024) /* regular stack */
|
||||
#ifdef CONFIG_USE_IRQ
|
||||
#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
|
||||
#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SRAM */
|
||||
#define PHYS_SDRAM_1 0x81000000 /* SRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB SRAM */
|
||||
|
||||
/* This is the external flash */
|
||||
#define PHYS_FLASH_1 0x80000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
/*
|
||||
* The first entry in CFG_FLASH_BANKS_LIST is a dummy, but it must be present.
|
||||
*/
|
||||
#define CFG_FLASH_BANKS_LIST { 0, PHYS_FLASH_1 }
|
||||
#define CFG_FLASH_ADDR0 0x555
|
||||
#define CFG_FLASH_ADDR1 0x2AA
|
||||
#define CFG_FLASH_ERASE_TOUT 16384 /* Timeout for Flash Erase (in ms) */
|
||||
#define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
|
||||
|
||||
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
/* The Environment Sector is in the CPU-internal flash */
|
||||
#define CFG_FLASH_BASE 0
|
||||
#define CFG_ENV_OFFSET 0x3C000
|
||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
|
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_MMC 1
|
||||
/* we use this ethernet chip */
|
||||
#define CONFIG_ENC28J60
|
||||
|
||||
#endif /* __CONFIG_H */
|
|
@ -207,7 +207,7 @@
|
|||
* PCI Bus clocking configuration
|
||||
*
|
||||
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
|
||||
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
|
||||
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
|
||||
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
|
||||
*/
|
||||
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
|
||||
|
|
|
@ -109,6 +109,7 @@
|
|||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||
|
||||
|
@ -122,6 +123,12 @@
|
|||
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
|
||||
#define _CFG_CMD_INCLUDE (CFG_CMD_ALL)
|
||||
#else
|
||||
#define CFG_NO_FLASH 1 /* No NOR on Acadia when NAND-booting */
|
||||
#define _CFG_CMD_INCLUDE ((CFG_CMD_ALL) & ~(CFG_CMD_FLASH | CFG_CMD_IMLS))
|
||||
#endif
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
|
||||
|
@ -132,6 +139,63 @@
|
|||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IPL (Initial Program Loader, integrated inside CPU)
|
||||
* Will load first 4k from NAND (SPL) into cache and execute it from there.
|
||||
*
|
||||
* SPL (Secondary Program Loader)
|
||||
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
|
||||
* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
|
||||
* controller and the NAND controller so that the special U-Boot image can be
|
||||
* loaded from NAND to SDRAM.
|
||||
*
|
||||
* NUB (NAND U-Boot)
|
||||
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
|
||||
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
|
||||
*
|
||||
* On 440EPx the SPL is copied to SDRAM before the NAND controller is
|
||||
* set up. While still running from cache, I experienced problems accessing
|
||||
* the NAND controller. sr - 2006-08-25
|
||||
*/
|
||||
#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
|
||||
#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
|
||||
#define CFG_NAND_BOOT_SPL_DST (CFG_OCM_DATA_ADDR + (12 << 10)) /* Copy SPL here*/
|
||||
#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
|
||||
#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
|
||||
#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
|
||||
|
||||
/*
|
||||
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
|
||||
*/
|
||||
#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
|
||||
#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
|
||||
|
||||
/*
|
||||
* Now the NAND chip has to be defined (no autodetection used!)
|
||||
*/
|
||||
#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
|
||||
#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
|
||||
#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
|
||||
#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
|
||||
#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
|
||||
|
||||
#define CFG_NAND_ECCSIZE 256
|
||||
#define CFG_NAND_ECCBYTES 3
|
||||
#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
|
||||
#define CFG_NAND_OOBSIZE 16
|
||||
#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
|
||||
#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_NAND
|
||||
/*
|
||||
* For NAND booting the environment is embedded in the U-Boot image. Please take
|
||||
* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
|
||||
*/
|
||||
#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
|
||||
#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* RAM (CRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
|
@ -209,7 +273,11 @@
|
|||
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
|
||||
"cp.b ${fileaddr} fffc0000 ${filesize};" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"upd=run load;run update\0" \
|
||||
"upd=run load update\0" \
|
||||
"nload=tftp 200000 acadia/u-boot-nand.bin\0" \
|
||||
"nupdate=nand erase 0 60000;nand write 200000 0 60000;" \
|
||||
"setenv filesize;saveenv\0" \
|
||||
"nupd=run nload nupdate\0" \
|
||||
"kozio=bootm ffc60000\0" \
|
||||
""
|
||||
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||
|
@ -233,24 +301,24 @@
|
|||
|
||||
#define CONFIG_SUPPORT_VFAT
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NAND | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_USB)
|
||||
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL & _CFG_CMD_INCLUDE) | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_DTT | \
|
||||
CFG_CMD_DIAG | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_FAT | \
|
||||
CFG_CMD_I2C | \
|
||||
CFG_CMD_IRQ | \
|
||||
CFG_CMD_MII | \
|
||||
CFG_CMD_NAND | \
|
||||
CFG_CMD_NET | \
|
||||
CFG_CMD_NFS | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PING | \
|
||||
CFG_CMD_REGINFO | \
|
||||
CFG_CMD_USB)
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
|
@ -312,12 +380,16 @@
|
|||
/*-----------------------------------------------------------------------
|
||||
* External Bus Controller (EBC) Setup
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_NAND_CS 3 /* NAND chip connected to CSx */
|
||||
|
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#define CFG_NAND_CS 3
|
||||
/* Memory Bank 0 (Flash) initialization */
|
||||
#define CFG_EBC_PB0AP 0x03337200
|
||||
#define CFG_EBC_PB0CR 0xfe0bc000
|
||||
|
||||
/* Memory Bank 3 (NAND-FLASH) initialization */
|
||||
#define CFG_EBC_PB3AP 0x018003c0
|
||||
#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
|
||||
|
||||
/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
|
||||
/* Memory Bank 1 (CRAM) initialization */
|
||||
#define CFG_EBC_PB1AP 0x030400c0
|
||||
|
@ -326,10 +398,24 @@
|
|||
/* Memory Bank 2 (CRAM) initialization */
|
||||
#define CFG_EBC_PB2AP 0x030400c0
|
||||
#define CFG_EBC_PB2CR 0x020bc000
|
||||
#else
|
||||
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
|
||||
/* Memory Bank 0 (NAND-FLASH) initialization */
|
||||
#define CFG_EBC_PB0AP 0x018003c0
|
||||
#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
|
||||
|
||||
/* Memory Bank 3 (NAND-FLASH) initialization */
|
||||
#define CFG_EBC_PB3AP 0x018003c0
|
||||
#define CFG_EBC_PB3CR (CFG_NAND_ADDR | 0x1c000)
|
||||
/*
|
||||
* When NAND-booting the CRAM EBC setup must be done in sync mode, since the
|
||||
* NAND-SPL already initialized the CRAM and EBC to sync mode.
|
||||
*/
|
||||
/* Memory Bank 1 (CRAM) initialization */
|
||||
#define CFG_EBC_PB1AP 0x9C0201C0
|
||||
#define CFG_EBC_PB1CR 0x000bc000
|
||||
|
||||
/* Memory Bank 2 (CRAM) initialization */
|
||||
#define CFG_EBC_PB2AP 0x9C0201C0
|
||||
#define CFG_EBC_PB2CR 0x020bc000
|
||||
#endif
|
||||
|
||||
/* Memory Bank 4 (CPLD) initialization */
|
||||
#define CFG_EBC_PB4AP 0x04006000
|
||||
|
@ -341,9 +427,9 @@
|
|||
* GPIO Setup
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_GPIO_CRAM_CLK 8
|
||||
#define CFG_GPIO_CRAM_WAIT 9
|
||||
#define CFG_GPIO_CRAM_WAIT 9 /* GPIO-In */
|
||||
#define CFG_GPIO_CRAM_ADV 10
|
||||
#define CFG_GPIO_CRAM_CRE (32 + 21)
|
||||
#define CFG_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for GPIO_0 setup (PPC405EZ specific)
|
||||
|
@ -365,10 +451,10 @@
|
|||
* GPIO0[28-30] - Trace Outputs / PWM Inputs
|
||||
* GPIO0[31] - PWM_8 I/O
|
||||
*/
|
||||
#define CFG_GPIO0_TCR 0xC0000000
|
||||
#define CFG_GPIO0_OSRL 0x50000000
|
||||
#define CFG_GPIO0_TCR 0xC0A00000
|
||||
#define CFG_GPIO0_OSRL 0x50004400
|
||||
#define CFG_GPIO0_OSRH 0x02000055
|
||||
#define CFG_GPIO0_ISR1L 0x00000000
|
||||
#define CFG_GPIO0_ISR1L 0x00001000
|
||||
#define CFG_GPIO0_ISR1H 0x00000055
|
||||
#define CFG_GPIO0_TSRL 0x02000000
|
||||
#define CFG_GPIO0_TSRH 0x00000055
|
||||
|
@ -387,13 +473,13 @@
|
|||
* GPIO1[16] - SPI_SS_1_N Output
|
||||
* GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
|
||||
*/
|
||||
#define CFG_GPIO1_OSRH 0x55455555
|
||||
#define CFG_GPIO1_TCR 0xFFFF8414
|
||||
#define CFG_GPIO1_OSRL 0x40000110
|
||||
#define CFG_GPIO1_ISR1H 0x00000000
|
||||
#define CFG_GPIO1_OSRH 0x55455555
|
||||
#define CFG_GPIO1_ISR1L 0x15555445
|
||||
#define CFG_GPIO1_TSRH 0x00000000
|
||||
#define CFG_GPIO1_ISR1H 0x00000000
|
||||
#define CFG_GPIO1_TSRL 0x00000000
|
||||
#define CFG_GPIO1_TCR 0xFFFF8014
|
||||
#define CFG_GPIO1_TSRH 0x00000000
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
|
|
|
@ -173,7 +173,7 @@
|
|||
* PCI Bus clocking configuration
|
||||
*
|
||||
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
|
||||
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
|
||||
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
|
||||
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
|
||||
*/
|
||||
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
|
||||
|
|
|
@ -50,7 +50,7 @@
|
|||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
|
||||
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
|
||||
#define CFG_MONITOR_BASE (-CFG_MONITOR_LEN)
|
||||
#define CFG_MONITOR_BASE TEXT_BASE
|
||||
#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
|
||||
#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
|
||||
#define CFG_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/
|
||||
|
@ -104,14 +104,11 @@
|
|||
/*-----------------------------------------------------------------------
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
/*
|
||||
* Define here the location of the environment variables (FLASH or EEPROM).
|
||||
* Note: DENX encourages to use redundant environment in FLASH.
|
||||
*/
|
||||
#if 1
|
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
#else
|
||||
#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
|
||||
#define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
|
||||
#define CFG_ENV_IS_EMBEDDED 1 /* use embedded environment */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
|
@ -133,7 +130,7 @@
|
|||
|
||||
#ifdef CFG_ENV_IS_IN_FLASH
|
||||
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
|
@ -141,22 +138,89 @@
|
|||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
#endif /* CFG_ENV_IS_IN_FLASH */
|
||||
|
||||
/*
|
||||
* IPL (Initial Program Loader, integrated inside CPU)
|
||||
* Will load first 4k from NAND (SPL) into cache and execute it from there.
|
||||
*
|
||||
* SPL (Secondary Program Loader)
|
||||
* Will load special U-Boot version (NUB) from NAND and execute it. This SPL
|
||||
* has to fit into 4kByte. It sets up the CPU and configures the SDRAM
|
||||
* controller and the NAND controller so that the special U-Boot image can be
|
||||
* loaded from NAND to SDRAM.
|
||||
*
|
||||
* NUB (NAND U-Boot)
|
||||
* This NAND U-Boot (NUB) is a special U-Boot version which can be started
|
||||
* from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
|
||||
*
|
||||
* On 440EPx the SPL is copied to SDRAM before the NAND controller is
|
||||
* set up. While still running from cache, I experienced problems accessing
|
||||
* the NAND controller. sr - 2006-08-25
|
||||
*/
|
||||
#define CFG_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
|
||||
#define CFG_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
|
||||
#define CFG_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */
|
||||
#define CFG_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
|
||||
#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start NUB from this addr */
|
||||
#define CFG_NAND_BOOT_SPL_DELTA (CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)
|
||||
|
||||
/*
|
||||
* Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
|
||||
*/
|
||||
#define CFG_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */
|
||||
#define CFG_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */
|
||||
|
||||
/*
|
||||
* Now the NAND chip has to be defined (no autodetection used!)
|
||||
*/
|
||||
#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
|
||||
#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
|
||||
#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
|
||||
#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
|
||||
#define CFG_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */
|
||||
|
||||
#define CFG_NAND_ECCSIZE 256
|
||||
#define CFG_NAND_ECCBYTES 3
|
||||
#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
|
||||
#define CFG_NAND_OOBSIZE 16
|
||||
#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
|
||||
#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_NAND
|
||||
/*
|
||||
* For NAND booting the environment is embedded in the U-Boot image. Please take
|
||||
* look at the file board/amcc/sequoia/u-boot-nand.lds for details.
|
||||
*/
|
||||
#define CFG_ENV_SIZE CFG_NAND_BLOCK_SIZE
|
||||
#define CFG_ENV_OFFSET (CFG_NAND_U_BOOT_OFFS + CFG_ENV_SIZE)
|
||||
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET + CFG_ENV_SIZE)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* NAND FLASH
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CFG_MAX_NAND_DEVICE 1
|
||||
#define NAND_MAX_CHIPS 1
|
||||
#define CFG_NAND_CS 1
|
||||
#define CFG_MAX_NAND_DEVICE 2
|
||||
#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
|
||||
#define CFG_NAND_BASE (CFG_NAND_ADDR + CFG_NAND_CS)
|
||||
#define CFG_NAND_BASE_LIST { CFG_NAND_BASE, CFG_NAND_ADDR + 2 }
|
||||
#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
|
||||
|
||||
#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
|
||||
#define CFG_NAND_CS 1
|
||||
#else
|
||||
#define CFG_NAND_CS 0 /* NAND chip connected to CSx */
|
||||
/* Memory Bank 0 (NAND-FLASH) initialization */
|
||||
#define CFG_EBC_PB0AP 0x018003c0
|
||||
#define CFG_EBC_PB0CR (CFG_NAND_ADDR | 0x1c000)
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------------- */
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
|
||||
#undef CONFIG_DDR_ECC /* don't use ECC */
|
||||
#define CFG_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */
|
||||
#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
|
||||
#define SPD_EEPROM_ADDRESS {CFG_SIMULATE_SPD_EEPROM, 0x50, 0x51}
|
||||
#define CFG_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
|
|
25
include/configs/lpc2292sodimm.h
Normal file → Executable file
25
include/configs/lpc2292sodimm.h
Normal file → Executable file
|
@ -1,12 +1,8 @@
|
|||
/*
|
||||
* (C) Copyright 2000
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
* (C) Copyright 2007
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* Configuation settings for the EP7312 board.
|
||||
*
|
||||
* Modified to work on Armadillo HT1070 ARM720T board
|
||||
* (C) Copyright 2005 Rowel Atienza rowel@diwalabs.com
|
||||
* Configuation settings for the LPC2292SODIMM board from Embedded Artists.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -31,7 +27,7 @@
|
|||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* If we are developing, we might want to start armboot from ram
|
||||
* If we are developing, we might want to start u-boot from ram
|
||||
* so we MUST NOT initialize critical regs like mem-timing ...
|
||||
*/
|
||||
#undef CONFIG_INIT_CRITICAL /* undef for developing */
|
||||
|
@ -46,7 +42,7 @@
|
|||
#define CONFIG_ARM7 1 /* This is a ARM7 CPU */
|
||||
#define CONFIG_ARM_THUMB 1 /* this is an ARM720TDMI */
|
||||
#define CONFIG_LPC2292
|
||||
#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
|
||||
#undef CONFIG_ARM7_REVD /* disable ARM720 REV.D Workarounds */
|
||||
|
||||
#undef CONFIG_USE_IRQ /* don't need them anymore */
|
||||
|
||||
|
@ -70,7 +66,7 @@
|
|||
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
|
||||
|
||||
/*
|
||||
* Supported commands
|
||||
|
@ -103,11 +99,12 @@
|
|||
#define CFG_MEMTEST_START 0x40000000 /* memtest works on */
|
||||
#define CFG_MEMTEST_END 0x40000000 /* 4 ... 8 MB in DRAM */
|
||||
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
|
||||
|
||||
#define CFG_LOAD_ADDR 0x00040000 /* default load address for armadillo: kernel img is here*/
|
||||
#define CFG_LOAD_ADDR 0x00040000 /* default load address for */
|
||||
/* armadillo: kernel img is here*/
|
||||
|
||||
#define CFG_SYS_CLK_FREQ 58982400 /* Hz */
|
||||
#define CFG_SYS_CLK_FREQ 58982400 /* Hz */
|
||||
#define CFG_HZ 2048 /* decrementer freq in Hz */
|
||||
|
||||
/* valid baudrates */
|
||||
|
@ -154,5 +151,7 @@
|
|||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
#define CONFIG_MMC 1
|
||||
/* we use this ethernet chip */
|
||||
#define CONFIG_ENC28J60
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
@ -135,7 +135,8 @@
|
|||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
|
||||
#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
|
||||
#undef CONFIG_DDR_ECC /* no ECC support for now */
|
||||
#define CONFIG_DDR_ECC 1 /* with ECC support */
|
||||
#define CFG_44x_DDR2_CKTR_180 1 /* use 180 deg advance */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
|
|
|
@ -58,7 +58,7 @@
|
|||
* 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
|
||||
*/
|
||||
|
||||
#define CONFIG_SOLIDCARD3 1
|
||||
#define CONFIG_SC3 1
|
||||
#define CONFIG_4xx 1
|
||||
#define CONFIG_405GP 1
|
||||
|
||||
|
@ -134,7 +134,8 @@
|
|||
#if 1 /* feel free to disable for development */
|
||||
#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
|
||||
#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with ENTER\n"
|
||||
#define CONFIG_AUTOBOOT_DELAY_STR "\n" /* 1st "password" */
|
||||
#define CONFIG_AUTOBOOT_DELAY_STR "\r" /* 1st "password" */
|
||||
#define CONFIG_AUTOBOOT_DELAY_STR2 "\n" /* 1st "password" */
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
@ -168,12 +168,19 @@
|
|||
/*
|
||||
* Now the NAND chip has to be defined (no autodetection used!)
|
||||
*/
|
||||
#define CFG_NAND_PAGE_SIZE (512) /* NAND chip page size */
|
||||
#define CFG_NAND_PAGE_SIZE 512 /* NAND chip page size */
|
||||
#define CFG_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */
|
||||
#define CFG_NAND_PAGE_COUNT (32) /* NAND chip page count */
|
||||
#define CFG_NAND_BAD_BLOCK_POS (5) /* Location of bad block marker */
|
||||
#define CFG_NAND_PAGE_COUNT 32 /* NAND chip page count */
|
||||
#define CFG_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */
|
||||
#undef CFG_NAND_4_ADDR_CYCLE /* No fourth addr used (<=32MB) */
|
||||
|
||||
#define CFG_NAND_ECCSIZE 256
|
||||
#define CFG_NAND_ECCBYTES 3
|
||||
#define CFG_NAND_ECCSTEPS (CFG_NAND_PAGE_SIZE / CFG_NAND_ECCSIZE)
|
||||
#define CFG_NAND_OOBSIZE 16
|
||||
#define CFG_NAND_ECCTOTAL (CFG_NAND_ECCBYTES * CFG_NAND_ECCSTEPS)
|
||||
#define CFG_NAND_ECCPOS {0, 1, 2, 3, 6, 7}
|
||||
|
||||
#ifdef CFG_ENV_IS_IN_NAND
|
||||
/*
|
||||
* For NAND booting the environment is embedded in the U-Boot image. Please take
|
||||
|
|
|
@ -226,7 +226,7 @@
|
|||
* PCI Bus clocking configuration
|
||||
*
|
||||
* Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
|
||||
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
|
||||
* CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
|
||||
* of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
|
||||
*/
|
||||
#define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
|
||||
|
|
|
@ -80,16 +80,20 @@
|
|||
* This address, however, is used to configure a 256M local bus
|
||||
* window that includes the Config latch below.
|
||||
*/
|
||||
#define CFG_LBC_OPTION_BASE 0xf0000000 /* Localbus Extension */
|
||||
#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
|
||||
#define CFG_LBC_OPTION_SIZE 256 /* 256MB */
|
||||
|
||||
/* There are various flash options used, we configure for the largest,
|
||||
* which is 64Mbytes. The CFI works fine and will discover the proper
|
||||
* sizes.
|
||||
*/
|
||||
#define CFG_FLASH_BASE 0xFC000000 /* start of FLASH 64M */
|
||||
#define CFG_BR0_PRELIM 0xFC001801 /* port size 32bit */
|
||||
#define CFG_OR0_PRELIM 0xFC000FF7 /* 64 MB Flash */
|
||||
#ifdef CONFIG_STXSSA_4M
|
||||
#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
|
||||
#else
|
||||
#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
|
||||
#endif
|
||||
#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x1801) /* port size 32bit */
|
||||
#define CFG_OR0_PRELIM (CFG_FLASH_BASE | 0x0FF7)
|
||||
|
||||
#define CFG_FLASH_CFI 1
|
||||
#define CFG_FLASH_CFI_DRIVER 1
|
||||
|
@ -104,9 +108,9 @@
|
|||
/* The configuration latch is Chip Select 1.
|
||||
* It's an 8-bit latch in the lower 8 bits of the word.
|
||||
*/
|
||||
#define CFG_LBC_CFGLATCH_BASE 0xfb000000 /* Base of config latch */
|
||||
#define CFG_BR1_PRELIM 0xfb001801 /* 32-bit port */
|
||||
#define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
|
||||
#define CFG_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
|
||||
#define CFG_BR1_PRELIM 0xFB001801 /* 32-bit port */
|
||||
#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
|
||||
|
||||
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
|
@ -300,17 +304,20 @@
|
|||
|
||||
/* Environment - default config is in flash, see below */
|
||||
#if 0 /* in EEPROM */
|
||||
#define CFG_ENV_IS_IN_EEPROM 1
|
||||
#define CFG_ENV_OFFSET 0
|
||||
#define CFG_ENV_SIZE 2048
|
||||
# define CFG_ENV_IS_IN_EEPROM 1
|
||||
# define CFG_ENV_OFFSET 0
|
||||
# define CFG_ENV_SIZE 2048
|
||||
#else /* in flash */
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
#define CFG_ENV_SECT_SIZE 0x40000
|
||||
|
||||
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE 0x4000
|
||||
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
|
||||
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
# define CFG_ENV_IS_IN_FLASH 1
|
||||
# ifdef CONFIG_STXSSA_4M
|
||||
# define CFG_ENV_SECT_SIZE 0x20000
|
||||
# else /* default configuration - 64 MiB flash */
|
||||
# define CFG_ENV_SECT_SIZE 0x40000
|
||||
# endif
|
||||
# define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
|
||||
# define CFG_ENV_SIZE 0x4000
|
||||
# define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
|
||||
# define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
|
|
|
@ -556,6 +556,11 @@
|
|||
#define sdricintstat 0x4510
|
||||
|
||||
#define SDR_NAND0_NDEN 0x80000000
|
||||
#define SDR_NAND0_NDBTEN 0x40000000
|
||||
#define SDR_NAND0_NDBADR_MASK 0x30000000
|
||||
#define SDR_NAND0_NDBPG_MASK 0x0f000000
|
||||
#define SDR_NAND0_NDAREN 0x00800000
|
||||
#define SDR_NAND0_NDRBEN 0x00400000
|
||||
|
||||
#define SDR_ULTRA0_NDGPIOBP 0x80000000
|
||||
#define SDR_ULTRA0_CSN_MASK 0x78000000
|
||||
|
@ -563,6 +568,9 @@
|
|||
#define SDR_ULTRA0_CSNSEL1 0x20000000
|
||||
#define SDR_ULTRA0_CSNSEL2 0x10000000
|
||||
#define SDR_ULTRA0_CSNSEL3 0x08000000
|
||||
#define SDR_ULTRA0_EBCRDYEN 0x04000000
|
||||
#define SDR_ULTRA0_SPISSINEN 0x02000000
|
||||
#define SDR_ULTRA0_NFSRSTEN 0x01000000
|
||||
|
||||
#define SDR_ULTRA1_LEDNENABLE 0x40000000
|
||||
|
||||
|
|
|
@ -76,7 +76,7 @@
|
|||
extern int update_flash_size (int flash_size);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOLIDCARD3)
|
||||
#if defined(CONFIG_SC3)
|
||||
extern void sc3_read_eeprom(void);
|
||||
#endif
|
||||
|
||||
|
@ -820,7 +820,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||
#endif /* CONFIG_405GP, CONFIG_405EP */
|
||||
#endif /* CFG_EXTBDINFO */
|
||||
|
||||
#if defined(CONFIG_SOLIDCARD3)
|
||||
#if defined(CONFIG_SC3)
|
||||
sc3_read_eeprom();
|
||||
#endif
|
||||
s = getenv ("ethaddr");
|
||||
|
@ -929,7 +929,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
|
|||
defined(CONFIG_KUP4X) || \
|
||||
defined(CONFIG_LWMON) || \
|
||||
defined(CONFIG_PCU_E) || \
|
||||
defined(CONFIG_SOLIDCARD3) || \
|
||||
defined(CONFIG_SC3) || \
|
||||
defined(CONFIG_W7O) || \
|
||||
defined(CONFIG_MISC_INIT_R)
|
||||
/* miscellaneous platform dependent initialisations */
|
||||
|
|
104
nand_spl/board/amcc/acadia/Makefile
Normal file
104
nand_spl/board/amcc/acadia/Makefile
Normal file
|
@ -0,0 +1,104 @@
|
|||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
|
||||
|
||||
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
|
||||
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
|
||||
AFLAGS += -DCONFIG_NAND_SPL
|
||||
CFLAGS += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o resetvec.o
|
||||
COBJS = gpio.o nand_boot.o nand_ecc.o memory.o ndfc.o
|
||||
|
||||
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
__OBJS := $(SOBJS) $(COBJS)
|
||||
LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
|
||||
|
||||
nandobj := $(OBJTREE)/nand_spl/
|
||||
|
||||
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
|
||||
|
||||
all: $(obj).depend $(ALL)
|
||||
|
||||
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl: $(OBJS)
|
||||
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
|
||||
-Map $(nandobj)u-boot-spl.map \
|
||||
-o $(nandobj)u-boot-spl
|
||||
|
||||
# create symbolic links for common files
|
||||
|
||||
# from cpu directory
|
||||
$(obj)gpio.c:
|
||||
@rm -f $(obj)gpio.c
|
||||
ln -s $(SRCTREE)/cpu/ppc4xx/gpio.c $(obj)gpio.c
|
||||
|
||||
$(obj)ndfc.c:
|
||||
@rm -f $(obj)ndfc.c
|
||||
ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
|
||||
|
||||
$(obj)resetvec.S:
|
||||
@rm -f $(obj)resetvec.S
|
||||
ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
|
||||
|
||||
$(obj)start.S:
|
||||
@rm -f $(obj)start.S
|
||||
ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
|
||||
|
||||
# from board directory
|
||||
$(obj)memory.c:
|
||||
@rm -f $(obj)memory.c
|
||||
ln -s $(SRCTREE)/board/amcc/acadia/memory.c $(obj)memory.c
|
||||
|
||||
# from nand_spl directory
|
||||
$(obj)nand_boot.c:
|
||||
@rm -f $(obj)nand_boot.c
|
||||
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
|
||||
|
||||
# from drivers/nand directory
|
||||
$(obj)nand_ecc.c:
|
||||
@rm -f $(obj)nand_ecc.c
|
||||
ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c
|
||||
|
||||
#########################################################################
|
||||
|
||||
$(obj)%.o: $(obj)%.S
|
||||
$(CC) $(AFLAGS) -c -o $@ $<
|
||||
|
||||
$(obj)%.o: $(obj)%.c
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
47
nand_spl/board/amcc/acadia/config.mk
Normal file
47
nand_spl/board/amcc/acadia/config.mk
Normal file
|
@ -0,0 +1,47 @@
|
|||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
#
|
||||
# AMCC 405EZ Reference Platform (Acadia) board
|
||||
#
|
||||
|
||||
#
|
||||
# TEXT_BASE for SPL:
|
||||
#
|
||||
# On 4xx platforms the SPL is located at 0xfffff000...0xffffffff,
|
||||
# in the last 4kBytes of memory space in cache.
|
||||
# We will copy this SPL into internal SRAM in start.S. So we set
|
||||
# TEXT_BASE to starting address in internal SRAM here.
|
||||
#
|
||||
TEXT_BASE = 0xF8003000
|
||||
|
||||
# PAD_TO used to generate a 16kByte binary needed for the combined image
|
||||
# -> PAD_TO = TEXT_BASE + 0x4000
|
||||
PAD_TO = 0xF8007000
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif
|
||||
|
||||
ifeq ($(dbcr),1)
|
||||
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
|
||||
endif
|
63
nand_spl/board/amcc/acadia/u-boot.lds
Normal file
63
nand_spl/board/amcc/acadia/u-boot.lds
Normal file
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc:common)
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0xF8003FFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
.text :
|
||||
{
|
||||
start.o (.text)
|
||||
nand_boot.o (.text)
|
||||
ndfc.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
}
|
||||
_etext = .;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rodata*)
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
__got2_start = .;
|
||||
*(.got2)
|
||||
__got2_end = .;
|
||||
}
|
||||
|
||||
_edata = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss)
|
||||
*(.bss)
|
||||
}
|
||||
|
||||
_end = . ;
|
||||
}
|
100
nand_spl/board/amcc/bamboo/Makefile
Normal file
100
nand_spl/board/amcc/bamboo/Makefile
Normal file
|
@ -0,0 +1,100 @@
|
|||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
|
||||
|
||||
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
|
||||
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
|
||||
AFLAGS += -DCONFIG_NAND_SPL
|
||||
CFLAGS += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o init.o resetvec.o
|
||||
COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o
|
||||
|
||||
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
__OBJS := $(SOBJS) $(COBJS)
|
||||
LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
|
||||
|
||||
nandobj := $(OBJTREE)/nand_spl/
|
||||
|
||||
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
|
||||
|
||||
all: $(obj).depend $(ALL)
|
||||
|
||||
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl: $(OBJS)
|
||||
cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
|
||||
-Map $(nandobj)u-boot-spl.map \
|
||||
-o $(nandobj)u-boot-spl
|
||||
|
||||
# create symbolic links for common files
|
||||
|
||||
# from cpu directory
|
||||
$(obj)ndfc.c:
|
||||
@rm -f $(obj)ndfc.c
|
||||
ln -s $(SRCTREE)/cpu/ppc4xx/ndfc.c $(obj)ndfc.c
|
||||
|
||||
$(obj)resetvec.S:
|
||||
@rm -f $(obj)resetvec.S
|
||||
ln -s $(SRCTREE)/cpu/ppc4xx/resetvec.S $(obj)resetvec.S
|
||||
|
||||
$(obj)start.S:
|
||||
@rm -f $(obj)start.S
|
||||
ln -s $(SRCTREE)/cpu/ppc4xx/start.S $(obj)start.S
|
||||
|
||||
# from board directory
|
||||
$(obj)init.S:
|
||||
@rm -f $(obj)init.S
|
||||
ln -s $(SRCTREE)/board/amcc/bamboo/init.S $(obj)init.S
|
||||
|
||||
# from nand_spl directory
|
||||
$(obj)nand_boot.c:
|
||||
@rm -f $(obj)nand_boot.c
|
||||
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
|
||||
|
||||
# from drivers/nand directory
|
||||
$(obj)nand_ecc.c:
|
||||
@rm -f $(obj)nand_ecc.c
|
||||
ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c
|
||||
|
||||
#########################################################################
|
||||
|
||||
$(obj)%.o: $(obj)%.S
|
||||
$(CC) $(AFLAGS) -c -o $@ $<
|
||||
|
||||
$(obj)%.o: $(obj)%.c
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
49
nand_spl/board/amcc/bamboo/config.mk
Normal file
49
nand_spl/board/amcc/bamboo/config.mk
Normal file
|
@ -0,0 +1,49 @@
|
|||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
#
|
||||
# AMCC 440EP Reference Platform (Bamboo) board
|
||||
#
|
||||
|
||||
#
|
||||
# TEXT_BASE for SPL:
|
||||
#
|
||||
# On 440EP(x) platforms the SPL is located at 0xfffff000...0xffffffff,
|
||||
# in the last 4kBytes of memory space in cache.
|
||||
# We will copy this SPL into instruction-cache in start.S. So we set
|
||||
# TEXT_BASE to starting address in i-cache here.
|
||||
#
|
||||
TEXT_BASE = 0x00800000
|
||||
|
||||
# PAD_TO used to generate a 16kByte binary needed for the combined image
|
||||
# -> PAD_TO = TEXT_BASE + 0x4000
|
||||
PAD_TO = 0x00804000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DCONFIG_440=1
|
||||
|
||||
ifeq ($(debug),1)
|
||||
PLATFORM_CPPFLAGS += -DDEBUG
|
||||
endif
|
||||
|
||||
ifeq ($(dbcr),1)
|
||||
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
|
||||
endif
|
92
nand_spl/board/amcc/bamboo/sdram.c
Normal file
92
nand_spl/board/amcc/bamboo/sdram.c
Normal file
|
@ -0,0 +1,92 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ppc4xx.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
static void wait_init_complete(void)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
do {
|
||||
mfsdram(mem_mcsts, val);
|
||||
} while (!(val & 0x80000000));
|
||||
}
|
||||
|
||||
/*
|
||||
* early_sdram_init()
|
||||
*
|
||||
* As the name already indicates, this function is called very early
|
||||
* from start.S and configures the SDRAM with fixed values. This is needed,
|
||||
* since the 440EP has no internal SRAM and the 4kB NAND_SPL loader has
|
||||
* not enough free space to implement the complete I2C SPD DDR autodetection
|
||||
* routines. Therefore the Bamboo only supports the onboard 64MBytes of SDRAM
|
||||
* when booting from NAND flash.
|
||||
*/
|
||||
void early_sdram_init(void)
|
||||
{
|
||||
/*
|
||||
* Soft-reset SDRAM controller.
|
||||
*/
|
||||
mtsdr(sdr_srst, SDR0_SRST_DMC);
|
||||
mtsdr(sdr_srst, 0x00000000);
|
||||
|
||||
/*
|
||||
* Disable memory controller.
|
||||
*/
|
||||
mtsdram(mem_cfg0, 0x00000000);
|
||||
|
||||
/*
|
||||
* Setup some default
|
||||
*/
|
||||
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
|
||||
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
|
||||
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
|
||||
mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
|
||||
mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
|
||||
|
||||
/*
|
||||
* Following for CAS Latency = 2.5 @ 133 MHz PLB
|
||||
*/
|
||||
mtsdram(mem_b0cr, 0x00082001);
|
||||
mtsdram(mem_tr0, 0x41094012);
|
||||
mtsdram(mem_tr1, 0x8080083d); /* SS=T2 SL=STAGE 3 CD=1 CT=0x00*/
|
||||
mtsdram(mem_rtr, 0x04100000); /* Interval 7.8µs @ 133MHz PLB */
|
||||
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM*/
|
||||
|
||||
/*
|
||||
* Enable the controller, then wait for DCEN to complete
|
||||
*/
|
||||
mtsdram(mem_cfg0, 0x80000000); /* DCEN=1, PMUD=0*/
|
||||
wait_init_complete();
|
||||
}
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
/*
|
||||
* Nothing to do here, just return size of fixed SDRAM setup
|
||||
*/
|
||||
return CFG_MBYTES_SDRAM << 20;
|
||||
}
|
65
nand_spl/board/amcc/bamboo/u-boot.lds
Normal file
65
nand_spl/board/amcc/bamboo/u-boot.lds
Normal file
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc:common)
|
||||
SECTIONS
|
||||
{
|
||||
.resetvec 0x00800FFC :
|
||||
{
|
||||
*(.resetvec)
|
||||
} = 0xffff
|
||||
|
||||
.text :
|
||||
{
|
||||
start.o (.text)
|
||||
init.o (.text)
|
||||
nand_boot.o (.text)
|
||||
sdram.o (.text)
|
||||
ndfc.o (.text)
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
}
|
||||
_etext = .;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.rodata*)
|
||||
*(.data*)
|
||||
*(.sdata*)
|
||||
__got2_start = .;
|
||||
*(.got2)
|
||||
__got2_end = .;
|
||||
}
|
||||
|
||||
_edata = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss)
|
||||
*(.bss)
|
||||
}
|
||||
|
||||
_end = . ;
|
||||
}
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# (C) Copyright 2006
|
||||
# (C) Copyright 2006-2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
|
@ -30,7 +30,7 @@ AFLAGS += -DCONFIG_NAND_SPL
|
|||
CFLAGS += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o init.o resetvec.o
|
||||
COBJS = nand_boot.o ndfc.o sdram.o
|
||||
COBJS = nand_boot.o nand_ecc.o ndfc.o sdram.o
|
||||
|
||||
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
@ -85,6 +85,11 @@ $(obj)nand_boot.c:
|
|||
@rm -f $(obj)nand_boot.c
|
||||
ln -s $(SRCTREE)/nand_spl/nand_boot.c $(obj)nand_boot.c
|
||||
|
||||
# from drivers/nand directory
|
||||
$(obj)nand_ecc.c:
|
||||
@rm -f $(obj)nand_ecc.c
|
||||
ln -s $(SRCTREE)/drivers/nand/nand_ecc.c $(obj)nand_ecc.c
|
||||
|
||||
#########################################################################
|
||||
|
||||
$(obj)%.o: $(obj)%.S
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* (C) Copyright 2006
|
||||
* (C) Copyright 2006-2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
|
@ -24,27 +24,28 @@
|
|||
#define CFG_NAND_READ_DELAY \
|
||||
{ volatile int dummy; int i; for (i=0; i<10000; i++) dummy = i; }
|
||||
|
||||
extern void board_nand_init(struct nand_chip *nand);
|
||||
extern void ndfc_hwcontrol(struct mtd_info *mtdinfo, int cmd);
|
||||
extern void ndfc_write_byte(struct mtd_info *mtdinfo, u_char byte);
|
||||
extern u_char ndfc_read_byte(struct mtd_info *mtdinfo);
|
||||
extern int ndfc_dev_ready(struct mtd_info *mtdinfo);
|
||||
extern int jump_to_ram(ulong delta);
|
||||
extern int jump_to_uboot(ulong addr);
|
||||
static int nand_ecc_pos[] = CFG_NAND_ECCPOS;
|
||||
|
||||
static int nand_is_bad_block(struct mtd_info *mtd, int block)
|
||||
extern void board_nand_init(struct nand_chip *nand);
|
||||
|
||||
static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
int page_addr = block * CFG_NAND_PAGE_COUNT;
|
||||
int page_addr = page + block * CFG_NAND_PAGE_COUNT;
|
||||
|
||||
if (this->dev_ready)
|
||||
this->dev_ready(mtd);
|
||||
else
|
||||
CFG_NAND_READ_DELAY;
|
||||
|
||||
/* Begin command latch cycle */
|
||||
this->hwcontrol(mtd, NAND_CTL_SETCLE);
|
||||
this->write_byte(mtd, NAND_CMD_READOOB);
|
||||
this->write_byte(mtd, cmd);
|
||||
/* Set ALE and clear CLE to start address cycle */
|
||||
this->hwcontrol(mtd, NAND_CTL_CLRCLE);
|
||||
this->hwcontrol(mtd, NAND_CTL_SETALE);
|
||||
/* Column address */
|
||||
this->write_byte(mtd, CFG_NAND_BAD_BLOCK_POS); /* A[7:0] */
|
||||
this->write_byte(mtd, offs); /* A[7:0] */
|
||||
this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */
|
||||
this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */
|
||||
#ifdef CFG_NAND_4_ADDR_CYCLE
|
||||
|
@ -62,6 +63,15 @@ static int nand_is_bad_block(struct mtd_info *mtd, int block)
|
|||
else
|
||||
CFG_NAND_READ_DELAY;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int nand_is_bad_block(struct mtd_info *mtd, int block)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
|
||||
nand_command(mtd, block, 0, CFG_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
|
||||
|
||||
/*
|
||||
* Read on byte
|
||||
*/
|
||||
|
@ -74,39 +84,46 @@ static int nand_is_bad_block(struct mtd_info *mtd, int block)
|
|||
static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
|
||||
{
|
||||
struct nand_chip *this = mtd->priv;
|
||||
int page_addr = page + block * CFG_NAND_PAGE_COUNT;
|
||||
u_char *ecc_calc;
|
||||
u_char *ecc_code;
|
||||
u_char *oob_data;
|
||||
int i;
|
||||
int eccsize = CFG_NAND_ECCSIZE;
|
||||
int eccbytes = CFG_NAND_ECCBYTES;
|
||||
int eccsteps = CFG_NAND_ECCSTEPS;
|
||||
uint8_t *p = dst;
|
||||
int stat;
|
||||
|
||||
/* Begin command latch cycle */
|
||||
this->hwcontrol(mtd, NAND_CTL_SETCLE);
|
||||
this->write_byte(mtd, NAND_CMD_READ0);
|
||||
/* Set ALE and clear CLE to start address cycle */
|
||||
this->hwcontrol(mtd, NAND_CTL_CLRCLE);
|
||||
this->hwcontrol(mtd, NAND_CTL_SETALE);
|
||||
/* Column address */
|
||||
this->write_byte(mtd, 0); /* A[7:0] */
|
||||
this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[16:9] */
|
||||
this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[24:17] */
|
||||
#ifdef CFG_NAND_4_ADDR_CYCLE
|
||||
/* One more address cycle for devices > 32MiB */
|
||||
this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:25] */
|
||||
#endif
|
||||
/* Latch in address */
|
||||
this->hwcontrol(mtd, NAND_CTL_CLRALE);
|
||||
nand_command(mtd, block, page, 0, NAND_CMD_READ0);
|
||||
|
||||
/*
|
||||
* Wait a while for the data to be ready
|
||||
/* No malloc available for now, just use some temporary locations
|
||||
* in SDRAM
|
||||
*/
|
||||
if (this->dev_ready)
|
||||
this->dev_ready(mtd);
|
||||
else
|
||||
CFG_NAND_READ_DELAY;
|
||||
ecc_calc = (u_char *)(CFG_SDRAM_BASE + 0x10000);
|
||||
ecc_code = ecc_calc + 0x100;
|
||||
oob_data = ecc_calc + 0x200;
|
||||
|
||||
/*
|
||||
* Read page into buffer
|
||||
*/
|
||||
for (i=0; i<CFG_NAND_PAGE_SIZE; i++)
|
||||
*dst++ = this->read_byte(mtd);
|
||||
for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
|
||||
this->enable_hwecc(mtd, NAND_ECC_READ);
|
||||
this->read_buf(mtd, p, eccsize);
|
||||
this->calculate_ecc(mtd, p, &ecc_calc[i]);
|
||||
}
|
||||
this->read_buf(mtd, oob_data, CFG_NAND_OOBSIZE);
|
||||
|
||||
/* Pick the ECC bytes out of the oob data */
|
||||
for (i = 0; i < CFG_NAND_ECCTOTAL; i++)
|
||||
ecc_code[i] = oob_data[nand_ecc_pos[i]];
|
||||
|
||||
eccsteps = CFG_NAND_ECCSTEPS;
|
||||
p = dst;
|
||||
|
||||
for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
|
||||
/* No chance to do something with the possible error message
|
||||
* from correct_data(). We just hope that all possible errors
|
||||
* are corrected by this routine.
|
||||
*/
|
||||
stat = this->correct_data(mtd, p, &ecc_code[i], &ecc_calc[i]);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
Loading…
Reference in a new issue