Update header file and some clean up
Replaced immap_5329.h and m5329.h with immap.h. Removed whitespaces. Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
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@ -28,23 +28,22 @@
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#include <common.h>
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/processor.h>
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#include <asm/m5329.h>
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#include <asm/immap.h>
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#include <asm/immap_5329.h>
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/* PLL min/max specifications */
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/* PLL min/max specifications */
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#define MAX_FVCO 500000 /* KHz */
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#define MAX_FVCO 500000 /* KHz */
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#define MAX_FSYS 80000 /* KHz */
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#define MAX_FSYS 80000 /* KHz */
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#define MIN_FSYS 58333 /* KHz */
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#define MIN_FSYS 58333 /* KHz */
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#define FREF 16000 /* KHz */
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#define FREF 16000 /* KHz */
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#define MAX_MFD 135 /* Multiplier */
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#define MAX_MFD 135 /* Multiplier */
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#define MIN_MFD 88 /* Multiplier */
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#define MIN_MFD 88 /* Multiplier */
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#define BUSDIV 6 /* Divider */
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#define BUSDIV 6 /* Divider */
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/*
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/*
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* Low Power Divider specifications
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* Low Power Divider specifications
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*/
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*/
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#define MIN_LPD (1 << 0) /* Divider (not encoded) */
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#define MIN_LPD (1 << 0) /* Divider (not encoded) */
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#define MAX_LPD (1 << 15) /* Divider (not encoded) */
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#define MAX_LPD (1 << 15) /* Divider (not encoded) */
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#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
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#define DEFAULT_LPD (1 << 1) /* Divider (not encoded) */
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/*
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/*
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* Get the value of the current system clock
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* Get the value of the current system clock
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@ -174,9 +173,6 @@ int clock_pll(int fsys, int flags)
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* If it has then the SDRAM needs to be put into self refresh
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* If it has then the SDRAM needs to be put into self refresh
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* mode before reprogramming the PLL.
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* mode before reprogramming the PLL.
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*/
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*/
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/* Put SDRAM into self refresh mode */
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/* if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
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MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;*/
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/*
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/*
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* Initialize the PLL to generate the new system clock frequency.
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* Initialize the PLL to generate the new system clock frequency.
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@ -197,12 +193,10 @@ int clock_pll(int fsys, int flags)
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/*
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/*
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* Return the SDRAM to normal operation if it is in use.
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* Return the SDRAM to normal operation if it is in use.
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*/
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*/
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/* Exit self refresh mode */
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/* if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
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MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_CKE;*/
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/* software workaround for SDRAM opeartion after exiting LIMP mode errata */
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/* software workaround for SDRAM opeartion after exiting LIMP mode errata */
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*sdram_workaround = CFG_SDRAM_BASE;
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*sdram_workaround = CFG_SDRAM_BASE;
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/* wait for DQS logic to relock */
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/* wait for DQS logic to relock */
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for (i = 0; i < 0x200; i++) ;
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for (i = 0; i < 0x200; i++) ;
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