Merge with git://www.denx.de/git/u-boot.git
This commit is contained in:
commit
bd38b7ecfd
816
CHANGELOG
816
CHANGELOG
|
@ -1,3 +1,393 @@
|
|||
commit 6923565db12af34fd5e02d354ee65a8c78ac460f
|
||||
Author: Detlev Zundel <dzu@denx.de>
|
||||
Date: Fri Apr 20 12:01:47 2007 +0200
|
||||
|
||||
Fix breakage of NC650 board with respect to nand support.
|
||||
|
||||
Signed-off-by: Detlev Zundel <dzu@denx.de>
|
||||
|
||||
commit 39f23cd90947639ac278a18ff277ec786b5ac167
|
||||
Author: Domen Puncer <domen.puncer@telargo.com>
|
||||
Date: Fri Apr 20 11:13:16 2007 +0200
|
||||
|
||||
[RFC PATCH] icecube/lite5200b: fix OF_TBCLK (timebase-frequency) calculation
|
||||
|
||||
G2 core reference manual says decrementer and time base
|
||||
are decreasing/increasing once every 4 bus clock cycles.
|
||||
Lets fix it, so time in Linux won't run twice as fast
|
||||
|
||||
Signed-off-by: Domen Puncer <domen.puncer@telargo.com>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
|
||||
commit 7651f8bdbba03bb0b4f241e2d2c4cb65b230bd56
|
||||
Author: Gerald Van Baren <vanbaren@cideas.com>
|
||||
Date: Thu Apr 19 23:14:39 2007 -0400
|
||||
|
||||
Fix serious pointer bug with bootm and reserve map.
|
||||
|
||||
What was suppose to be a stack variable was declared as a pointer,
|
||||
overwriting random memory.
|
||||
Also moved the libfdt.a requirement into the main Makefile. That is
|
||||
The U-Boot Way.
|
||||
|
||||
commit 37837828d89084879bee2f2b8c7c68d4695940df
|
||||
Author: Wolfgang Denk <wd@denx.de>
|
||||
Date: Wed Apr 18 17:49:29 2007 +0200
|
||||
|
||||
Clenaup, update CHANGELOG
|
||||
|
||||
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
||||
|
||||
commit fd094c6379e2ef8a4d0ceb5640b24cb0c8d04449
|
||||
Author: Wolfgang Denk <wd@denx.de>
|
||||
Date: Wed Apr 18 17:20:58 2007 +0200
|
||||
|
||||
Update CHANGELOG
|
||||
|
||||
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
||||
|
||||
commit 2a26ec4732efd7a308d0bbc97714c1d75ef1173b
|
||||
Author: Wolfgang Denk <wd@denx.de>
|
||||
Date: Wed Apr 18 17:07:26 2007 +0200
|
||||
|
||||
Cleanup, update CHANGELOG
|
||||
|
||||
Sigend-off-by: Wolfgang Denk <wd@denx.de>
|
||||
|
||||
commit 5f6c732affea9647762d27a4617a2ae64c52dceb
|
||||
Author: Wolfgang Denk <wd@denx.de>
|
||||
Date: Wed Apr 18 16:17:46 2007 +0200
|
||||
|
||||
Update CHANGELOG
|
||||
|
||||
commit ad4eb555671d97f96dc56eab55103b1f86874b01
|
||||
Author: Wolfgang Denk <wd@denx.de>
|
||||
Date: Wed Apr 18 14:30:39 2007 +0200
|
||||
|
||||
MCC200 board: remove warning which is obsolete after PSoC firmware changes
|
||||
|
||||
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
||||
|
||||
commit 3747a3f010b2b1442dec3e871c69788b6017aaae
|
||||
Author: Domen Puncer <domen.puncer@telargo.com>
|
||||
Date: Wed Apr 18 12:11:05 2007 +0200
|
||||
|
||||
[PATCH] icecube/lite5200b: document wakeup from low-power support
|
||||
|
||||
Signed-off-by: Domen Puncer <domen.puncer@telargo.com>
|
||||
|
||||
commit e673226ff9d6aa91b47ceac74b8c13770b06bb37
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Wed Apr 18 12:07:47 2007 +0200
|
||||
|
||||
ppc4xx: Update Acadia to not setup PLL when booting via bootstrap EEPROM
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 90e6f41cf09fc98f6ccb510e183d53ab8546cf2f
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Wed Apr 18 12:05:59 2007 +0200
|
||||
|
||||
ppc4xx: Add output for bootrom location to 405EZ ports
|
||||
|
||||
Now 405EZ ports also show upon bootup from which boot device
|
||||
they are configured to boot:
|
||||
|
||||
U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05)
|
||||
|
||||
CPU: AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz)
|
||||
Bootstrap Option E - Boot ROM Location EBC (32 bits)
|
||||
16 kB I-Cache 16 kB D-Cache
|
||||
Board: Acadia - AMCC PPC405EZ Evaluation Board
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 9c00dfb0bf89c8c23e8af5b5bdf49cf66d769f85
|
||||
Author: Peter Pearse <peter.pearse@arm.com>
|
||||
Date: Tue Apr 17 13:30:33 2007 +0100
|
||||
|
||||
Move ppearse to ARM board list
|
||||
Add Konstantin Kletschke for scb9328.
|
||||
Signed-off-by: Peter Pearse <peter.pearse@arm.com>
|
||||
|
||||
commit d3832e8fe1b214ec62424eac36cfda9fc56d21b3
|
||||
Author: Domen Puncer <domen.puncer@telargo.com>
|
||||
Date: Mon Apr 16 14:00:13 2007 +0200
|
||||
|
||||
[PATCH] icecube/lite5200b: wakeup from low-power support
|
||||
|
||||
U-Boot part of Lite5200b low power mode support.
|
||||
Puts SDRAM out of self-refresh and transfers control to
|
||||
address saved at physical 0x0.
|
||||
|
||||
Signed-off-by: Domen Puncer <domen.puncer@telargo.com>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
|
||||
commit f35a53fc7b0c79fcfe7bdc01163c4b34aaba1460
|
||||
Author: Gerald Van Baren <vanbaren@cideas.com>
|
||||
Date: Sun Apr 15 13:54:26 2007 -0400
|
||||
|
||||
Fix the ft_cpu_setup() property settings.
|
||||
|
||||
Use "setter" functions instead of flags, cleaner and more flexible.
|
||||
It also fixes the problem noted by Timur Tabi that the ethernet MAC
|
||||
addresses were all being set incorrectly to the same MAC address.
|
||||
|
||||
commit c28abb9c614f65ce2096cc4a66fc886c77d0e5a4
|
||||
Author: Gerald Van Baren <vanbaren@cideas.com>
|
||||
Date: Sat Apr 14 22:51:24 2007 -0400
|
||||
|
||||
Improve the bootm command for CONFIG_OF_LIBFDT
|
||||
|
||||
In bootm, create the "/chosen" node only if it doesn't already exist
|
||||
(better matches the previous behavior).
|
||||
Update for proper reserved memory map handling for initrd.
|
||||
|
||||
commit 3f9f08cf91c8a6949a5d78a18bd3d8df7b86d888
|
||||
Author: Gerald Van Baren <vanbaren@cideas.com>
|
||||
Date: Sat Apr 14 22:46:41 2007 -0400
|
||||
|
||||
Add some utilities to manipulate the reserved memory map.
|
||||
|
||||
commit 8048cdd56f04a756eeea4951f402bf5cc33785db
|
||||
Author: Wolfgang Denk <wd@denx.de>
|
||||
Date: Sat Apr 14 21:16:54 2007 +0200
|
||||
|
||||
Update CHANGELOG
|
||||
|
||||
commit 8e6875183cdca91c134408d119d4abcd48ef6856
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Sun Dec 17 18:56:46 2006 +0100
|
||||
|
||||
AVR32: Enable MMC support
|
||||
|
||||
Set up the portmux for the MMC interface and enable the MMC driver
|
||||
along with support for DOS partitions, ext2 and FAT filesystems.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit fc26c97bb6df41b4a95662c34054fe912387bf38
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Fri Jan 20 10:03:53 2006 +0100
|
||||
|
||||
Atmel MCI driver
|
||||
|
||||
Driver for the Atmel MCI controller (MMC interface) for AT32AP CPUs.
|
||||
|
||||
The AT91 ARM-based CPUs use basically the same hardware, so it should
|
||||
be possible to share this driver, but no effort has been made so far.
|
||||
|
||||
Hardware documentation can be found in the AT32AP7000 data sheet,
|
||||
which can be downloaded from
|
||||
|
||||
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit 05fdab1ef6a10d049a50021a86f1226f444d9b9f
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Sun Dec 17 18:55:37 2006 +0100
|
||||
|
||||
AVR32: Add clk and gpio infrastructure for mmci
|
||||
|
||||
Implement functions for configuring the mmci pins, as well as
|
||||
functions for getting the clock rate of the mmci controller.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit 7fac3f69e9f05c5e5326681976c35d129324c4de
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Sun Dec 17 18:53:56 2006 +0100
|
||||
|
||||
Enable partition support with MMC
|
||||
|
||||
Include implementations of init_part() and get_partition_info() when
|
||||
CONFIG_MMC is set.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit 9a24f477a1ed5bb0f74377c985d754ebbfa44872
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Sun Dec 17 17:14:30 2006 +0100
|
||||
|
||||
AVR32: Enable networking
|
||||
|
||||
Implement MACB initialization for AVR32 and ATSTK1000, and turn
|
||||
everything on, including the MACB driver.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit 5c1fe1ffffd1750a7e47e5a2e2cd600c00e4f009
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Fri Jan 20 10:03:34 2006 +0100
|
||||
|
||||
Atmel MACB ethernet driver
|
||||
|
||||
Driver for the Atmel MACB on-chip ethernet controller.
|
||||
|
||||
This driver has been tested on the ATSTK1000 board with a AT32AP7000
|
||||
CPU. It should probably work on AT91SAM926x as well with some minor
|
||||
modifications.
|
||||
|
||||
Hardware documentation can be found in the AT32AP7000 data sheet,
|
||||
which can be downloaded from
|
||||
|
||||
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit b4ec9c2d43d894729bb633bfdbdfa95a962c1556
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Sun Dec 17 16:56:14 2006 +0100
|
||||
|
||||
AVR32: Add clk and gpio infrastructure for macb0 and macb1
|
||||
|
||||
Implement functions for configuring the macb0 and macb1 pins, as
|
||||
well as functions for getting the clock rate of the various
|
||||
busses the macb ethernet controllers are connected to.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit d5acb95b16a0a74c643524342c3437e765426d05
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Sun Dec 17 15:39:15 2006 +0100
|
||||
|
||||
AVR32: Implement simple DMA memory allocator
|
||||
|
||||
Implement dma_alloc_coherent() which returns cache-aligned
|
||||
uncacheable memory.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit 91975b0fea773c9e681fea8cf3349669f27685ee
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Sun Dec 17 15:46:02 2006 +0100
|
||||
|
||||
Import <linux/mii.h> from the Linux kernel
|
||||
|
||||
Instead of creating yet another set of MII register definitions
|
||||
in the macb driver, here's a complete set of definitions for everyone
|
||||
to use.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit 1b804b229556a4d862da93c0ec94e79419364b2c
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Wed Mar 21 19:47:36 2007 +0100
|
||||
|
||||
AVR32: Include more commands for ATSTK1000
|
||||
|
||||
Include the imi, imls and jffs commands sets by default on ATSTK1000.
|
||||
Also define CONFIG_BOOTARGS to something more useful, define
|
||||
CONFIG_BOOTCOMMAND and enable autoboot by default.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit 9c0deb5ae3ea0189f2e08ac29ef1316f1fb8548d
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Wed Mar 21 19:44:48 2007 +0100
|
||||
|
||||
AVR32: Provide a definition of struct stat
|
||||
|
||||
Copy the definition of struct stat from the Linux kernel.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit 12f099c08167a7a51aeee623bc16dafd0841271c
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Sun Dec 17 14:46:06 2006 +0100
|
||||
|
||||
AVR32: Use initdram() instead of board_init_memories()
|
||||
|
||||
Conform to the "standard" interface and use initdram() instead of
|
||||
board_init_memories() on AVR32. This enables us to get rid of the
|
||||
sdram_size member of the global_data struct as well.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit 1f4f2121c2685182eb87fa9a9b799d1917387a1c
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Mon Nov 20 15:53:10 2006 +0100
|
||||
|
||||
AVR32: Relocate u-boot to SDRAM
|
||||
|
||||
Relocate the u-boot image into SDRAM like everyone else does. This
|
||||
means that we can handle much larger .data and .bss than we used to.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit df548d3c3e2bbc40258713167859ffc2ce99a900
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Sun Nov 19 18:06:53 2006 +0100
|
||||
|
||||
AVR32: Resource management rewrite
|
||||
|
||||
Rewrite the resource management code (i.e. I/O memory, clock gating,
|
||||
gpio) so it doesn't depend on any global state. This is necessary
|
||||
because this code is heavily used before relocation to RAM, so we
|
||||
can't write to any global variables.
|
||||
|
||||
As an added bonus, this makes u-boot's memory footprint a bit smaller,
|
||||
although some functionality has been left out; all clocks are enabled
|
||||
all the time, and there's no checking for gpio line conflicts.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit 03d1e1365796cd15d1726e8a51fd8b5be50b2fe9
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Sat Nov 18 18:01:13 2006 +0100
|
||||
|
||||
AVR32: Clean up memory-map.h for at32ap7000
|
||||
|
||||
Convert spaces to tabs (must have missed this one last time around),
|
||||
sort the entries by address and group them together by bus
|
||||
connectivity.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit 28c699ef69f4b6cdf252e4747b7b590028a88981
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Sat Nov 18 17:32:31 2006 +0100
|
||||
|
||||
AVR32: Build position-independent u-boot
|
||||
|
||||
Add -fPIC -mno-init-got to the avr32-specific CFLAGS to make u-boot
|
||||
position independent. This will make relocation a lot easier.
|
||||
|
||||
-mno-init-got means that gcc shouldn't emit code to load the GOT
|
||||
address into r6 in every function prologue. We do it once and for
|
||||
all in the early startup assembly code, so enabling this option
|
||||
makes u-boot a bit faster and smaller.
|
||||
|
||||
The assembly parts have always been position-independent, so no code
|
||||
changes should be necessary.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit 5374b36de91d006d1df9536259fa9f66b01aa3aa
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Sat Nov 18 17:24:31 2006 +0100
|
||||
|
||||
AVR32: Use avr32-linux- cross-compilation prefix by default
|
||||
|
||||
It doesn't really matter which toolchain you use to compile u-boot,
|
||||
but the avr32-linux one is probably what most people have installed.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit c841beeddebece0039e724fb27f4d1a39ee1c6b6
|
||||
Author: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
Date: Sat Nov 18 17:15:30 2006 +0100
|
||||
|
||||
AVR32: Split start_u_boot into board_init_f and board_init_r
|
||||
|
||||
Split the avr32 initialization code into a function to run before
|
||||
relocation, board_init_f and a function to run after relocation,
|
||||
board_init_r. For now, board_init_f simply calls board_init_r
|
||||
at the end.
|
||||
|
||||
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
|
||||
|
||||
commit 37403005cfe6bb13964d450f6a48a0b0f2f7017e
|
||||
Author: Heiko Schocher <hs@pollux.denx.de>
|
||||
Date: Sat Apr 14 05:26:48 2007 +0200
|
||||
|
@ -7,6 +397,42 @@ Date: Sat Apr 14 05:26:48 2007 +0200
|
|||
|
||||
Signed-off-by: Heiko Schocher <hs@denx.de>
|
||||
|
||||
commit 7882751c78b7ecabfd49b0eff8de27661c71f16c
|
||||
Author: Denis Peter <d.peter@mpl.ch>
|
||||
Date: Fri Apr 13 09:13:33 2007 +0200
|
||||
|
||||
[PATCH] Fix bugs in cmd_ide.c and cmd_scsi.c
|
||||
|
||||
Fix bug introduced by "Fix get_partition_info() parameter error in all
|
||||
other calls" from 2005-03-04 in cmd_ide.c and cmd_scsi.c, which prevented
|
||||
to use diskboot or scsiboot form another device than 0.
|
||||
|
||||
Signed-off-by: Denis Peter <d.peter@mpl.ch>
|
||||
|
||||
commit 0b94504d22e70f537c17a0d38c87edb6e370977d
|
||||
Author: Greg Lopp <lopp@pobox.com>
|
||||
Date: Fri Apr 13 08:02:24 2007 +0200
|
||||
|
||||
[PATCH] Fix use of "void *" for block dev read/write buffer pointers
|
||||
|
||||
Signed-of-by: Greg Lopp <lopp@pobox.com>
|
||||
Acked-by: Grant Likely <grant.likely@secretlab.ca>
|
||||
|
||||
commit 2ad3aba01d37b72e7c957b07e102fccd64fe6d13
|
||||
Author: Jeffrey Mann <mannj@embeddedplanet.com>
|
||||
Date: Thu Apr 12 14:15:59 2007 +0200
|
||||
|
||||
ppc4xx: Fix i2c divisor calcularion for PPC4xx
|
||||
|
||||
This patch fixes changes the i2c_init(...) function to use the function
|
||||
get_OPB_freq() rather than calculating the OPB speed by
|
||||
sysInfo.freqPLB/sysInfo.pllOpbDiv. The get_OPB_freq() function is
|
||||
specific per processor. The prior method was not and so was calculating
|
||||
the wrong speed for some PPC4xx processors.
|
||||
|
||||
Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 6c9ba919375db977aaad9146bf320c7afd07ae7a
|
||||
Author: Wolfgang Denk <wd@denx.de>
|
||||
Date: Wed Apr 11 17:25:01 2007 +0200
|
||||
|
@ -25,6 +451,106 @@ Date: Wed Apr 11 17:22:55 2007 +0200
|
|||
* Use Newline as "password" string
|
||||
* Use just a single partition in NAND flash
|
||||
|
||||
commit 3d98b85800c80dc68227c8f10bf5c93456d6d054
|
||||
Author: Haiying Wang <haiying.wang@freescale.com>
|
||||
Date: Mon Jan 22 12:37:30 2007 -0600
|
||||
|
||||
Add PIXIS FPGA support for MPC8641HPCN board.
|
||||
|
||||
Move the 8641HPCN's PIXIS code to the new directory
|
||||
board/freescale/common/ as it will be shared by
|
||||
future boards not in the same processor family.
|
||||
|
||||
Write a "pixis_reset" command that utilizes the FPGA
|
||||
reset sequencer to support alternate soft-reset options
|
||||
such as using the "alternate" flash bank, enabling
|
||||
the watch dog, or choosing different CPU frequencies.
|
||||
|
||||
Add documentation for the pixis_reset to README.mpc8641hpcn.
|
||||
|
||||
Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
|
||||
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
||||
|
||||
commit 64dbbd40c58349b64f43fd33dbb5ca0adb67d642
|
||||
Author: Gerald Van Baren <vanbaren@cideas.com>
|
||||
Date: Fri Apr 6 14:19:43 2007 -0400
|
||||
|
||||
Moved fdt command support code to fdt_support.c
|
||||
|
||||
...in preparation for improving the bootm command's handling of fdt blobs.
|
||||
Also cleaned up some coding sloppiness.
|
||||
|
||||
commit 6679f9299534e488a171a9bb8f9bb891de247aab
|
||||
Author: Gerald Van Baren <vanbaren@cideas.com>
|
||||
Date: Fri Apr 6 14:17:14 2007 -0400
|
||||
|
||||
libfdt: Make fdt_check_header() public
|
||||
|
||||
Changed _fdt_check_header() to fdt_check_header() and made it part of
|
||||
the interface - it is a useful routine.
|
||||
|
||||
Also did some asthetics cleanup to the include files (headers).
|
||||
|
||||
commit c0707ce65677650b5ceab0500ee50ae5168afef2
|
||||
Author: Aubrey Li <aubrey.adi@gmail.com>
|
||||
Date: Thu Apr 5 18:34:06 2007 +0800
|
||||
|
||||
[Blackfin][PATCH] Kill off a bunch of common local prototypes
|
||||
|
||||
commit 7b7e30aa64bb6657a1bfd32fdbdbfeb561e6a48d
|
||||
Author: Aubrey Li <aubrey.adi@gmail.com>
|
||||
Date: Thu Apr 5 18:33:04 2007 +0800
|
||||
|
||||
[Blackfin][PATCH] Fix dynamic CPLB generation issue
|
||||
|
||||
commit 0445e3a264251d75b1be45ef713c70726a2952f0
|
||||
Author: Aubrey Li <aubrey.adi@gmail.com>
|
||||
Date: Thu Apr 5 18:31:47 2007 +0800
|
||||
|
||||
[Blackfin][PATCH] minior cleanup
|
||||
|
||||
commit 155fd766573981090e638b493d5857562151862e
|
||||
Author: Aubrey Li <aubrey.adi@gmail.com>
|
||||
Date: Thu Apr 5 18:31:18 2007 +0800
|
||||
|
||||
[Blackfin][PATCH] Fix copyright and update license
|
||||
|
||||
commit 9fd437bbd75d282f899e1da50be20a2bf38450bc
|
||||
Author: Aubrey Li <aubrey.adi@gmail.com>
|
||||
Date: Thu Apr 5 18:30:25 2007 +0800
|
||||
|
||||
[Blackfin][PATCH] Add BF537 EMAC driver initialization
|
||||
|
||||
commit 889256e8604e0c68db1d866d720894dffede9df6
|
||||
Author: Aubrey Li <aubrey.adi@gmail.com>
|
||||
Date: Thu Apr 5 18:29:55 2007 +0800
|
||||
|
||||
[Blackfin][PATCH] call real the system synchronize instruction
|
||||
|
||||
commit e0df1c921b788289564e4c1ee7120a6a9cd3ab05
|
||||
Author: Aubrey Li <aubrey.adi@gmail.com>
|
||||
Date: Thu Apr 5 18:29:17 2007 +0800
|
||||
|
||||
[Blackfin][PATCH] remove asm/page.h as we do not actually use/want any of these definitions nor does any other arch include it
|
||||
|
||||
commit dfeeab2cd680df047e68e723b246adf6f33bb556
|
||||
Author: Aubrey Li <aubrey.adi@gmail.com>
|
||||
Date: Thu Apr 5 18:28:34 2007 +0800
|
||||
|
||||
[Blackfin][PATCH]: fix flash unaligned copy issue
|
||||
|
||||
commit 443feb740584e406efa203af909fe2926608e8d5
|
||||
Author: Igor Marnat <marny@rambler.ru>
|
||||
Date: Wed Mar 21 09:55:01 2007 +0300
|
||||
|
||||
Update usage of 'nc' in README.NetConsole
|
||||
|
||||
Added information about usage of NetConsole on systems where the -l and -p
|
||||
switches are mutually exclusive.
|
||||
|
||||
Signed-off-by: Igor Marnat <marny@rambler.ru>
|
||||
Signed-off-by: Ben Warren <bwarren@qstreams.com>
|
||||
|
||||
commit 31c98a88228021b314c89ebb8104fb6473da4471
|
||||
Author: Wolfgang Denk <wd@denx.de>
|
||||
Date: Wed Apr 4 02:09:30 2007 +0200
|
||||
|
@ -37,6 +563,18 @@ Date: Wed Apr 4 01:49:15 2007 +0200
|
|||
|
||||
Minor cleanup.
|
||||
|
||||
commit a65c5768e5537530bd1780af3d3fddc3113a163c
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Mon Apr 2 10:09:30 2007 +0200
|
||||
|
||||
ppc4xx: Change SysACE address on Katmai
|
||||
|
||||
With this new base address of the Xilinx SystemACE controller
|
||||
the Linux driver will be easier to adapt, since it can now be
|
||||
mapped via the "normal" ioremap() call.
|
||||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit aea03c4e8c3a21ce43d3faf48a6e6d474c8bdf73
|
||||
Author: Gerald Van Baren <vanbaren@cideas.com>
|
||||
Date: Sat Mar 31 14:30:53 2007 -0400
|
||||
|
@ -604,6 +1142,24 @@ Date: Thu Mar 8 10:06:09 2007 +0100
|
|||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 83853178bd36bca6f0f8f1331476620c84a587fc
|
||||
Author: Ed Swarthout <Ed.Swarthout@freescale.com>
|
||||
Date: Wed Mar 7 12:14:50 2007 -0600
|
||||
|
||||
net - Support ping reply when processing net-loop
|
||||
|
||||
Add ICMP_ECHO_REQUEST packet support by responding with a ICMP_ECHO_REPLY.
|
||||
|
||||
This permits the ping command to test the phy interface when the phy
|
||||
is put in loopback mode (typically by setting register 0 bit 14).
|
||||
|
||||
It also allows the port to respond to an external ping when u-boot is
|
||||
processing some other net command (such as tftp). This is useful when
|
||||
tftp appears to hang.
|
||||
|
||||
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
|
||||
Signed-off-by: Ben Warren <bwarren@qstreams.com>
|
||||
|
||||
commit fa1aef15bcd47736687be1af544506e90fba545d
|
||||
Author: Stefan Roese <sr@denx.de>
|
||||
Date: Wed Mar 7 16:43:00 2007 +0100
|
||||
|
@ -680,6 +1236,12 @@ Date: Tue Mar 6 07:47:04 2007 +0100
|
|||
|
||||
Signed-off-by: Stefan Roese <sr@denx.de>
|
||||
|
||||
commit 647d3c3eed0da1d1505eecabe0b0fab96f956e68
|
||||
Author: Wolfgang Denk <wd@pollux.denx.de>
|
||||
Date: Sun Mar 4 01:36:05 2007 +0100
|
||||
|
||||
Some code cleanup.
|
||||
|
||||
commit 781e026c8aa6f7e9eb5f0e72cc4d20971219b148
|
||||
Author: Kim Phillips <kim.phillips@freescale.com>
|
||||
Date: Wed Feb 28 00:02:04 2007 -0600
|
||||
|
@ -1551,6 +2113,15 @@ Date: Tue Jan 23 13:25:22 2007 +0100
|
|||
[ColdFire MCF5271 family] Add CPU detection based on the value of Chip
|
||||
Identification Register (CIR).
|
||||
|
||||
commit fdef388758506765d4d6a7155c8f1584c63ff581
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Mon Jan 22 13:19:21 2007 +0800
|
||||
|
||||
use CFG_WRITE_SWAPPED_DATA define instead of define CFG_FLASH_CFI_SWAP
|
||||
The patch by Heiko Schocher <hs@pollux.denx.de> on Jan, 19, 2007
|
||||
fixes cfi_driver bug for mpc7448hpc2 board. The default cfi_driver can support
|
||||
mpc7448hpc2 board.
|
||||
|
||||
commit a4012396645533aef218354eeba754dff0deace8
|
||||
Author: Wolfgang Denk <wd@pollux.denx.de>
|
||||
Date: Fri Jan 19 23:08:39 2007 +0100
|
||||
|
@ -1966,6 +2537,72 @@ Date: Fri Dec 8 16:23:08 2006 +0100
|
|||
|
||||
automatic update mechanism
|
||||
|
||||
commit 9d27b3a0685ff99fc477983f315c04d49f657a8a
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Mon Dec 4 17:56:59 2006 +0800
|
||||
|
||||
Slight code clean up.
|
||||
Add comments, delete duplicate define and remove spaces.
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 4dbcd69e3e2776ea334590d5768e3692c5fae5c1
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Mon Dec 4 17:54:21 2006 +0800
|
||||
|
||||
Introduce PLL_CFG[0:4] table for processor 7448/7447A/7455/7457. The original
|
||||
multiplier table can not refect the real PLL clock behavior of these
|
||||
processors. Please refer to the hardware specification for detailed
|
||||
information of the corresponding processors.
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 4efe20c9579011d9987f62ed7d35ee8cdc1cf0e0
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Mon Dec 4 14:46:23 2006 +0800
|
||||
|
||||
Remove the static MAC address, ip address, server ip, netmask and
|
||||
gateway ip for network setting.
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 6f12c61cf31ed73d72ddfcfc712a854a3a177aaf
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Mon Dec 4 14:33:08 2006 +0800
|
||||
|
||||
Remove the duplicate memory test code for mpc744ihpc2 board.
|
||||
If a memory test is needed, please use the functions in
|
||||
post/memory.c or memtest command.
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit c9c1eeed7dd193fa65fb194654132040d49d4d3a
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Fri Dec 1 19:01:25 2006 +0800
|
||||
|
||||
Fix the exception occuring in RAM table search issue.
|
||||
The original search_one_table() function code can only processes the search
|
||||
for the exception occurring in FLASH/ROM, because the exception and fixup
|
||||
table usually locate in FLASH. If the exception address is also in
|
||||
FLASH, it will be OK.
|
||||
If the exception occurs in RAM, after the u-boot relocation, a
|
||||
relocation offset should be added.
|
||||
|
||||
clean up the code in cpu/74xx_7xx/cpu.c
|
||||
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit ee311214e0d216f904feea269599d0934bf71f23
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Fri Dec 1 11:47:36 2006 +0800
|
||||
|
||||
Clean up the code according to codestyle:
|
||||
(1) remove some C++ comments.
|
||||
(2) remove trailing white space.
|
||||
(3) remove trailing empty line.
|
||||
(4) Indentation by table.
|
||||
(5) remove {} in one line condition.
|
||||
(6) add space before '(' in function call.
|
||||
Remove some weird printf () output.
|
||||
Add necessary comments.
|
||||
Modified Makefile to support building in a separate directory.
|
||||
|
||||
commit dd520bf314c7add4183c5191692180f576f96b60
|
||||
Author: Wolfgang Denk <wd@pollux.denx.de>
|
||||
Date: Thu Nov 30 18:02:20 2006 +0100
|
||||
|
@ -2672,12 +3309,191 @@ Date: Thu Sep 7 07:39:46 2006 -0700
|
|||
|
||||
Signed-off-by: Nick Spence <nick.spence@freescale.com>
|
||||
|
||||
commit 4831c8b8a97799da77923d6bbb4c260c0d45521c
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Fri Nov 3 13:10:00 2006 +0800
|
||||
|
||||
Remove some unused CFG define.
|
||||
undef CFG_DRAM_TEST
|
||||
|
||||
commit 99c09c4dec34f77c243bf51bea532e3f339410ad
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Fri Nov 3 13:07:36 2006 +0800
|
||||
|
||||
Change the TEXT_BASE from 0xFFF00000 to 0xFF000000.
|
||||
Both work. 0xFF000000 seems more reasonable.
|
||||
|
||||
commit c59200443072353044aa4bf737a5a60f9a9af231
|
||||
Author: Wolfgang Denk <wd@pollux.denx.de>
|
||||
Date: Thu Nov 2 15:15:01 2006 +0100
|
||||
|
||||
Release U-Boot 1.1.6
|
||||
|
||||
commit c1fbe4103a0d6c8957f912af902d705ba67836f2
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Thu Nov 2 19:14:48 2006 +0800
|
||||
|
||||
This patch comes from Yuli's posted patch on 8/8/2006
|
||||
titled "CFI Driver Little-Endian write Issue".
|
||||
|
||||
http://sourceforge.net/mailarchive/message.php?msg_id=36311999
|
||||
|
||||
If that patch applied, please discard this one.
|
||||
Until now , I do not see his patch is applied. So please apply this one.
|
||||
|
||||
Signed-off-by: Yuli Barcohen <yuli@arabellasw.com>
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit b825f158e449e1e9cf74c08e572955e122394c96
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Thu Nov 2 19:12:31 2006 +0800
|
||||
|
||||
Tsi108 on chip i2c support.
|
||||
|
||||
The i2c Interface provides a master-only, serial interface that can be
|
||||
used for initializing Tsi108/Tsi109 registers from an EEPROM after a
|
||||
device reset.
|
||||
|
||||
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com>
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 9226e7d6f09b9a1ac074cd918c81225a4689bba8
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Thu Nov 2 19:11:06 2006 +0800
|
||||
|
||||
Tsi108 on chip pci controller support.
|
||||
|
||||
If there is no pci card, the tsi108/109 pci configure read will
|
||||
cause a machine check exception to the processor. PCI error should
|
||||
also be cleared after the read.
|
||||
|
||||
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com>
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit d1927cee977126e547ceeba23e4f978f377cfb8f
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Thu Nov 2 19:08:55 2006 +0800
|
||||
|
||||
Tundra tsi108 on chip Ethernet controller support.
|
||||
|
||||
The following is a brief description of the Ethernet controller:
|
||||
The Tsi108/9 Ethernet Controller connects Switch Fabric to two independent
|
||||
Gigabit Ethernet ports,E0 and E1. It uses a single Management interface
|
||||
to manage the two physical connection devices (PHYs). Each Ethernet port
|
||||
has its own statistics monitor that tracks and reports key interface
|
||||
statistics. Each port supports a 256-entry hash table for address
|
||||
filtering. In addition, each port is bridged to the Switch Fabric
|
||||
through a 2-Kbyte transmit FIFO and a 4-Kbyte Receive FIFO.
|
||||
|
||||
Each Ethernet port also has a pair of internal Ethernet DMA channels to
|
||||
support the transmit and receive data flows. The Ethernet DMA channels
|
||||
use descriptors set up in memory, the memory map of the device, and
|
||||
access via the Switch Fabric. The Ethernet Controller?s DMA arbiter
|
||||
handles arbitration for the Switch Fabric. The Controller also
|
||||
has a register businterface for register accesses and status monitor
|
||||
control.
|
||||
|
||||
The PMD (Physical Media Device) interface operates in MII, GMII, or TBI
|
||||
modes. The MII mode is used for connecting with 10 or 100 Mbit/s PMDs.
|
||||
The GMII and TBI modes are used to connect with Gigabit PMDs. Internal
|
||||
data flows to and from the Ethernet Controller through the Switch Fabric.
|
||||
|
||||
Each Ethernet port uses its transmit and receive DMA channels to manage
|
||||
data flows through buffer descriptors that are predefined by the
|
||||
system (the descriptors can exist anywhere in the system memory map).
|
||||
These descriptors are data structures that point to buffers filled
|
||||
with data ready to transmit over Ethernet, or they point to empty
|
||||
buffers ready to receive data from Ethernet.
|
||||
|
||||
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com>
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 78aa0c3427f3ecdeb34aabfbbe2dd23b6ad8f40e
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Thu Nov 2 19:01:33 2006 +0800
|
||||
|
||||
Tundra tsi108 header file.
|
||||
|
||||
The Tundra Semiconductor Corporation (Tundra) Tsi108 is a host bridge for
|
||||
PowerPC processors that offers numerous system interconnect options for
|
||||
embedded application designers. The Tsi108 can interconnect 60x or
|
||||
MPX processors to PCI/X peripherals, DDR2-400 memory, Gigabit Ethernet,
|
||||
and Flash. Provided the macro define for tsi108 chip.
|
||||
|
||||
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com>
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 87c4db09699c6b89176b31004afcb83eb1585d47
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Thu Nov 2 18:59:15 2006 +0800
|
||||
|
||||
Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support.
|
||||
mpc7448hpc2 board support high level code:tsi108 init + mpc7448hpc2.
|
||||
|
||||
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com>
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 27801b8ab11c61b577e45742a515bb3b23b80241
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Thu Nov 2 18:57:21 2006 +0800
|
||||
|
||||
Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support.
|
||||
Make ,config.mk and link file for the mpc7448hpc2 board.
|
||||
|
||||
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com>
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit c6411c0c3bbc79f9ba8aef58296a42d8f9d8a0a6
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Thu Nov 2 18:55:04 2006 +0800
|
||||
|
||||
Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support.
|
||||
The mpc7448hpc2 board support header file.
|
||||
|
||||
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com>
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 625bb5ddb50b243f931262ca8c46956409471917
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Thu Nov 2 18:52:21 2006 +0800
|
||||
|
||||
Add mpc7448hpc2 (mpc7448 + tsi108) board associated code support.
|
||||
The mpc7448hpc2 board support low level assemble language init code.
|
||||
|
||||
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com>
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 4c52783b3d024e153c4972b97332e314bc3bdc46
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Thu Nov 2 18:49:51 2006 +0800
|
||||
|
||||
General code modification for mpc7448hpc2 board support.
|
||||
1. Add 7447A and 7448 processor support.
|
||||
2. Add the following flags.
|
||||
|
||||
CFG_CONFIG_BUS_CLK : If the 74xx bus frequency can be configured dynamically
|
||||
(such as by switch on board), this flag should be set.
|
||||
|
||||
CFG_EXCEPTION_AFTER_RELOCATE: If an exception occurs after the u-boot
|
||||
relocates to RAM, this flag should be set.
|
||||
|
||||
CFG_SERIAL_HANG_IN_EXCEPTION: If the print out function will cause the
|
||||
system hang in exception, this flag should be set.
|
||||
|
||||
There is a design issue for tsi108/109 pci configure read. When pci scan
|
||||
the slots, if there is no pci card, the tsi108/9 will cause a machine
|
||||
check exception for mpc7448 processor.
|
||||
|
||||
Signed-off-by: Alexandre Bounine <alexandreb@tundra.com>
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 69366bf42f22d67efce8da3f8c40a43d4a3c2695
|
||||
Author: roy zang <tie-fei.zang@freescale.com>
|
||||
Date: Thu Nov 2 18:34:47 2006 +0800
|
||||
|
||||
Add README file for mpc7448hpc2 board.
|
||||
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
||||
|
||||
commit 25721b5cec2be4bce79cfade17ec8f6aa1e67526
|
||||
Author: Bartlomiej Sieka <tur@semihalf.com>
|
||||
Date: Wed Nov 1 02:04:38 2006 +0100
|
||||
|
|
21
MAINTAINERS
21
MAINTAINERS
|
@ -257,15 +257,6 @@ Frank Panno <fpanno@delphintech.com>
|
|||
|
||||
ep8260 MPC8260
|
||||
|
||||
Peter Pearse <peter.pearse@arm.com>
|
||||
integratorcp All current ARM supplied &
|
||||
supported core modules
|
||||
- see http://www.arm.com
|
||||
/products/DevTools
|
||||
/Hardware_Platforms.html
|
||||
versatile ARM926EJ-S
|
||||
versatile ARM926EJ-S
|
||||
|
||||
Denis Peter <d.peter@mpl.ch>
|
||||
|
||||
MIP405 PPC4xx
|
||||
|
@ -444,6 +435,9 @@ Gary Jennejohn <gj@denx.de>
|
|||
smdk2400 ARM920T
|
||||
trab ARM920T
|
||||
|
||||
Konstantin Kletschke <kletschke@synertronixx.de>
|
||||
scb9328 ARM920T
|
||||
|
||||
Nishant Kamat <nskamat@ti.com>
|
||||
|
||||
omap1610h2 ARM926EJS
|
||||
|
@ -461,6 +455,15 @@ Rolf Offermanns <rof@sysgo.de>
|
|||
|
||||
shannon SA1100
|
||||
|
||||
Peter Pearse <peter.pearse@arm.com>
|
||||
integratorcp All current ARM supplied &
|
||||
supported core modules
|
||||
-see http://www.arm.com
|
||||
/products/DevTools
|
||||
/Hardware_Platforms.html
|
||||
versatile ARM926EJ-S
|
||||
versatile ARM926EJ-S
|
||||
|
||||
Dave Peverley <dpeverley@mpc-data.co.uk>
|
||||
|
||||
omap730p2 ARM926EJS
|
||||
|
|
1
MAKEALL
1
MAKEALL
|
@ -155,6 +155,7 @@ LIST_85xx=" \
|
|||
LIST_74xx=" \
|
||||
DB64360 DB64460 EVB64260 P3G4 \
|
||||
p3m7448 PCIPPC2 PCIPPC6 ZUMA \
|
||||
mpc7448hpc2
|
||||
"
|
||||
|
||||
LIST_7xx=" \
|
||||
|
|
6
Makefile
6
Makefile
|
@ -149,7 +149,7 @@ ifeq ($(ARCH),blackfin)
|
|||
CROSS_COMPILE = bfin-uclinux-
|
||||
endif
|
||||
ifeq ($(ARCH),avr32)
|
||||
CROSS_COMPILE = avr32-
|
||||
CROSS_COMPILE = avr32-linux-
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
@ -219,6 +219,7 @@ LIBS += $(shell if [ -d post/cpu/$(CPU) ]; then echo \
|
|||
LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
|
||||
"post/board/$(BOARDDIR)/libpost$(BOARD).a"; fi)
|
||||
LIBS += common/libcommon.a
|
||||
LIBS += libfdt/libfdt.a
|
||||
LIBS += $(BOARDLIBS)
|
||||
|
||||
LIBS := $(addprefix $(obj),$(LIBS))
|
||||
|
@ -1819,6 +1820,9 @@ EVB64260_config \
|
|||
EVB64260_750CX_config: unconfig
|
||||
@$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260
|
||||
|
||||
mpc7448hpc2_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2
|
||||
|
||||
P3G4_config: unconfig
|
||||
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260
|
||||
|
||||
|
|
22
README
22
README
|
@ -2398,17 +2398,17 @@ configurations; the following names are supported:
|
|||
csb272_config lwmon_config sbc8260_config
|
||||
CU824_config MBX860T_config sbc8560_33_config
|
||||
DUET_ADS_config MBX_config sbc8560_66_config
|
||||
EBONY_config MPC8260ADS_config SM850_config
|
||||
ELPT860_config MPC8540ADS_config SPD823TS_config
|
||||
ESTEEM192E_config MPC8540EVAL_config stxgp3_config
|
||||
ETX094_config MPC8560ADS_config SXNI855T_config
|
||||
FADS823_config NETVIA_config TQM823L_config
|
||||
FADS850SAR_config omap1510inn_config TQM850L_config
|
||||
FADS860T_config omap1610h2_config TQM855L_config
|
||||
FPS850L_config omap1610inn_config TQM860L_config
|
||||
omap5912osk_config walnut_config
|
||||
omap2420h4_config Yukon8220_config
|
||||
ZPC1900_config
|
||||
EBONY_config mpc7448hpc2_config SM850_config
|
||||
ELPT860_config MPC8260ADS_config SPD823TS_config
|
||||
ESTEEM192E_config MPC8540ADS_config stxgp3_config
|
||||
ETX094_config MPC8540EVAL_config SXNI855T_config
|
||||
FADS823_config NMPC8560ADS_config TQM823L_config
|
||||
FADS850SAR_config NETVIA_config TQM850L_config
|
||||
FADS860T_config omap1510inn_config TQM855L_config
|
||||
FPS850L_config omap1610h2_config TQM860L_config
|
||||
omap1610inn_config walnut_config
|
||||
omap5912osk_config Yukon8220_config
|
||||
omap2420h4_config ZPC1900_config
|
||||
|
||||
Note: for some board special configuration names may exist; check if
|
||||
additional information is available from the board vendor; for
|
||||
|
|
|
@ -21,5 +21,5 @@
|
|||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -ffixed-r5 -mno-pic -mrelax
|
||||
PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax
|
||||
PLATFORM_LDFLAGS += --relax
|
||||
|
|
|
@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB := $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o flash.o
|
||||
COBJS := $(BOARD).o flash.o eth.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
|
|
@ -23,6 +23,8 @@
|
|||
|
||||
#include <asm/io.h>
|
||||
#include <asm/sdram.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/hmatrix2.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
@ -40,9 +42,27 @@ static const struct sdram_info sdram = {
|
|||
.txsr = 5,
|
||||
};
|
||||
|
||||
void board_init_memories(void)
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
gd->sdram_size = sdram_init(&sdram);
|
||||
/* Set the SDRAM_ENABLE bit in the HEBI SFR */
|
||||
hmatrix2_writel(SFR4, 1 << 1);
|
||||
|
||||
gpio_enable_ebi();
|
||||
gpio_enable_usart1();
|
||||
#if defined(CONFIG_MACB)
|
||||
gpio_enable_macb0();
|
||||
gpio_enable_macb1();
|
||||
#endif
|
||||
#if defined(CONFIG_MMC)
|
||||
gpio_enable_mmci();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
long int initdram(int board_type)
|
||||
{
|
||||
return sdram_init(&sdram);
|
||||
}
|
||||
|
||||
void board_init_info(void)
|
||||
|
|
|
@ -1,5 +1,7 @@
|
|||
/*
|
||||
* Copyright (C) 2006 Atmel Corporation
|
||||
* Copyright (C) 2005-2006 Atmel Corporation
|
||||
*
|
||||
* Ethernet initialization for the ATSTK1000 starterkit
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -21,18 +23,16 @@
|
|||
*/
|
||||
#include <common.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
|
||||
#include <asm/arch/hmatrix2.h>
|
||||
#include <asm/arch/memory-map.h>
|
||||
#include <asm/arch/platform.h>
|
||||
|
||||
void cpu_enable_sdram(void)
|
||||
extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
|
||||
|
||||
#if defined(CONFIG_MACB) && (CONFIG_COMMANDS & CFG_CMD_NET)
|
||||
void atstk1000_eth_initialize(bd_t *bi)
|
||||
{
|
||||
const struct device *hmatrix;
|
||||
int id = 0;
|
||||
|
||||
hmatrix = get_device(DEVICE_HMATRIX);
|
||||
|
||||
/* Set the SDRAM_ENABLE bit in the HEBI SFR */
|
||||
hmatrix2_writel(hmatrix, SFR4, 1 << 1);
|
||||
macb_eth_initialize(id++, (void *)MACB0_BASE, bi->bi_phy_id[0]);
|
||||
macb_eth_initialize(id++, (void *)MACB1_BASE, bi->bi_phy_id[1]);
|
||||
}
|
||||
#endif
|
|
@ -57,7 +57,7 @@ unsigned long flash_init(void)
|
|||
|
||||
gd->bd->bi_flashstart = CFG_FLASH_BASE;
|
||||
gd->bd->bi_flashsize = CFG_FLASH_SIZE;
|
||||
gd->bd->bi_flashoffset = __edata_lma - _text;
|
||||
gd->bd->bi_flashoffset = _edata - _text;
|
||||
|
||||
flash_info[0].size = CFG_FLASH_SIZE;
|
||||
flash_info[0].sector_count = 135;
|
||||
|
|
|
@ -40,35 +40,38 @@ SECTIONS
|
|||
}
|
||||
. = ALIGN(32);
|
||||
__flashprog_end = .;
|
||||
_etext = .;
|
||||
|
||||
. = ALIGN(8);
|
||||
.rodata : {
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
}
|
||||
_etext = .;
|
||||
|
||||
__data_lma = ALIGN(8);
|
||||
. = 0x24000000;
|
||||
. = ALIGN(8);
|
||||
_data = .;
|
||||
.data : AT(__data_lma) {
|
||||
.data : {
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
}
|
||||
|
||||
. = ALIGN(4);
|
||||
__u_boot_cmd_start = .;
|
||||
__u_boot_cmd_lma = __data_lma + (__u_boot_cmd_start - _data);
|
||||
.u_boot_cmd : AT(__u_boot_cmd_lma) {
|
||||
.u_boot_cmd : {
|
||||
KEEP(*(.u_boot_cmd))
|
||||
}
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
_got = .;
|
||||
.got : {
|
||||
*(.got)
|
||||
}
|
||||
_egot = .;
|
||||
|
||||
. = ALIGN(8);
|
||||
_edata = .;
|
||||
__edata_lma = __u_boot_cmd_lma + (_edata - __u_boot_cmd_start);
|
||||
|
||||
.bss : AT(__edata_lma) {
|
||||
.bss : {
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
}
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# U-boot - Makefile
|
||||
#
|
||||
# Copyright (c) 2007 Analog Device Inc.
|
||||
# Copyright (c) 2005-2007 Analog Device Inc.
|
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - ezkit533.c
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -21,8 +21,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - flash-defines.h
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -21,8 +21,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __FLASHDEFINES_H__
|
||||
|
@ -60,7 +60,7 @@ void reset_flash(void);
|
|||
int erase_flash(void);
|
||||
int erase_block_flash(int, unsigned long);
|
||||
void unlock_flash(long lOffset);
|
||||
int write_data(long lStart, long lCount, long lStride, int *pnData);
|
||||
int write_data(long lStart, long lCount, uchar *pnData);
|
||||
int FillData(long lStart, long lCount, long lStride, int *pnData);
|
||||
int read_data(long lStart, long lCount, long lStride, int *pnData);
|
||||
int read_flash(long nOffset, int *pnValue);
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - flash.c Flash driver for PSD4256GV
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
* This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
|
@ -22,8 +22,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <asm/io.h>
|
||||
|
@ -178,63 +178,66 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
|
|||
int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = write_data(addr, cnt, 1, (int *)src);
|
||||
int d;
|
||||
if (addr % 2) {
|
||||
read_flash(addr - 1 - CFG_FLASH_BASE, &d);
|
||||
d = (int)((d & 0x00FF) | (*src++ << 8));
|
||||
ret = write_data(addr - 1, 2, (uchar *) & d);
|
||||
if (ret == FLASH_FAIL)
|
||||
return ERR_NOT_ERASED;
|
||||
ret = write_data(addr + 1, cnt - 1, src);
|
||||
} else
|
||||
ret = write_data(addr, cnt, src);
|
||||
if (ret == FLASH_FAIL)
|
||||
return ERR_NOT_ERASED;
|
||||
return FLASH_SUCCESS;
|
||||
}
|
||||
|
||||
int write_data(long lStart, long lCount, long lStride, int *pnData)
|
||||
int write_data(long lStart, long lCount, uchar * pnData)
|
||||
{
|
||||
long i = 0;
|
||||
int j = 0;
|
||||
unsigned long ulOffset = lStart - CFG_FLASH_BASE;
|
||||
int d;
|
||||
int iShift = 0;
|
||||
int iNumWords = 2;
|
||||
int nLeftover = lCount % 4;
|
||||
int nSector = 0;
|
||||
int flag = 0;
|
||||
|
||||
for (i = 0; (i < lCount / 4) && (i < BUFFER_SIZE); i++) {
|
||||
for (iShift = 0, j = 0; (j < iNumWords);
|
||||
j++, ulOffset += (lStride * 2)) {
|
||||
if ((ulOffset >= INVALIDLOCNSTART)
|
||||
&& (ulOffset < INVALIDLOCNEND)) {
|
||||
printf
|
||||
("Invalid locations, Try writing to another location \n");
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
get_sector_number(ulOffset, &nSector);
|
||||
read_flash(ulOffset, &d);
|
||||
if (d != 0xffff) {
|
||||
printf
|
||||
("Flash not erased at offset 0x%x Please erase to reprogram \n",
|
||||
ulOffset);
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
unlock_flash(ulOffset);
|
||||
if (write_flash(ulOffset, (pnData[i] >> iShift)) < 0) {
|
||||
printf("Error programming the flash \n");
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
iShift += 16;
|
||||
}
|
||||
if (lCount % 2) {
|
||||
flag = 1;
|
||||
lCount = lCount - 1;
|
||||
}
|
||||
if (nLeftover > 0) {
|
||||
if ((ulOffset >= INVALIDLOCNSTART)
|
||||
&& (ulOffset < INVALIDLOCNEND))
|
||||
return FLASH_FAIL;
|
||||
|
||||
for (i = 0; i < lCount - 1; i += 2, ulOffset += 2) {
|
||||
get_sector_number(ulOffset, &nSector);
|
||||
read_flash(ulOffset, &d);
|
||||
if (d != 0xffff) {
|
||||
printf
|
||||
("Flash already programmed. Please erase to reprogram \n");
|
||||
printf("uloffset = 0x%x \t d = 0x%x\n", ulOffset, d);
|
||||
("Flash not erased at offset 0x%x Please erase to reprogram \n",
|
||||
ulOffset);
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
unlock_flash(ulOffset);
|
||||
if (write_flash(ulOffset, pnData[i]) < 0) {
|
||||
d = (int)(pnData[i] | pnData[i + 1] << 8);
|
||||
write_flash(ulOffset, d);
|
||||
if (poll_toggle_bit(ulOffset) < 0) {
|
||||
printf("Error programming the flash \n");
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
if ((i > 0) && (!(i % AFP_SectorSize2)))
|
||||
printf(".");
|
||||
}
|
||||
if (flag) {
|
||||
get_sector_number(ulOffset, &nSector);
|
||||
read_flash(ulOffset, &d);
|
||||
if (d != 0xffff) {
|
||||
printf
|
||||
("Flash not erased at offset 0x%x Please erase to reprogram \n",
|
||||
ulOffset);
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
unlock_flash(ulOffset);
|
||||
d = (int)(pnData[i] | (d & 0xFF00));
|
||||
write_flash(ulOffset, d);
|
||||
if (poll_toggle_bit(ulOffset) < 0) {
|
||||
printf("Error programming the flash \n");
|
||||
return FLASH_FAIL;
|
||||
}
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - psd4256.h
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -21,8 +21,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
#
|
||||
# U-boot - Makefile
|
||||
#
|
||||
# Copyright (c) 2007 Analog Device Inc.
|
||||
# Copyright (c) 2005-2007 Analog Device Inc.
|
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - stamp.c STAMP board specific routines
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -21,8 +21,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - stamp.h
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -21,8 +21,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __STAMP_H__
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - BF537.c
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -21,8 +21,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - flash-defines.h
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -21,8 +21,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef __FLASHDEFINES_H__
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - flash.c Flash driver for PSD4256GV
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
* This file is based on BF533EzFlash.c originally written by Analog Devices, Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
|
@ -22,8 +22,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <malloc.h>
|
||||
|
|
|
@ -2,7 +2,7 @@
|
|||
* U-boot - ezkit561.c
|
||||
*
|
||||
* Copyright (c) 2005 Bas Vermeulen <bas@buyways.nl>
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -22,8 +22,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -23,14 +23,25 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <watchdog.h>
|
||||
#include <command.h>
|
||||
#include <watchdog.h>
|
||||
#include <asm/cache.h>
|
||||
#include <mpc86xx.h>
|
||||
|
||||
#include "pixis.h"
|
||||
|
||||
|
||||
static ulong strfractoint(uchar *strptr);
|
||||
|
||||
|
||||
/*
|
||||
* Simple board reset.
|
||||
*/
|
||||
void pixis_reset(void)
|
||||
{
|
||||
out8(PIXIS_BASE + PIXIS_RST, 0);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Per table 27, page 58 of MPC8641HPCN spec.
|
||||
*/
|
||||
|
@ -235,7 +246,8 @@ void set_px_go_with_watchdog(void)
|
|||
}
|
||||
|
||||
|
||||
int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp,
|
||||
int flag, int argc, char *argv[])
|
||||
{
|
||||
u8 tmp;
|
||||
|
||||
|
@ -252,7 +264,7 @@ int disable_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
}
|
||||
|
||||
U_BOOT_CMD(
|
||||
diswd, 1, 0, disable_watchdog,
|
||||
diswd, 1, 0, pixis_disable_watchdog_cmd,
|
||||
"diswd - Disable watchdog timer \n",
|
||||
NULL);
|
||||
|
||||
|
@ -263,7 +275,7 @@ U_BOOT_CMD(
|
|||
* input: strptr i.e. argv[2]
|
||||
*/
|
||||
|
||||
ulong strfractoint(uchar *strptr)
|
||||
static ulong strfractoint(uchar *strptr)
|
||||
{
|
||||
int i, j, retval;
|
||||
int mulconst;
|
||||
|
@ -319,3 +331,142 @@ ulong strfractoint(uchar *strptr)
|
|||
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
ulong val;
|
||||
ulong corepll;
|
||||
|
||||
/*
|
||||
* No args is a simple reset request.
|
||||
*/
|
||||
if (argc <= 1) {
|
||||
pixis_reset();
|
||||
/* not reached */
|
||||
}
|
||||
|
||||
if (strcmp(argv[1], "cf") == 0) {
|
||||
|
||||
/*
|
||||
* Reset with frequency changed:
|
||||
* cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
|
||||
*/
|
||||
if (argc < 5) {
|
||||
puts(cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
|
||||
read_from_px_regs(0);
|
||||
|
||||
val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
|
||||
|
||||
corepll = strfractoint(argv[3]);
|
||||
val = val + set_px_corepll(corepll);
|
||||
val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
|
||||
if (val == 3) {
|
||||
puts("Setting registers VCFGEN0 and VCTL\n");
|
||||
read_from_px_regs(1);
|
||||
puts("Resetting board with values from ");
|
||||
puts("VSPEED0, VSPEED1, VCLKH, and VCLKL \n");
|
||||
set_px_go();
|
||||
} else {
|
||||
puts(cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
|
||||
while (1) ; /* Not reached */
|
||||
|
||||
} else if (strcmp(argv[1], "altbank") == 0) {
|
||||
|
||||
/*
|
||||
* Reset using alternate flash bank:
|
||||
*/
|
||||
if (argv[2] == 0) {
|
||||
/*
|
||||
* Reset from alternate bank without changing
|
||||
* frequency and without watchdog timer enabled.
|
||||
* altbank
|
||||
*/
|
||||
read_from_px_regs(0);
|
||||
read_from_px_regs_altbank(0);
|
||||
if (argc > 2) {
|
||||
puts(cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
|
||||
set_altbank();
|
||||
read_from_px_regs_altbank(1);
|
||||
puts("Resetting board to boot from the other bank.\n");
|
||||
set_px_go();
|
||||
|
||||
} else if (strcmp(argv[2], "cf") == 0) {
|
||||
/*
|
||||
* Reset with frequency changed
|
||||
* altbank cf <SYSCLK freq> <COREPLL ratio>
|
||||
* <MPXPLL ratio>
|
||||
*/
|
||||
read_from_px_regs(0);
|
||||
read_from_px_regs_altbank(0);
|
||||
val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
|
||||
corepll = strfractoint(argv[4]);
|
||||
val = val + set_px_corepll(corepll);
|
||||
val = val + set_px_mpxpll(simple_strtoul(argv[5],
|
||||
NULL, 10));
|
||||
if (val == 3) {
|
||||
puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
|
||||
set_altbank();
|
||||
read_from_px_regs(1);
|
||||
read_from_px_regs_altbank(1);
|
||||
puts("Enabling watchdog timer on the FPGA\n");
|
||||
puts("Resetting board with values from ");
|
||||
puts("VSPEED0, VSPEED1, VCLKH and VCLKL ");
|
||||
puts("to boot from the other bank.\n");
|
||||
set_px_go_with_watchdog();
|
||||
} else {
|
||||
puts(cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
|
||||
while (1) ; /* Not reached */
|
||||
|
||||
} else if (strcmp(argv[2], "wd") == 0) {
|
||||
/*
|
||||
* Reset from alternate bank without changing
|
||||
* frequencies but with watchdog timer enabled:
|
||||
* altbank wd
|
||||
*/
|
||||
read_from_px_regs(0);
|
||||
read_from_px_regs_altbank(0);
|
||||
puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
|
||||
set_altbank();
|
||||
read_from_px_regs_altbank(1);
|
||||
puts("Enabling watchdog timer on the FPGA\n");
|
||||
puts("Resetting board to boot from the other bank.\n");
|
||||
set_px_go_with_watchdog();
|
||||
while (1) ; /* Not reached */
|
||||
|
||||
} else {
|
||||
puts(cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
|
||||
} else {
|
||||
puts(cmdtp->usage);
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
U_BOOT_CMD(
|
||||
pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
|
||||
"pixis_reset - Reset the board using the FPGA sequencer\n",
|
||||
" pixis_reset\n"
|
||||
" pixis_reset [altbank]\n"
|
||||
" pixis_reset altbank wd\n"
|
||||
" pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
|
||||
" pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
|
||||
);
|
|
@ -20,6 +20,7 @@
|
|||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
extern void pixis_reset(void);
|
||||
extern int set_px_sysclk(ulong sysclk);
|
||||
extern int set_px_mpxpll(ulong mpxpll);
|
||||
extern int set_px_corepll(ulong corepll);
|
||||
|
@ -28,6 +29,3 @@ extern void read_from_px_regs_altbank(int set);
|
|||
extern void set_altbank(void);
|
||||
extern void set_px_go(void);
|
||||
extern void set_px_go_with_watchdog(void);
|
||||
extern int disable_watchdog(cmd_tbl_t *cmdtp,
|
||||
int flag, int argc, char *argv[]);
|
||||
extern ulong strfractoint(uchar *strptr);
|
|
@ -180,10 +180,6 @@ void lcd_enable (void)
|
|||
break;
|
||||
udelay (PSOC_WAIT_TIME);
|
||||
}
|
||||
if (!retries) {
|
||||
printf ("%s Warning: PSoC doesn't respond on "
|
||||
"RTS NEGATE\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -0,0 +1,52 @@
|
|||
#
|
||||
# (C) Copyright 2000
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o tsi108_init.o
|
||||
SOBJS := asm_init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS))
|
||||
SOBJS := $(addprefix $(obj),$(SOBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
|
||||
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
|
||||
|
||||
clean:
|
||||
rm -f $(SOBJS) $(OBJS)
|
||||
|
||||
.PHONY: distclean
|
||||
distclean: clean
|
||||
rm -f $(LIB) core *.bak .depend
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude ($obj).depend
|
||||
|
||||
#########################################################################
|
|
@ -0,0 +1,918 @@
|
|||
/*
|
||||
* (C) Copyright 2004-05; Tundra Semiconductor Corp.
|
||||
*
|
||||
* Added automatic detect of SDC settings
|
||||
* Copyright (c) 2005 Freescale Semiconductor, Inc.
|
||||
* Maintainer tie-fei.zang@freescale.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* FILENAME: asm_init.s
|
||||
*
|
||||
* Originator: Alex Bounine
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* Initialization code for the Tundra Tsi108 bridge chip
|
||||
*
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
|
||||
#include <ppc_asm.tmpl>
|
||||
#include <ppc_defs.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#include <tsi108.h>
|
||||
|
||||
/*
|
||||
* Build Configuration Options
|
||||
*/
|
||||
|
||||
/* #define DISABLE_PBM disables usage of PB Master */
|
||||
/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */
|
||||
/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */
|
||||
|
||||
/*
|
||||
* Hardcoded SDC settings
|
||||
*/
|
||||
|
||||
#ifdef SDC_HARDCODED_INIT
|
||||
|
||||
/* Micron MT9HTF6472AY-40EA1 : Unbuffered, 512MB, 400, CL3, Single Rank */
|
||||
|
||||
#define VAL_SD_REFRESH (0x61A)
|
||||
#define VAL_SD_TIMING (0x0308336b)
|
||||
#define VAL_SD_D0_CTRL (0x07100021) /* auto-precharge disabled */
|
||||
#define VAL_SD_D0_BAR (0x0FE00000) /* 512MB @ 0x00000000 */
|
||||
#define VAL_SD_D1_CTRL (0x07100021) /* auto-precharge disabled */
|
||||
#define VAL_SD_D1_BAR (0x0FE00200) /* 512MB @ 0x20000000 */
|
||||
|
||||
#endif /* SDC_HARDCODED_INIT */
|
||||
|
||||
/*
|
||||
CPU Configuration:
|
||||
|
||||
CPU Address and Data Parity enables.
|
||||
|
||||
#define CPU_AP
|
||||
#define CPU_DP
|
||||
*/
|
||||
|
||||
/*
|
||||
* Macros
|
||||
* !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
|
||||
* expected to work correctly for the CSR space within 32KB range.
|
||||
*
|
||||
* LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
|
||||
* These macros are absolutely identical except their names. This difference
|
||||
* is provided intentionally for better readable code.
|
||||
*/
|
||||
|
||||
#define LOAD_PTR(reg,const32) \
|
||||
addis reg,r0,const32@h; ori reg,reg,const32@l
|
||||
|
||||
#define LOAD_U32(reg,const32) \
|
||||
addis reg,r0,const32@h; ori reg,reg,const32@l
|
||||
|
||||
/* LOADMEM initializes a register with the contents of a specified 32-bit
|
||||
* memory location, usually a CSR value.
|
||||
*/
|
||||
|
||||
#define LOAD_MEM(reg,addr32) \
|
||||
addis reg,r0,addr32@ha; lwz reg,addr32@l(reg)
|
||||
|
||||
#ifndef SDC_HARDCODED_INIT
|
||||
sdc_clk_sync:
|
||||
/* MHz: 0,0,183,100,133,167,200,233 */
|
||||
.long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* board_asm_init() - early initialization function. Coded to be portable to
|
||||
* dual-CPU configuration.
|
||||
* Checks CPU number and performs board HW initialization if called for CPU0.
|
||||
* Registers used: r3,r4,r5,r6,r19,r29
|
||||
*
|
||||
* NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
|
||||
* and the rest of the board. Current implementation demonstrates two
|
||||
* possible ways to identify CPU number:
|
||||
* - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
|
||||
* - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
|
||||
*/
|
||||
|
||||
.globl board_asm_init
|
||||
board_asm_init:
|
||||
mflr r19 /* Save LR to be able return later. */
|
||||
bl icache_enable /* Enable icache to reduce reads from flash. */
|
||||
|
||||
/* Initialize pointer to Tsi108 register space */
|
||||
|
||||
LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
|
||||
ori r4,r29,TSI108_PB_REG_OFFSET
|
||||
|
||||
/* Check Processor Version Number */
|
||||
|
||||
mfspr r3, PVR
|
||||
rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */
|
||||
|
||||
cmpli 0,0,r3,0x8000 /* MPC74xx */
|
||||
bne cont_brd_init
|
||||
|
||||
/*
|
||||
* For MPC744x/5x enable extended BATs[4-7]
|
||||
* Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
|
||||
* to disable prefetch
|
||||
*/
|
||||
|
||||
mfspr r5, HID0
|
||||
oris r5, r5, 0x0080 /* Set HID0[HIGH_BAT_EN] bit #8 */
|
||||
ori r5, r5, 0x0380 /* Set SPD,XBSEN,SGE bits #22,23,24 */
|
||||
mtspr HID0, r5
|
||||
isync
|
||||
sync
|
||||
|
||||
/* Adding code to disable external interventions in MPX bus mode */
|
||||
mfspr r3, 1014
|
||||
oris r3, r3, 0x0100 /* Set the EIDIS bit in MSSCR0: bit 7 */
|
||||
mtspr 1014, r3
|
||||
isync
|
||||
sync
|
||||
|
||||
/* Sri: code to enable FP unit */
|
||||
mfmsr r3
|
||||
ori r3, r3, 0x2000
|
||||
mtmsr r3
|
||||
isync
|
||||
sync
|
||||
|
||||
/* def CONFIG_DUAL_CPU
|
||||
* For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
|
||||
*/
|
||||
#if(1)
|
||||
mfspr r3,1014 /* read MSSCR0 */
|
||||
rlwinm. r3,r3,27,31,31 /* get processor ID number */
|
||||
mtspr SPRN_PIR,r3 /* Save CPU ID */
|
||||
sync
|
||||
bne init_done
|
||||
b do_tsi108_init
|
||||
|
||||
cont_brd_init:
|
||||
|
||||
/* An alternative method of checking the processor number (in addition
|
||||
* to configuration using MSSCR0[ID] bit on MPC74xx).
|
||||
* Good for IBM PPC750FX/GX.
|
||||
*/
|
||||
|
||||
lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */
|
||||
rlwinm. r3,r3,24,31,31 /* get processor ID number */
|
||||
bne init_done
|
||||
#else
|
||||
|
||||
cont_brd_init:
|
||||
|
||||
#endif /* CONFIG_DUAL_CPU */
|
||||
|
||||
/* Initialize Tsi108 chip */
|
||||
|
||||
do_tsi108_init:
|
||||
|
||||
/*
|
||||
* Adjust HLP/Flash parameters. By default after reset the HLP port is
|
||||
* set to support slow devices. Better performance can be achived when
|
||||
* an optimal parameters are used for specific EPROM device.
|
||||
* NOTE: This should be performed ASAP for the emulation platform
|
||||
* because it has 5MHz HLP clocking.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_TSI108EMU
|
||||
ori r4,r29,TSI108_HLP_REG_OFFSET
|
||||
LOAD_U32(r5,0x434422c0)
|
||||
stw r5,0x08(r4) /* set HLP B0_CTRL0 */
|
||||
sync
|
||||
LOAD_U32(r5,0xd0012000)
|
||||
stw r5,0x0c(r4) /* set HLP B0_CTRL1 */
|
||||
sync
|
||||
#endif
|
||||
|
||||
/* Initialize PB interface. */
|
||||
|
||||
ori r4,r29,TSI108_PB_REG_OFFSET
|
||||
|
||||
#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE)
|
||||
/* Relocate (if required) Tsi108 registers. Set new value for
|
||||
* PB_REG_BAR:
|
||||
* Note we are in the 32-bit address mode.
|
||||
*/
|
||||
LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
|
||||
stw r5,PB_REG_BAR(r4)
|
||||
andis. r29,r5,0xFFFF
|
||||
sync
|
||||
ori r4,r29,TSI108_PB_REG_OFFSET
|
||||
#endif
|
||||
|
||||
/* Set PB Slave configuration register */
|
||||
|
||||
LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */
|
||||
lwz r3, PB_RSR(r4) /* get PB bus mode */
|
||||
xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */
|
||||
rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */
|
||||
stw r5,PB_SCR(r4)
|
||||
sync
|
||||
|
||||
/* Configure PB Arbiter */
|
||||
|
||||
lwz r5,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
|
||||
li r3, 0x00F0 /* ARB_PIPELINE_DEP mask */
|
||||
#ifdef DISABLE_PBM
|
||||
ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */
|
||||
#endif
|
||||
andc r5,r5,r3 /* Clear the masked bit fields */
|
||||
ori r5,r5,0x0001 /* Set pipeline depth */
|
||||
stw r5,PB_ARB_CTRL(r4)
|
||||
|
||||
#if (0) /* currently using the default settings for PBM after reset */
|
||||
LOAD_U32(r5,0x) /* value for PB_MCR */
|
||||
stw r5,PB_MCR(r4)
|
||||
sync
|
||||
|
||||
LOAD_U32(r5,0x) /* value for PB_MCMD */
|
||||
stw r5,PB_MCMD(r4)
|
||||
sync
|
||||
#endif
|
||||
|
||||
/* Disable or enable PVT based on processor bus frequency
|
||||
* 1. Read CG_PWRUP_STATUS register field bits 18,17,16
|
||||
* 2. See if the value is < or > 133mhz (18:16 = 100)
|
||||
* 3. If > enable PVT
|
||||
*/
|
||||
|
||||
LOAD_U32(r3,0xC0002234)
|
||||
lwz r3,0(r3)
|
||||
rlwinm r3,r3,16,29,31
|
||||
|
||||
cmpi 0,0,r3,0x0004
|
||||
bgt sdc_init
|
||||
|
||||
#ifndef CONFIG_TSI108EMU
|
||||
/* FIXME: Disable PB calibration control for any real Tsi108 board */
|
||||
li r5,0x0101 /* disable calibration control */
|
||||
stw r5,PB_PVT_CTRL2(r4)
|
||||
sync
|
||||
#endif
|
||||
|
||||
/* Initialize SDRAM controller. */
|
||||
|
||||
sdc_init:
|
||||
|
||||
#ifndef SDC_HARDCODED_INIT
|
||||
/* get SDC clock prior doing sdram controller autoconfig */
|
||||
ori r4,r29,TSI108_CLK_REG_OFFSET /* r4 - ptr to CG registers */
|
||||
lwz r3, CG_PWRUP_STATUS(r4) /* get CG configuration */
|
||||
rlwinm r3,r3,12,29,31 /* r3 - SD clk */
|
||||
lis r5,sdc_clk_sync@h
|
||||
ori r5,r5,sdc_clk_sync@l
|
||||
/* Sri: At this point check if r3 = 001. If yes,
|
||||
* the memory frequency should be same as the
|
||||
* MPX bus frequency
|
||||
*/
|
||||
cmpi 0,0,r3,0x0001
|
||||
bne get_nsec
|
||||
lwz r6, CG_PWRUP_STATUS(r4)
|
||||
rlwinm r6,r6,16,29,31
|
||||
mr r3,r6
|
||||
|
||||
get_nsec:
|
||||
rlwinm r3,r3,2,0,31
|
||||
lwzx r9,r5,r3 /* get SD clk rate in nSec */
|
||||
/* ATTN: r9 will be used by SPD routine */
|
||||
#endif /* !SDC_HARDCODED_INIT */
|
||||
|
||||
ori r4,r29,TSI108_SD_REG_OFFSET /* r4 - ptr to SDRAM registers */
|
||||
|
||||
/* Initialize SDRAM controller. SDRAM Size = 512MB, One DIMM. */
|
||||
|
||||
LOAD_U32(r5,0x00)
|
||||
stw r5,SD_INT_ENABLE(r4) /* Ensure that interrupts are disabled */
|
||||
#ifdef ENABLE_SDRAM_ECC
|
||||
li r5, 0x01
|
||||
#endif /* ENABLE_SDRAM_ECC */
|
||||
stw r5,SD_ECC_CTRL(r4) /* Enable/Disable ECC */
|
||||
sync
|
||||
|
||||
#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */
|
||||
|
||||
/* First read the CG_PWRUP_STATUS register to get the
|
||||
* memory speed from bits 22,21,20
|
||||
*/
|
||||
|
||||
LOAD_U32(r3,0xC0002234)
|
||||
lwz r3,0(r3)
|
||||
rlwinm r3,r3,12,29,31
|
||||
|
||||
/* Now first check for 166, then 200, or default */
|
||||
|
||||
cmpi 0,0,r3,0x0005
|
||||
bne check_for_200mhz
|
||||
|
||||
/* set values for 166 Mhz memory speed
|
||||
* Set refresh rate and timing parameters
|
||||
*/
|
||||
LOAD_U32(r5,0x00000515)
|
||||
stw r5,SD_REFRESH(r4)
|
||||
LOAD_U32(r5,0x03073368)
|
||||
stw r5,SD_TIMING(r4)
|
||||
sync
|
||||
|
||||
/* Initialize DIMM0 control and BAR registers */
|
||||
LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
|
||||
#ifdef SDC_AUTOPRECH_EN
|
||||
oris r5,r5,0x0001 /* set auto precharge EN bit */
|
||||
#endif
|
||||
stw r5,SD_D0_CTRL(r4)
|
||||
LOAD_U32(r5,VAL_SD_D0_BAR)
|
||||
stw r5,SD_D0_BAR(r4)
|
||||
sync
|
||||
|
||||
/* Initialize DIMM1 control and BAR registers
|
||||
* (same as dimm 0, next 512MB, disabled)
|
||||
*/
|
||||
LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
|
||||
#ifdef SDC_AUTOPRECH_EN
|
||||
oris r5,r5,0x0001 /* set auto precharge EN bit */
|
||||
#endif
|
||||
stw r5,SD_D1_CTRL(r4)
|
||||
LOAD_U32(r5,VAL_SD_D1_BAR)
|
||||
stw r5,SD_D1_BAR(r4)
|
||||
sync
|
||||
|
||||
b sdc_init_done
|
||||
|
||||
check_for_200mhz:
|
||||
|
||||
cmpi 0,0,r3,0x0006
|
||||
bne set_default_values
|
||||
|
||||
/* set values for 200Mhz memory speed
|
||||
* Set refresh rate and timing parameters
|
||||
*/
|
||||
LOAD_U32(r5,0x0000061a)
|
||||
stw r5,SD_REFRESH(r4)
|
||||
LOAD_U32(r5,0x03083348)
|
||||
stw r5,SD_TIMING(r4)
|
||||
sync
|
||||
|
||||
/* Initialize DIMM0 control and BAR registers */
|
||||
LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
|
||||
#ifdef SDC_AUTOPRECH_EN
|
||||
oris r5,r5,0x0001 /* set auto precharge EN bit */
|
||||
#endif
|
||||
stw r5,SD_D0_CTRL(r4)
|
||||
LOAD_U32(r5,VAL_SD_D0_BAR)
|
||||
stw r5,SD_D0_BAR(r4)
|
||||
sync
|
||||
|
||||
/* Initialize DIMM1 control and BAR registers
|
||||
* (same as dimm 0, next 512MB, disabled)
|
||||
*/
|
||||
LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
|
||||
#ifdef SDC_AUTOPRECH_EN
|
||||
oris r5,r5,0x0001 /* set auto precharge EN bit */
|
||||
#endif
|
||||
stw r5,SD_D1_CTRL(r4)
|
||||
LOAD_U32(r5,VAL_SD_D1_BAR)
|
||||
stw r5,SD_D1_BAR(r4)
|
||||
sync
|
||||
|
||||
b sdc_init_done
|
||||
|
||||
set_default_values:
|
||||
|
||||
/* Set refresh rate and timing parameters */
|
||||
LOAD_U32(r5,VAL_SD_REFRESH)
|
||||
stw r5,SD_REFRESH(r4)
|
||||
LOAD_U32(r5,VAL_SD_TIMING)
|
||||
stw r5,SD_TIMING(r4)
|
||||
sync
|
||||
|
||||
/* Initialize DIMM0 control and BAR registers */
|
||||
LOAD_U32(r5,VAL_SD_D0_CTRL) /* auto-precharge disabled */
|
||||
#ifdef SDC_AUTOPRECH_EN
|
||||
oris r5,r5,0x0001 /* set auto precharge EN bit */
|
||||
#endif
|
||||
stw r5,SD_D0_CTRL(r4)
|
||||
LOAD_U32(r5,VAL_SD_D0_BAR)
|
||||
stw r5,SD_D0_BAR(r4)
|
||||
sync
|
||||
|
||||
/* Initialize DIMM1 control and BAR registers
|
||||
* (same as dimm 0, next 512MB, disabled)
|
||||
*/
|
||||
LOAD_U32(r5,VAL_SD_D1_CTRL) /* auto-precharge disabled */
|
||||
#ifdef SDC_AUTOPRECH_EN
|
||||
oris r5,r5,0x0001 /* set auto precharge EN bit */
|
||||
#endif
|
||||
stw r5,SD_D1_CTRL(r4)
|
||||
LOAD_U32(r5,VAL_SD_D1_BAR)
|
||||
stw r5,SD_D1_BAR(r4)
|
||||
sync
|
||||
#else /* !SDC_HARDCODED_INIT */
|
||||
bl tsi108_sdram_spd /* automatically detect SDC settings */
|
||||
#endif /* SDC_HARDCODED_INIT */
|
||||
|
||||
sdc_init_done:
|
||||
|
||||
#ifdef DISABLE_PBM
|
||||
LOAD_U32(r5,0x00000030) /* PB_EN + OCN_EN */
|
||||
#else
|
||||
LOAD_U32(r5,0x00000230) /* PB_EN + OCN_EN + PB/OCN=80/20 */
|
||||
#endif /* DISABLE_PBM */
|
||||
|
||||
#ifdef CONFIG_TSI108EMU
|
||||
oris r5,r5,0x0010 /* set EMULATION_MODE bit */
|
||||
#endif
|
||||
|
||||
stw r5,SD_CTRL(r4)
|
||||
eieio
|
||||
sync
|
||||
|
||||
/* Enable SDRAM access */
|
||||
|
||||
oris r5,r5,0x8000 /* start SDC: set SD_CTRL[ENABLE] bit */
|
||||
stw r5,SD_CTRL(r4)
|
||||
sync
|
||||
|
||||
wait_init_complete:
|
||||
lwz r5,SD_STATUS(r4)
|
||||
andi. r5,r5,0x0001
|
||||
/* wait until SDRAM initialization is complete */
|
||||
beq wait_init_complete
|
||||
|
||||
/* Map SDRAM into the processor bus address space */
|
||||
|
||||
ori r4,r29,TSI108_PB_REG_OFFSET
|
||||
|
||||
/* Setup BARs associated with direct path PB<->SDRAM */
|
||||
|
||||
/* PB_SDRAM_BAR1:
|
||||
* provides a direct path to the main system memory (cacheable SDRAM)
|
||||
*/
|
||||
|
||||
/* BA=0,Size=512MB, ENable, No Addr.Translation */
|
||||
LOAD_U32(r5, 0x00000011)
|
||||
stw r5,PB_SDRAM_BAR1(r4)
|
||||
sync
|
||||
|
||||
/* Make sure that PB_SDRAM_BAR1 decoder is set
|
||||
* (to allow following immediate read from SDRAM)
|
||||
*/
|
||||
lwz r5,PB_SDRAM_BAR1(r4)
|
||||
sync
|
||||
|
||||
/* PB_SDRAM_BAR2:
|
||||
* provides non-cacheable alias (via the direct path) to main
|
||||
* system memory.
|
||||
* Size = 512MB, ENable, Addr.Translation - ON,
|
||||
* BA = 0x0_40000000, TA = 0x0_00000000
|
||||
*/
|
||||
|
||||
LOAD_U32(r5, 0x40010011)
|
||||
stw r5,PB_SDRAM_BAR2(r4)
|
||||
sync
|
||||
|
||||
/* Make sure that PB_SDRAM_BAR2 decoder is set
|
||||
* (to allow following immediate read from SDRAM)
|
||||
*/
|
||||
lwz r5,PB_SDRAM_BAR2(r4)
|
||||
sync
|
||||
|
||||
init_done:
|
||||
|
||||
/* All done. Restore LR and return. */
|
||||
mtlr r19
|
||||
blr
|
||||
|
||||
#if (0)
|
||||
/*
|
||||
* init_cpu1
|
||||
* This routine enables CPU1 on the dual-processor system.
|
||||
* Now there is only one processor in the system
|
||||
*/
|
||||
|
||||
.global enable_cpu1
|
||||
enable_cpu1:
|
||||
|
||||
lis r3,Tsi108_Base@ha /* Get Grendel CSR Base Addr */
|
||||
addi r3,r3,Tsi108_Base@l
|
||||
lwz r3,0(r3) /* R3 = CSR Base Addr */
|
||||
ori r4,r3,TSI108_PB_REG_OFFSET
|
||||
lwz r3,PB_ARB_CTRL(r4) /* Read PB Arbiter Control Register */
|
||||
ori r3,r3,0x0200 /* Set M1_EN bit */
|
||||
stw r3,PB_ARB_CTRL(r4)
|
||||
|
||||
blr
|
||||
#endif
|
||||
|
||||
/*
|
||||
* enable_EI
|
||||
* Enable CPU core external interrupt
|
||||
*/
|
||||
|
||||
.global enable_EI
|
||||
enable_EI:
|
||||
mfmsr r3
|
||||
ori r3,r3,0x8000 /* set EE bit */
|
||||
mtmsr r3
|
||||
blr
|
||||
|
||||
/*
|
||||
* disable_EI
|
||||
* Disable CPU core external interrupt
|
||||
*/
|
||||
|
||||
.global disable_EI
|
||||
disable_EI:
|
||||
mfmsr r3
|
||||
li r4,-32768 /* aka "li r4,0x8000" */
|
||||
andc r3,r3,r4 /* clear EE bit */
|
||||
mtmsr r3
|
||||
blr
|
||||
|
||||
#ifdef ENABLE_SDRAM_ECC
|
||||
/* enables SDRAM ECC */
|
||||
|
||||
.global enable_ECC
|
||||
enable_ECC:
|
||||
ori r4,r29,TSI108_SD_REG_OFFSET
|
||||
lwz r3,SD_ECC_CTRL(r4) /* Read SDRAM ECC Control Register */
|
||||
ori r3,r3,0x0001 /* Set ECC_EN bit */
|
||||
stw r3,SD_ECC_CTRL(r4)
|
||||
blr
|
||||
|
||||
/*
|
||||
* clear_ECC_err
|
||||
* Clears all pending SDRAM ECC errors
|
||||
* (normally after SDRAM scrubbing/initialization)
|
||||
*/
|
||||
|
||||
.global clear_ECC_err
|
||||
clear_ECC_err:
|
||||
ori r4,r29,TSI108_SD_REG_OFFSET
|
||||
ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */
|
||||
stw r3,SD_INT_STATUS(r4)
|
||||
blr
|
||||
|
||||
#endif /* ENABLE_SDRAM_ECC */
|
||||
|
||||
#ifndef SDC_HARDCODED_INIT
|
||||
|
||||
/* SDRAM SPD Support */
|
||||
#define SD_I2C_CTRL1 (0x400)
|
||||
#define SD_I2C_CTRL2 (0x404)
|
||||
#define SD_I2C_RD_DATA (0x408)
|
||||
#define SD_I2C_WR_DATA (0x40C)
|
||||
|
||||
/*
|
||||
* SDRAM SPD Support Macros
|
||||
*/
|
||||
|
||||
#define SPD_DIMM0 (0x00000100)
|
||||
#define SPD_DIMM1 (0x00000200) /* SPD_DIMM1 was 0x00000000 */
|
||||
|
||||
#define SPD_RDIMM (0x01)
|
||||
#define SPD_UDIMM (0x02)
|
||||
|
||||
#define SPD_CAS_3 0x8
|
||||
#define SPD_CAS_4 0x10
|
||||
#define SPD_CAS_5 0x20
|
||||
|
||||
#define ERR_NO_DIMM_FOUND (0xdb0)
|
||||
#define ERR_TRAS_FAIL (0xdb1)
|
||||
#define ERR_TRCD_FAIL (0xdb2)
|
||||
#define ERR_TRP_FAIL (0xdb3)
|
||||
#define ERR_TWR_FAIL (0xdb4)
|
||||
#define ERR_UNKNOWN_PART (0xdb5)
|
||||
#define ERR_NRANK_INVALID (0xdb6)
|
||||
#define ERR_DIMM_SIZE (0xdb7)
|
||||
#define ERR_ADDR_MODE (0xdb8)
|
||||
#define ERR_RFRSH_RATE (0xdb9)
|
||||
#define ERR_DIMM_TYPE (0xdba)
|
||||
#define ERR_CL_VALUE (0xdbb)
|
||||
#define ERR_TRFC_FAIL (0xdbc)
|
||||
|
||||
/* READ_SPD requirements:
|
||||
* byte - byte address in SPD device (0 - 255)
|
||||
* r3 = will return data read from I2C Byte location
|
||||
* r4 - unchanged (SDC base addr)
|
||||
* r5 - clobbered in routine (I2C status)
|
||||
* r10 - number of DDR slot where first SPD device is detected
|
||||
*/
|
||||
|
||||
#define READ_SPD(byte_num) \
|
||||
addis r3, 0, byte_num@l; \
|
||||
or r3, r3, r10; \
|
||||
ori r3, r3, 0x0A; \
|
||||
stw r3, SD_I2C_CTRL1(r4); \
|
||||
li r3, I2C_CNTRL2_START; \
|
||||
stw r3, SD_I2C_CTRL2(r4); \
|
||||
eieio; \
|
||||
sync; \
|
||||
li r3, 0x100; \
|
||||
1:; \
|
||||
addic. r3, r3, -1; \
|
||||
bne 1b; \
|
||||
2:; \
|
||||
lwz r5, SD_I2C_CTRL2(r4); \
|
||||
rlwinm. r3,r5,0,23,23; \
|
||||
bne 2b; \
|
||||
rlwinm. r3,r5,0,3,3; \
|
||||
lwz r3,SD_I2C_RD_DATA(r4)
|
||||
|
||||
#define SPD_MIN_RFRSH (0x80)
|
||||
#define SPD_MAX_RFRSH (0x85)
|
||||
|
||||
refresh_rates: /* in nSec */
|
||||
.long 15625 /* Normal (0x80) */
|
||||
.long 3900 /* Reduced 0.25x (0x81) */
|
||||
.long 7800 /* Reduced 0.5x (0x82) */
|
||||
.long 31300 /* Extended 2x (0x83) */
|
||||
.long 62500 /* Extended 4x (0x84) */
|
||||
.long 125000 /* Extended 8x (0x85) */
|
||||
|
||||
/*
|
||||
* tsi108_sdram_spd
|
||||
*
|
||||
* Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data
|
||||
* Uses registers: r4 - SDC base address (not changed)
|
||||
* r9 - SDC clocking period in nSec
|
||||
* Changes registers: r3,r5,r6,r7,r8,r10,r11
|
||||
*/
|
||||
|
||||
tsi108_sdram_spd:
|
||||
|
||||
li r10,SPD_DIMM0
|
||||
xor r11,r11,r11 /* DIMM Base Address: starts from 0 */
|
||||
|
||||
do_first_dimm:
|
||||
|
||||
/* Program Refresh Rate Register */
|
||||
|
||||
READ_SPD(12) /* get Refresh Rate */
|
||||
beq check_next_slot
|
||||
li r5, ERR_RFRSH_RATE
|
||||
cmpi 0,0,r3,SPD_MIN_RFRSH
|
||||
ble spd_fail
|
||||
cmpi 0,0,r3,SPD_MAX_RFRSH
|
||||
bgt spd_fail
|
||||
addi r3,r3,-SPD_MIN_RFRSH
|
||||
rlwinm r3,r3,2,0,31
|
||||
lis r5,refresh_rates@h
|
||||
ori r5,r5,refresh_rates@l
|
||||
lwzx r5,r5,r3 /* get refresh rate in nSec */
|
||||
divwu r5,r5,r9 /* calculate # of SDC clocks */
|
||||
stw r5,SD_REFRESH(r4) /* Set refresh rate */
|
||||
sync
|
||||
|
||||
/* Program SD Timing Register */
|
||||
|
||||
li r7, 0 /* clear r7 prior parameter collection */
|
||||
|
||||
READ_SPD(20) /* get DIMM type: Registered or Unbuffered */
|
||||
beq spd_read_fail
|
||||
li r5, ERR_DIMM_TYPE
|
||||
cmpi 0,0,r3,SPD_UDIMM
|
||||
beq do_cl
|
||||
cmpi 0,0,r3,SPD_RDIMM
|
||||
bne spd_fail
|
||||
oris r7,r7,0x1000 /* set SD_TIMING[DIMM_TYPE] bit */
|
||||
|
||||
do_cl:
|
||||
READ_SPD(18) /* Get CAS Latency */
|
||||
beq spd_read_fail
|
||||
li r5,ERR_CL_VALUE
|
||||
andi. r6,r3,SPD_CAS_3
|
||||
beq cl_4
|
||||
li r6,3
|
||||
b set_cl
|
||||
cl_4:
|
||||
andi. r6,r3,SPD_CAS_4
|
||||
beq cl_5
|
||||
li r6,4
|
||||
b set_cl
|
||||
cl_5:
|
||||
andi. r6,r3,SPD_CAS_5
|
||||
beq spd_fail
|
||||
li r6,5
|
||||
set_cl:
|
||||
rlwimi r7,r6,24,5,7
|
||||
|
||||
READ_SPD(30) /* Get tRAS */
|
||||
beq spd_read_fail
|
||||
divwu r6,r3,r9
|
||||
mullw r8,r6,r9
|
||||
subf. r8,r8,r3
|
||||
beq set_tras
|
||||
addi r6,r6,1
|
||||
set_tras:
|
||||
li r5,ERR_TRAS_FAIL
|
||||
cmpi 0,0,r6,0x0F /* max supported value */
|
||||
bgt spd_fail
|
||||
rlwimi r7,r6,16,12,15
|
||||
|
||||
READ_SPD(29) /* Get tRCD */
|
||||
beq spd_read_fail
|
||||
/* right shift tRCD by 2 bits as per DDR2 spec */
|
||||
rlwinm r3,r3,30,2,31
|
||||
divwu r6,r3,r9
|
||||
mullw r8,r6,r9
|
||||
subf. r8,r8,r3
|
||||
beq set_trcd
|
||||
addi r6,r6,1
|
||||
set_trcd:
|
||||
li r5,ERR_TRCD_FAIL
|
||||
cmpi 0,0,r6,0x07 /* max supported value */
|
||||
bgt spd_fail
|
||||
rlwimi r7,r6,12,17,19
|
||||
|
||||
READ_SPD(27) /* Get tRP value */
|
||||
beq spd_read_fail
|
||||
rlwinm r3,r3,30,2,31 /* right shift tRP by 2 bits as per DDR2 spec */
|
||||
divwu r6,r3,r9
|
||||
mullw r8,r6,r9
|
||||
subf. r8,r8,r3
|
||||
beq set_trp
|
||||
addi r6,r6,1
|
||||
set_trp:
|
||||
li r5,ERR_TRP_FAIL
|
||||
cmpi 0,0,r6,0x07 /* max supported value */
|
||||
bgt spd_fail
|
||||
rlwimi r7,r6,8,21,23
|
||||
|
||||
READ_SPD(36) /* Get tWR value */
|
||||
beq spd_read_fail
|
||||
rlwinm r3,r3,30,2,31 /* right shift tWR by 2 bits as per DDR2 spec */
|
||||
divwu r6,r3,r9
|
||||
mullw r8,r6,r9
|
||||
subf. r8,r8,r3
|
||||
beq set_twr
|
||||
addi r6,r6,1
|
||||
set_twr:
|
||||
addi r6,r6,-1 /* Tsi108 SDC always gives one extra clock */
|
||||
li r5,ERR_TWR_FAIL
|
||||
cmpi 0,0,r6,0x07 /* max supported value */
|
||||
bgt spd_fail
|
||||
rlwimi r7,r6,5,24,26
|
||||
|
||||
READ_SPD(42) /* Get tRFC */
|
||||
beq spd_read_fail
|
||||
li r5, ERR_TRFC_FAIL
|
||||
/* Tsi108 spec: tRFC=(tRFC + 1)/2 */
|
||||
addi r3,r3,1
|
||||
rlwinm. r3,r3,31,1,31 /* divide by 2 */
|
||||
beq spd_fail
|
||||
divwu r6,r3,r9
|
||||
mullw r8,r6,r9
|
||||
subf. r8,r8,r3
|
||||
beq set_trfc
|
||||
addi r6,r6,1
|
||||
set_trfc:
|
||||
cmpi 0,0,r6,0x1F /* max supported value */
|
||||
bgt spd_fail
|
||||
rlwimi r7,r6,0,27,31
|
||||
|
||||
stw r7,SD_TIMING(r4)
|
||||
sync
|
||||
|
||||
/*
|
||||
* The following two registers are set on per-DIMM basis.
|
||||
* The SD_REFRESH and SD_TIMING settings are common for both DIMMS
|
||||
*/
|
||||
|
||||
do_each_dimm:
|
||||
|
||||
/* Program SDRAM DIMM Control Register */
|
||||
|
||||
li r7, 0 /* clear r7 prior parameter collection */
|
||||
|
||||
READ_SPD(13) /* Get Primary SDRAM Width */
|
||||
beq spd_read_fail
|
||||
cmpi 0,0,r3,4 /* Check for 4-bit SDRAM */
|
||||
beq do_nbank
|
||||
oris r7,r7,0x0010 /* Set MEM_WIDTH bit */
|
||||
|
||||
do_nbank:
|
||||
READ_SPD(17) /* Get Number of banks on SDRAM device */
|
||||
beq spd_read_fail
|
||||
/* Grendel only distinguish betw. 4 or 8-bank memory parts */
|
||||
li r5,ERR_UNKNOWN_PART /* non-supported memory part */
|
||||
cmpi 0,0,r3,4
|
||||
beq do_nrank
|
||||
cmpi 0,0,r3,8
|
||||
bne spd_fail
|
||||
ori r7,r7,0x1000
|
||||
|
||||
do_nrank:
|
||||
READ_SPD(5) /* Get # of Ranks */
|
||||
beq spd_read_fail
|
||||
li r5,ERR_NRANK_INVALID
|
||||
andi. r6,r3,0x7 /* Use bits [2..0] only */
|
||||
beq do_addr_mode
|
||||
cmpi 0,0,r6,1
|
||||
bgt spd_fail
|
||||
rlwimi r7,r6,8,23,23
|
||||
|
||||
do_addr_mode:
|
||||
READ_SPD(4) /* Get # of Column Addresses */
|
||||
beq spd_read_fail
|
||||
li r5, ERR_ADDR_MODE
|
||||
andi. r3,r3,0x0f /* cut off reserved bits */
|
||||
cmpi 0,0,r3,8
|
||||
ble spd_fail
|
||||
cmpi 0,0,r3,15
|
||||
bgt spd_fail
|
||||
addi r6,r3,-8 /* calculate ADDR_MODE parameter */
|
||||
rlwimi r7,r6,4,24,27 /* set ADDR_MODE field */
|
||||
|
||||
set_dimm_ctrl:
|
||||
#ifdef SDC_AUTOPRECH_EN
|
||||
oris r7,r7,0x0001 /* set auto precharge EN bit */
|
||||
#endif
|
||||
ori r7,r7,1 /* set ENABLE bit */
|
||||
cmpi 0,0,r10,SPD_DIMM0
|
||||
bne 1f
|
||||
stw r7,SD_D0_CTRL(r4)
|
||||
sync
|
||||
b set_dimm_bar
|
||||
1:
|
||||
stw r7,SD_D1_CTRL(r4)
|
||||
sync
|
||||
|
||||
|
||||
/* Program SDRAM DIMMx Base Address Register */
|
||||
|
||||
set_dimm_bar:
|
||||
READ_SPD(5) /* get # of Ranks */
|
||||
beq spd_read_fail
|
||||
andi. r7,r3,0x7
|
||||
addi r7,r7,1
|
||||
READ_SPD(31) /* Read DIMM rank density */
|
||||
beq spd_read_fail
|
||||
rlwinm r5,r3,27,29,31
|
||||
rlwinm r6,r3,3,24,28
|
||||
or r5,r6,r5 /* r5 = Normalized Rank Density byte */
|
||||
lis r8, 0x0080 /* 128MB >> 4 */
|
||||
mullw r8,r8,r5 /* r8 = (rank_size >> 4) */
|
||||
mullw r8,r8,r7 /* r8 = (DIMM_size >> 4) */
|
||||
neg r7,r8
|
||||
rlwinm r7,r7,28,4,31
|
||||
or r7,r7,r11 /* set ADDR field */
|
||||
rlwinm r8,r8,12,20,31
|
||||
add r11,r11,r8 /* set Base Addr for next DIMM */
|
||||
|
||||
cmpi 0,0,r10,SPD_DIMM0
|
||||
bne set_dimm1_size
|
||||
stw r7,SD_D0_BAR(r4)
|
||||
sync
|
||||
li r10,SPD_DIMM1
|
||||
READ_SPD(0)
|
||||
bne do_each_dimm
|
||||
b spd_done
|
||||
|
||||
set_dimm1_size:
|
||||
stw r7,SD_D1_BAR(r4)
|
||||
sync
|
||||
spd_done:
|
||||
blr
|
||||
|
||||
check_next_slot:
|
||||
cmpi 0,0,r10,SPD_DIMM1
|
||||
beq spd_read_fail
|
||||
li r10,SPD_DIMM1
|
||||
b do_first_dimm
|
||||
spd_read_fail:
|
||||
ori r3,r0,0xdead
|
||||
b err_hung
|
||||
spd_fail:
|
||||
li r3,0x0bad
|
||||
sync
|
||||
err_hung: /* hang here for debugging */
|
||||
nop
|
||||
nop
|
||||
b err_hung
|
||||
|
||||
#endif /* !SDC_HARDCODED_INIT */
|
|
@ -0,0 +1,28 @@
|
|||
#
|
||||
# Copyright (c) 2005 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
# Flash address
|
||||
TEXT_BASE = 0xFF000000
|
||||
# RAM address
|
||||
#TEXT_BASE = 0x00400000
|
||||
|
||||
PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -maltivec -mabi=altivec -msoft-float
|
|
@ -0,0 +1,107 @@
|
|||
/*
|
||||
* (C) Copyright 2005 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Roy Zang <tie-fei.zang@freescale.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* modifications for the Tsi108 Emul Board by avb@Tundra
|
||||
*/
|
||||
|
||||
/*
|
||||
* board support/init functions for the
|
||||
* Freescale MPC7448 HPC2 (High-Performance Computing 2 Platform).
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <74xx_7xx.h>
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
extern void ft_cpu_setup (void *blob, bd_t *bd);
|
||||
#endif
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
extern void flush_data_cache (void);
|
||||
extern void invalidate_l1_instruction_cache (void);
|
||||
extern void tsi108_init_f (void);
|
||||
|
||||
int display_mem_map (void);
|
||||
|
||||
void after_reloc (ulong dest_addr)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Jump to the main U-Boot board init code
|
||||
*/
|
||||
board_init_r ((gd_t *) gd, dest_addr);
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
/*
|
||||
* Check Board Identity:
|
||||
* report board type
|
||||
*/
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
int l_type = 0;
|
||||
|
||||
printf ("BOARD: %s\n", CFG_BOARD_NAME);
|
||||
return (l_type);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read Processor ID:
|
||||
*
|
||||
* report calling processor number
|
||||
*/
|
||||
|
||||
int read_pid (void)
|
||||
{
|
||||
return 0; /* we are on single CPU platform for a while */
|
||||
}
|
||||
|
||||
long int dram_size (int board_type)
|
||||
{
|
||||
return 0x20000000; /* 256M bytes */
|
||||
}
|
||||
|
||||
long int initdram (int board_type)
|
||||
{
|
||||
return dram_size (board_type);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
|
||||
void
|
||||
ft_board_setup (void *blob, bd_t *bd)
|
||||
{
|
||||
u32 *p;
|
||||
int len;
|
||||
|
||||
ft_cpu_setup (blob, bd);
|
||||
|
||||
p = ft_get_prop (blob, "/memory/reg", &len);
|
||||
if (p != NULL) {
|
||||
*p++ = cpu_to_be32 (bd->bi_memstart);
|
||||
*p = cpu_to_be32 (bd->bi_memsize);
|
||||
}
|
||||
}
|
||||
#endif
|
|
@ -0,0 +1,665 @@
|
|||
/*****************************************************************************
|
||||
* (C) Copyright 2003; Tundra Semiconductor Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*****************************************************************************/
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
* FILENAME: tsi108_init.c
|
||||
*
|
||||
* Originator: Alex Bounine
|
||||
*
|
||||
* DESCRIPTION:
|
||||
* Initialization code for the Tundra Tsi108 bridge chip
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
#include <common.h>
|
||||
#include <74xx_7xx.h>
|
||||
#include <config.h>
|
||||
#include <version.h>
|
||||
#include <asm/processor.h>
|
||||
#include <tsi108.h>
|
||||
|
||||
extern void mpicInit (int verbose);
|
||||
|
||||
/*
|
||||
* Configuration Options
|
||||
*/
|
||||
|
||||
typedef struct {
|
||||
ulong upper;
|
||||
ulong lower;
|
||||
} PB2OCN_LUT_ENTRY;
|
||||
|
||||
PB2OCN_LUT_ENTRY pb2ocn_lut1[32] = {
|
||||
/* 0 - 7 */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xE000_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xE100_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xE200_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xE300_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xE400_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xE500_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xE600_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xE700_0000 -> PCI/X (Byte-Swap) */
|
||||
|
||||
/* 8 - 15 */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xE800_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xE900_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xEA00_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xEB00_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xEC00_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xED00_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xEE00_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xEF00_0000 -> PCI/X (Byte-Swap) */
|
||||
|
||||
/* 16 - 23 */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xF000_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xF100_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xF200_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xF300_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xF400_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xF500_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xF600_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xF700_0000 -> PCI/X (Byte-Swap) */
|
||||
/* 24 - 31 */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xF800_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xF900_0000 -> PCI/X (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xFA00_0000 -> PCI/X PCI I/O (Byte-Swap) */
|
||||
{0x00000000, 0x00000201}, /* PBA=0xFB00_0000 -> PCI/X PCI Config (Byte-Swap) */
|
||||
|
||||
{0x00000000, 0x02000240}, /* PBA=0xFC00_0000 -> HLP */
|
||||
{0x00000000, 0x01000240}, /* PBA=0xFD00_0000 -> HLP */
|
||||
{0x00000000, 0x03000240}, /* PBA=0xFE00_0000 -> HLP */
|
||||
{0x00000000, 0x00000240} /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
|
||||
};
|
||||
|
||||
#ifdef CFG_CLK_SPREAD
|
||||
typedef struct {
|
||||
ulong ctrl0;
|
||||
ulong ctrl1;
|
||||
} PLL_CTRL_SET;
|
||||
|
||||
/*
|
||||
* Clock Generator SPLL0 initialization values
|
||||
* PLL0 configuration table for various PB_CLKO freq.
|
||||
* Uses pre-calculated values for Fs = 30 kHz, D = 0.5%
|
||||
* Fout depends on required PB_CLKO. Based on Fref = 33 MHz
|
||||
*/
|
||||
|
||||
static PLL_CTRL_SET pll0_config[8] = {
|
||||
{0x00000000, 0x00000000}, /* 0: bypass */
|
||||
{0x00000000, 0x00000000}, /* 1: reserved */
|
||||
{0x00430044, 0x00000043}, /* 2: CG_PB_CLKO = 183 MHz */
|
||||
{0x005c0044, 0x00000039}, /* 3: CG_PB_CLKO = 100 MHz */
|
||||
{0x005c0044, 0x00000039}, /* 4: CG_PB_CLKO = 133 MHz */
|
||||
{0x004a0044, 0x00000040}, /* 5: CG_PB_CLKO = 167 MHz */
|
||||
{0x005c0044, 0x00000039}, /* 6: CG_PB_CLKO = 200 MHz */
|
||||
{0x004f0044, 0x0000003e} /* 7: CG_PB_CLKO = 233 MHz */
|
||||
};
|
||||
#endif /* CFG_CLK_SPREAD */
|
||||
|
||||
/*
|
||||
* Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
|
||||
* (based on recommended Tsi108 reference clock 33MHz)
|
||||
*/
|
||||
static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
|
||||
|
||||
/*
|
||||
* get_board_bus_clk ()
|
||||
*
|
||||
* returns the bus clock in Hz.
|
||||
*/
|
||||
unsigned long get_board_bus_clk (void)
|
||||
{
|
||||
ulong i;
|
||||
|
||||
/* Detect PB clock freq. */
|
||||
i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
|
||||
i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
|
||||
|
||||
return pb_clk_sel[i] * 1000000;
|
||||
}
|
||||
|
||||
/*
|
||||
* board_early_init_f ()
|
||||
*
|
||||
* board-specific initialization executed from flash
|
||||
*/
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
ulong i;
|
||||
|
||||
gd->mem_clk = 0;
|
||||
i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
|
||||
CG_PWRUP_STATUS);
|
||||
i = (i >> 20) & 0x07; /* Get GD PLL multiplier */
|
||||
switch (i) {
|
||||
case 0: /* external clock */
|
||||
printf ("Using external clock\n");
|
||||
break;
|
||||
case 1: /* system clock */
|
||||
gd->mem_clk = gd->bus_clk;
|
||||
break;
|
||||
case 4: /* 133 MHz */
|
||||
case 5: /* 166 MHz */
|
||||
case 6: /* 200 MHz */
|
||||
gd->mem_clk = pb_clk_sel[i] * 1000000;
|
||||
break;
|
||||
default:
|
||||
printf ("Invalid DDR2 clock setting\n");
|
||||
return -1;
|
||||
}
|
||||
printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
|
||||
printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* board_early_init_r() - Tsi108 initialization function executed right after
|
||||
* relocation. Contains code that cannot be executed from flash.
|
||||
*/
|
||||
|
||||
int board_early_init_r (void)
|
||||
{
|
||||
ulong temp, i;
|
||||
ulong reg_val;
|
||||
volatile ulong *reg_ptr;
|
||||
|
||||
reg_ptr =
|
||||
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
|
||||
|
||||
for (i = 0; i < 32; i++) {
|
||||
*reg_ptr++ = 0x00000201; /* SWAP ENABLED */
|
||||
*reg_ptr++ = 0x00;
|
||||
}
|
||||
|
||||
__asm__ __volatile__ ("eieio");
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
|
||||
0x80000001);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* Make sure that OCN_BAR2 decoder is set (to allow following immediate
|
||||
* read from SDRAM)
|
||||
*/
|
||||
|
||||
temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/*
|
||||
* Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
|
||||
* processor bus address space. Immediately after reset LUT and address
|
||||
* translation are disabled for this BAR. Now we have to initialize LUT
|
||||
* and switch from the BOOT mode to the normal operation mode.
|
||||
*
|
||||
* The aperture defined by PB_OCN_BAR1 startes at address 0xE0000000
|
||||
* and covers 512MB of address space. To allow larger aperture we also
|
||||
* have to relocate register window of Tsi108
|
||||
*
|
||||
* Initialize LUT (32-entries) prior switching PB_OCN_BAR1 from BOOT
|
||||
* mode.
|
||||
*
|
||||
* initialize pointer to LUT associated with PB_OCN_BAR1
|
||||
*/
|
||||
reg_ptr =
|
||||
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
|
||||
|
||||
for (i = 0; i < 32; i++) {
|
||||
*reg_ptr++ = pb2ocn_lut1[i].lower;
|
||||
*reg_ptr++ = pb2ocn_lut1[i].upper;
|
||||
}
|
||||
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* Base addresses for CS0, CS1, CS2, CS3 */
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
|
||||
0x00000000);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
|
||||
0x00100000);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
|
||||
0x00200000);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
|
||||
0x00300000);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* Masks for HLP banks */
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
|
||||
0xFFF00000);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
|
||||
0xFFF00000);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
|
||||
0xFFF00000);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
|
||||
0xFFF00000);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* Set CTRL0 values for banks */
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
|
||||
0x7FFC44C2);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
|
||||
0x7FFC44C0);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
|
||||
0x7FFC44C0);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
|
||||
0x7FFC44C2);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* Set banks to latched mode, enabled, and other default settings */
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
|
||||
0x7C0F2000);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
|
||||
0x7C0F2000);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
|
||||
0x7C0F2000);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
|
||||
0x7C0F2000);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/*
|
||||
* Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
|
||||
* value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
|
||||
*/
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
|
||||
0xE0000011);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* Make sure that OCN_BAR2 decoder is set (to allow following
|
||||
* immediate read from SDRAM)
|
||||
*/
|
||||
|
||||
temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/*
|
||||
* SRI: At this point we have enabled the HLP banks. That means we can
|
||||
* now read from the NVRAM and initialize the environment variables.
|
||||
* We will over-ride the env_init called in board_init_f
|
||||
* This is really a work-around because, the HLP bank 1
|
||||
* where NVRAM resides is not visible during board_init_f
|
||||
* (lib_ppc/board.c)
|
||||
* Alternatively, we could use the I2C EEPROM at start-up to configure
|
||||
* and enable all HLP banks and not just HLP 0 as is being done for
|
||||
* Taiga Rev. 2.
|
||||
*/
|
||||
|
||||
env_init ();
|
||||
|
||||
#ifndef DISABLE_PBM
|
||||
|
||||
/*
|
||||
* For IBM processors we have to set Address-Only commands generated
|
||||
* by PBM that are different from ones set after reset.
|
||||
*/
|
||||
|
||||
temp = get_cpu_type ();
|
||||
|
||||
if ((CPU_750FX == temp) || (CPU_750GX == temp))
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
|
||||
0x00009955);
|
||||
#endif /* DISABLE_PBM */
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/*
|
||||
* Initialize PCI/X block
|
||||
*/
|
||||
|
||||
/* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
|
||||
PCI_PFAB_BAR0_UPPER, 0);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
|
||||
0xFB000001);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
|
||||
|
||||
temp = in32(CFG_TSI108_CSR_BASE +
|
||||
TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
|
||||
|
||||
temp &= ~0xFF00; /* Clear the BUS_NUM field */
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
|
||||
temp);
|
||||
|
||||
/* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
|
||||
0);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* This register is on the PCI side to interpret the address it receives
|
||||
* and maps it as a IO address.
|
||||
*/
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
|
||||
0xFA000001);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/*
|
||||
* Map PCI/X Memory Space
|
||||
*
|
||||
* Transactions directed from OCM to PCI Memory Space are directed
|
||||
* from PB to PCI
|
||||
* unchanged (as defined by PB_OCN_BAR1,2 and LUT settings).
|
||||
* If address remapping is required the corresponding PCI_PFAB_MEM32
|
||||
* and PCI_PFAB_PFMx register groups have to be configured.
|
||||
*
|
||||
* Map the path from the PCI/X bus into the system memory
|
||||
*
|
||||
* The memory mapped window assotiated with PCI P2O_BAR2 provides
|
||||
* access to the system memory without address remapping.
|
||||
* All system memory is opened for accesses initiated by PCI/X bus
|
||||
* masters.
|
||||
*
|
||||
* Initialize LUT associated with PCI P2O_BAR2
|
||||
*
|
||||
* set pointer to LUT associated with PCI P2O_BAR2
|
||||
*/
|
||||
|
||||
reg_ptr =
|
||||
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
|
||||
|
||||
#ifdef DISABLE_PBM
|
||||
|
||||
/* In case when PBM is disabled (no HW supported cache snoopng on PB)
|
||||
* P2O_BAR2 is directly mapped into the system memory without address
|
||||
* translation.
|
||||
*/
|
||||
|
||||
reg_val = 0x00000004; /* SDRAM port + NO Addr_Translation */
|
||||
|
||||
for (i = 0; i < 32; i++) {
|
||||
*reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
|
||||
*reg_ptr++ = 0; /* P2O_BAR2_LUT_UPPERx */
|
||||
}
|
||||
|
||||
/* value for PCI BAR2 (size = 512MB, Enabled, No Addr. Translation) */
|
||||
reg_val = 0x00007500;
|
||||
#else
|
||||
|
||||
reg_val = 0x00000002; /* Destination port = PBM */
|
||||
|
||||
for (i = 0; i < 32; i++) {
|
||||
*reg_ptr++ = reg_val; /* P2O_BAR2_LUTx */
|
||||
/* P2O_BAR2_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
|
||||
*reg_ptr++ = 0x40000000;
|
||||
/* offset = 16MB, address translation is enabled to allow byte swapping */
|
||||
reg_val += 0x01000000;
|
||||
}
|
||||
|
||||
/* value for PCI BAR2 (size = 512MB, Enabled, Address Translation Enabled) */
|
||||
reg_val = 0x00007100;
|
||||
#endif
|
||||
|
||||
__asm__ __volatile__ ("eieio");
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
|
||||
reg_val);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* Set 64-bit PCI bus address for system memory
|
||||
* ( 0 is the best choice for easy mapping)
|
||||
*/
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
|
||||
0x00000000);
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
|
||||
0x00000000);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
#ifndef DISABLE_PBM
|
||||
/*
|
||||
* The memory mapped window assotiated with PCI P2O_BAR3 provides
|
||||
* access to the system memory using SDRAM OCN port and address
|
||||
* translation. This is alternative way to access SDRAM from PCI
|
||||
* required for Tsi108 emulation testing.
|
||||
* All system memory is opened for accesses initiated by
|
||||
* PCI/X bus masters.
|
||||
*
|
||||
* Initialize LUT associated with PCI P2O_BAR3
|
||||
*
|
||||
* set pointer to LUT associated with PCI P2O_BAR3
|
||||
*/
|
||||
reg_ptr =
|
||||
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
|
||||
|
||||
reg_val = 0x00000004; /* Destination port = SDC */
|
||||
|
||||
for (i = 0; i < 32; i++) {
|
||||
*reg_ptr++ = reg_val; /* P2O_BAR3_LUTx */
|
||||
|
||||
/* P2O_BAR3_LUT_UPPERx : Set data swapping mode for PBM (byte swapping) */
|
||||
*reg_ptr++ = 0;
|
||||
|
||||
/* offset = 16MB, address translation is enabled to allow byte swapping */
|
||||
reg_val += 0x01000000;
|
||||
}
|
||||
|
||||
__asm__ __volatile__ ("eieio");
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
|
||||
|
||||
reg_val =
|
||||
in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
|
||||
PCI_P2O_PAGE_SIZES);
|
||||
reg_val &= ~0x00FF;
|
||||
reg_val |= 0x0071;
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
|
||||
reg_val);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/* Set 64-bit base PCI bus address for window (0x20000000) */
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
|
||||
0x00000000);
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
|
||||
0x20000000);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
#endif /* !DISABLE_PBM */
|
||||
|
||||
#ifdef ENABLE_PCI_CSR_BAR
|
||||
/* open if required access to Tsi108 CSRs from the PCI/X bus */
|
||||
/* enable BAR0 on the PCI/X bus */
|
||||
reg_val = in32(CFG_TSI108_CSR_BASE +
|
||||
TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
|
||||
reg_val |= 0x02;
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
|
||||
reg_val);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
|
||||
0x00000000);
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
|
||||
CFG_TSI108_CSR_BASE);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Finally enable PCI/X Bus Master and Memory Space access
|
||||
*/
|
||||
|
||||
reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
|
||||
reg_val |= 0x06;
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/*
|
||||
* Initialize MPIC outputs (interrupt pins):
|
||||
* Interrupt routing on the Grendel Emul. Board:
|
||||
* PB_INT[0] -> INT (CPU0)
|
||||
* PB_INT[1] -> INT (CPU1)
|
||||
* PB_INT[2] -> MCP (CPU0)
|
||||
* PB_INT[3] -> MCP (CPU1)
|
||||
* Set interrupt controller outputs as Level_Sensitive/Active_Low
|
||||
*/
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
|
||||
__asm__ __volatile__ ("sync");
|
||||
|
||||
/*
|
||||
* Ensure that Machine Check exception is enabled
|
||||
* We need it to support PCI Bus probing (configuration reads)
|
||||
*/
|
||||
|
||||
reg_val = mfmsr ();
|
||||
mtmsr(reg_val | MSR_ME);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Needed to print out L2 cache info
|
||||
* used in the misc_init_r function
|
||||
*/
|
||||
|
||||
unsigned long get_l2cr (void)
|
||||
{
|
||||
unsigned long l2controlreg;
|
||||
asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
|
||||
return l2controlreg;
|
||||
}
|
||||
|
||||
/*
|
||||
* misc_init_r()
|
||||
*
|
||||
* various things to do after relocation
|
||||
*
|
||||
*/
|
||||
|
||||
int misc_init_r (void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
|
||||
ulong i;
|
||||
|
||||
/* Ensure that Spread-Spectrum is disabled */
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
|
||||
|
||||
/* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
|
||||
* Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
|
||||
*/
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
|
||||
0x002e0044); /* D = 0.25% */
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
|
||||
0x00000039); /* BWADJ */
|
||||
|
||||
/* Initialize PLL0: CG_PB_CLKO */
|
||||
/* Detect PB clock freq. */
|
||||
i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
|
||||
i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
|
||||
|
||||
out32 (CFG_TSI108_CSR_BASE +
|
||||
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
|
||||
out32 (CFG_TSI108_CSR_BASE +
|
||||
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
|
||||
|
||||
/* Wait and set SSEN for both PLL0 and 1 */
|
||||
udelay (1000);
|
||||
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
|
||||
0x802e0044); /* D=0.25% */
|
||||
out32 (CFG_TSI108_CSR_BASE +
|
||||
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
|
||||
0x80000000 | pll0_config[i].ctrl0);
|
||||
#endif /* CFG_CLK_SPREAD */
|
||||
|
||||
#ifdef CFG_L2
|
||||
l2cache_enable ();
|
||||
#endif
|
||||
printf ("BUS: %d MHz\n", gd->bus_clk / 1000000);
|
||||
printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
|
||||
|
||||
/*
|
||||
* All the information needed to print the cache details is avaiblable
|
||||
* at this point i.e. above call to l2cache_enable is the very last
|
||||
* thing done with regards to enabling diabling the cache.
|
||||
* So this seems like a good place to print all this information
|
||||
*/
|
||||
|
||||
printf ("CACHE: ");
|
||||
switch (get_cpu_type()) {
|
||||
case CPU_7447A:
|
||||
printf ("L1 Instruction cache - 32KB 8-way");
|
||||
(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
|
||||
printf (" DISABLED\n");
|
||||
printf ("L1 Data cache - 32KB 8-way");
|
||||
(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
|
||||
printf (" DISABLED\n");
|
||||
printf ("Unified L2 cache - 512KB 8-way");
|
||||
(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
|
||||
printf (" DISABLED\n");
|
||||
printf ("\n");
|
||||
break;
|
||||
|
||||
case CPU_7448:
|
||||
printf ("L1 Instruction cache - 32KB 8-way");
|
||||
(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
|
||||
printf (" DISABLED\n");
|
||||
printf ("L1 Data cache - 32KB 8-way");
|
||||
(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
|
||||
printf (" DISABLED\n");
|
||||
printf ("Unified L2 cache - 1MB 8-way");
|
||||
(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
|
||||
printf (" DISABLED\n");
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
|
@ -0,0 +1,136 @@
|
|||
/*
|
||||
* (C) Copyright 2001
|
||||
* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
* u-boot.lds - linker script for U-Boot on mpc7448hpc2 Board.
|
||||
*/
|
||||
|
||||
OUTPUT_ARCH(powerpc)
|
||||
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||
/* Do we need any of these for elf?
|
||||
__DYNAMIC = 0; */
|
||||
SECTIONS
|
||||
{
|
||||
/* Read-only sections, merged into text segment: */
|
||||
. = + SIZEOF_HEADERS;
|
||||
.interp : { *(.interp) }
|
||||
.hash : { *(.hash) }
|
||||
.dynsym : { *(.dynsym) }
|
||||
.dynstr : { *(.dynstr) }
|
||||
.rel.text : { *(.rel.text) }
|
||||
.rela.text : { *(.rela.text) }
|
||||
.rel.data : { *(.rel.data) }
|
||||
.rela.data : { *(.rela.data) }
|
||||
.rel.rodata : { *(.rel.rodata) }
|
||||
.rela.rodata : { *(.rela.rodata) }
|
||||
.rel.got : { *(.rel.got) }
|
||||
.rela.got : { *(.rela.got) }
|
||||
.rel.ctors : { *(.rel.ctors) }
|
||||
.rela.ctors : { *(.rela.ctors) }
|
||||
.rel.dtors : { *(.rel.dtors) }
|
||||
.rela.dtors : { *(.rela.dtors) }
|
||||
.rel.bss : { *(.rel.bss) }
|
||||
.rela.bss : { *(.rela.bss) }
|
||||
.rel.plt : { *(.rel.plt) }
|
||||
.rela.plt : { *(.rela.plt) }
|
||||
.init : { *(.init) }
|
||||
.plt : { *(.plt) }
|
||||
.text :
|
||||
{
|
||||
cpu/74xx_7xx/start.o (.text)
|
||||
|
||||
/* store the environment in a seperate sector in the boot flash */
|
||||
/* . = env_offset; */
|
||||
/* common/environment.o(.text) */
|
||||
|
||||
*(.text)
|
||||
*(.fixup)
|
||||
*(.got1)
|
||||
}
|
||||
_etext = .;
|
||||
PROVIDE (etext = .);
|
||||
.rodata :
|
||||
{
|
||||
*(.rodata)
|
||||
*(.rodata1)
|
||||
*(.rodata.str1.4)
|
||||
}
|
||||
.fini : { *(.fini) } =0
|
||||
.ctors : { *(.ctors) }
|
||||
.dtors : { *(.dtors) }
|
||||
|
||||
/* Read-write section, merged into data segment: */
|
||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||
_erotext = .;
|
||||
PROVIDE (erotext = .);
|
||||
.reloc :
|
||||
{
|
||||
*(.got)
|
||||
_GOT2_TABLE_ = .;
|
||||
*(.got2)
|
||||
_FIXUP_TABLE_ = .;
|
||||
*(.fixup)
|
||||
}
|
||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||
|
||||
.data :
|
||||
{
|
||||
*(.data)
|
||||
*(.data1)
|
||||
*(.sdata)
|
||||
*(.sdata2)
|
||||
*(.dynamic)
|
||||
CONSTRUCTORS
|
||||
}
|
||||
_edata = .;
|
||||
PROVIDE (edata = .);
|
||||
|
||||
. = .;
|
||||
__u_boot_cmd_start = .;
|
||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||
__u_boot_cmd_end = .;
|
||||
|
||||
. = .;
|
||||
__start___ex_table = .;
|
||||
__ex_table : { *(__ex_table) }
|
||||
__stop___ex_table = .;
|
||||
|
||||
. = ALIGN(256);
|
||||
__init_begin = .;
|
||||
.text.init : { *(.text.init) }
|
||||
.data.init : { *(.data.init) }
|
||||
. = ALIGN(256);
|
||||
__init_end = .;
|
||||
|
||||
__bss_start = .;
|
||||
.bss :
|
||||
{
|
||||
*(.sbss) *(.scommon)
|
||||
*(.dynbss)
|
||||
*(.bss)
|
||||
*(COMMON)
|
||||
}
|
||||
_end = . ;
|
||||
PROVIDE (end = .);
|
||||
}
|
|
@ -26,8 +26,3 @@
|
|||
#
|
||||
|
||||
TEXT_BASE = 0xFE000000
|
||||
|
||||
#
|
||||
# Additional board-specific libraries
|
||||
#
|
||||
BOARDLIBS = libfdt/libfdt.a
|
||||
|
|
|
@ -664,19 +664,28 @@ U_BOOT_CMD(ecc, 4, 0, do_ecc,
|
|||
|
||||
#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \
|
||||
&& defined(CONFIG_OF_BOARD_SETUP)
|
||||
|
||||
/*
|
||||
* Prototypes of functions that we use.
|
||||
*/
|
||||
void ft_cpu_setup(void *blob, bd_t *bd);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
void ft_pci_setup(void *blob, bd_t *bd);
|
||||
#endif
|
||||
|
||||
void
|
||||
ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
int nodeoffset;
|
||||
int err;
|
||||
int tmp[2];
|
||||
|
||||
nodeoffset = fdt_path_offset (fdt, "/memory");
|
||||
if (nodeoffset >= 0) {
|
||||
tmp[0] = cpu_to_be32(bd->bi_memstart);
|
||||
tmp[1] = cpu_to_be32(bd->bi_memsize);
|
||||
err = fdt_setprop(fdt, nodeoffset, "reg", tmp, sizeof(tmp));
|
||||
fdt_setprop(fdt, nodeoffset, "reg", tmp, sizeof(tmp));
|
||||
}
|
||||
#else
|
||||
u32 *p;
|
||||
|
@ -694,4 +703,4 @@ ft_board_setup(void *blob, bd_t *bd)
|
|||
#endif
|
||||
ft_cpu_setup(blob, bd);
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_OF_x */
|
||||
|
|
|
@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS := $(BOARD).o pixis.o sys_eeprom.o
|
||||
COBJS := $(BOARD).o sys_eeprom.o \
|
||||
../freescale/common/pixis.o
|
||||
|
||||
SOBJS := init.o
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
|
|
|
@ -1,9 +1,5 @@
|
|||
/*
|
||||
* Copyright 2004 Freescale Semiconductor.
|
||||
* Jeff Brown
|
||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
||||
*
|
||||
* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
|
||||
* Copyright 2006, 2007 Freescale Semiconductor.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -25,18 +21,18 @@
|
|||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <pci.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/immap_86xx.h>
|
||||
#include <spd.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
extern void ft_cpu_setup(void *blob, bd_t *bd);
|
||||
#endif
|
||||
|
||||
#include "pixis.h"
|
||||
#include "../freescale/common/pixis.h"
|
||||
|
||||
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
||||
extern void ddr_enable_ecc(unsigned int dram_size);
|
||||
|
@ -258,109 +254,6 @@ ft_board_setup(void *blob, bd_t *bd)
|
|||
#endif
|
||||
|
||||
|
||||
void
|
||||
mpc8641_reset_board(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
||||
{
|
||||
char cmd;
|
||||
ulong val;
|
||||
ulong corepll;
|
||||
|
||||
/*
|
||||
* No args is a simple reset request.
|
||||
*/
|
||||
if (argc <= 1) {
|
||||
out8(PIXIS_BASE + PIXIS_RST, 0);
|
||||
/* not reached */
|
||||
}
|
||||
|
||||
cmd = argv[1][1];
|
||||
switch (cmd) {
|
||||
case 'f': /* reset with frequency changed */
|
||||
if (argc < 5)
|
||||
goto my_usage;
|
||||
read_from_px_regs(0);
|
||||
|
||||
val = set_px_sysclk(simple_strtoul(argv[2], NULL, 10));
|
||||
|
||||
corepll = strfractoint(argv[3]);
|
||||
val = val + set_px_corepll(corepll);
|
||||
val = val + set_px_mpxpll(simple_strtoul(argv[4], NULL, 10));
|
||||
if (val == 3) {
|
||||
puts("Setting registers VCFGEN0 and VCTL\n");
|
||||
read_from_px_regs(1);
|
||||
puts("Resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL ....\n");
|
||||
set_px_go();
|
||||
} else
|
||||
goto my_usage;
|
||||
|
||||
while (1) ; /* Not reached */
|
||||
|
||||
case 'l':
|
||||
if (argv[2][1] == 'f') {
|
||||
read_from_px_regs(0);
|
||||
read_from_px_regs_altbank(0);
|
||||
/* reset with frequency changed */
|
||||
val = set_px_sysclk(simple_strtoul(argv[3], NULL, 10));
|
||||
|
||||
corepll = strfractoint(argv[4]);
|
||||
val = val + set_px_corepll(corepll);
|
||||
val = val + set_px_mpxpll(simple_strtoul(argv[5],
|
||||
NULL, 10));
|
||||
if (val == 3) {
|
||||
puts("Setting registers VCFGEN0, VCFGEN1, VBOOT, and VCTL\n");
|
||||
set_altbank();
|
||||
read_from_px_regs(1);
|
||||
read_from_px_regs_altbank(1);
|
||||
puts("Enabling watchdog timer on the FPGA and resetting board with values from VSPEED0, VSPEED1, VCLKH, and VCLKL to boot from the other bank ....\n");
|
||||
set_px_go_with_watchdog();
|
||||
} else
|
||||
goto my_usage;
|
||||
|
||||
while (1) ; /* Not reached */
|
||||
|
||||
} else if (argv[2][1] == 'd') {
|
||||
/*
|
||||
* Reset from alternate bank without changing
|
||||
* frequencies but with watchdog timer enabled.
|
||||
*/
|
||||
read_from_px_regs(0);
|
||||
read_from_px_regs_altbank(0);
|
||||
puts("Setting registers VCFGEN1, VBOOT, and VCTL\n");
|
||||
set_altbank();
|
||||
read_from_px_regs_altbank(1);
|
||||
puts("Enabling watchdog timer on the FPGA and resetting board to boot from the other bank....\n");
|
||||
set_px_go_with_watchdog();
|
||||
while (1) ; /* Not reached */
|
||||
|
||||
} else {
|
||||
/*
|
||||
* Reset from next bank without changing
|
||||
* frequency and without watchdog timer enabled.
|
||||
*/
|
||||
read_from_px_regs(0);
|
||||
read_from_px_regs_altbank(0);
|
||||
if (argc > 2)
|
||||
goto my_usage;
|
||||
puts("Setting registers VCFGNE1, VBOOT, and VCTL\n");
|
||||
set_altbank();
|
||||
read_from_px_regs_altbank(1);
|
||||
puts("Resetting board to boot from the other bank....\n");
|
||||
set_px_go();
|
||||
}
|
||||
|
||||
default:
|
||||
goto my_usage;
|
||||
}
|
||||
|
||||
my_usage:
|
||||
puts("\nUsage: reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n");
|
||||
puts(" reset altbank [cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>]\n");
|
||||
puts(" reset altbank [wd]\n");
|
||||
puts("For example: reset cf 40 2.5 10\n");
|
||||
puts("See MPC8641HPCN Design Workbook for valid values of command line parameters.\n");
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* get_board_sys_clk
|
||||
* Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# (C) Copyright 2006 Detlev Zundel, dzu@denx.de
|
||||
# (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de
|
||||
# (C) Copyright 2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
#
|
||||
|
@ -27,4 +27,3 @@
|
|||
#
|
||||
|
||||
TEXT_BASE = 0x40700000
|
||||
BOARDLIBS = $(obj)drivers/nand/libnand.a
|
||||
|
|
|
@ -177,16 +177,14 @@ long int initdram (int board_type)
|
|||
*
|
||||
* try 8 column mode
|
||||
*/
|
||||
size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
|
||||
SDRAM_MAX_SIZE);
|
||||
size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
|
||||
|
||||
udelay (1000);
|
||||
|
||||
/*
|
||||
* try 9 column mode
|
||||
*/
|
||||
size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE3_PRELIM,
|
||||
SDRAM_MAX_SIZE);
|
||||
size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
|
||||
|
||||
udelay (1000);
|
||||
|
||||
|
|
|
@ -45,7 +45,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
|
|||
env_nand.o env_dataflash.o env_flash.o env_eeprom.o \
|
||||
env_nvram.o env_nowhere.o \
|
||||
exports.o \
|
||||
flash.o fpga.o ft_build.o \
|
||||
fdt_support.o flash.o fpga.o ft_build.o \
|
||||
hush.o kgdb.o lcd.o lists.o lynxkdi.o \
|
||||
memsize.o miiphybb.o miiphyutil.o \
|
||||
s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
|
||||
|
|
|
@ -37,6 +37,7 @@
|
|||
#if defined(CONFIG_OF_LIBFDT)
|
||||
#include <fdt.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#endif
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
|
@ -748,7 +749,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
of_flat_tree = (char *) simple_strtoul(argv[3], NULL, 16);
|
||||
hdr = (image_header_t *)of_flat_tree;
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
if (be32_to_cpu(fdt_magic(of_flat_tree)) == FDT_MAGIC) {
|
||||
if (fdt_check_header(of_flat_tree) == 0) {
|
||||
#else
|
||||
if (*(ulong *)of_flat_tree == OF_DT_HEADER) {
|
||||
#endif
|
||||
|
@ -795,7 +796,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
return;
|
||||
}
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
if (be32_to_cpu(fdt_magic(of_flat_tree + sizeof(image_header_t))) != FDT_MAGIC) {
|
||||
if (fdt_check_header(of_flat_tree + sizeof(image_header_t)) == 0) {
|
||||
#else
|
||||
if (*((ulong *)(of_flat_tree + sizeof(image_header_t))) != OF_DT_HEADER) {
|
||||
#endif
|
||||
|
@ -836,7 +837,7 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
}
|
||||
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
if (be32_to_cpu(fdt_magic(of_data)) != FDT_MAGIC) {
|
||||
if (fdt_check_header((void *)of_data) != 0) {
|
||||
#else
|
||||
if (((struct boot_param_header *)of_data)->magic != OF_DT_HEADER) {
|
||||
#endif
|
||||
|
@ -937,23 +938,44 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
if (of_data) {
|
||||
int err;
|
||||
ulong of_start, of_len;
|
||||
|
||||
of_len = be32_to_cpu(fdt_totalsize(of_data));
|
||||
/* provide extra 8k pad */
|
||||
/* position on a 4K boundary before the initrd/kbd */
|
||||
if (initrd_start)
|
||||
of_start = initrd_start - of_len - 8192;
|
||||
of_start = initrd_start - of_len;
|
||||
else
|
||||
of_start = (ulong)kbd - of_len - 8192;
|
||||
of_start = (ulong)kbd - of_len;
|
||||
of_start &= ~(4096 - 1); /* align on page */
|
||||
debug ("## device tree at 0x%08lX ... 0x%08lX (len=%ld=0x%lX)\n",
|
||||
of_data, of_data + of_len - 1, of_len, of_len);
|
||||
|
||||
|
||||
of_flat_tree = (char *)of_start;
|
||||
printf (" Loading Device Tree to %08lx, end %08lx ... ",
|
||||
of_start, of_start + of_len - 1);
|
||||
err = fdt_open_into(of_start, of_data, of_len);
|
||||
err = fdt_open_into((void *)of_start, (void *)of_data, of_len);
|
||||
if (err != 0) {
|
||||
printf ("libfdt: %s\n", fdt_strerror(err));
|
||||
printf ("libfdt: %s " __FILE__ " %d\n", fdt_strerror(err), __LINE__);
|
||||
}
|
||||
/*
|
||||
* Add the chosen node if it doesn't exist, add the env and bd_t
|
||||
* if the user wants it (the logic is in the subroutines).
|
||||
*/
|
||||
if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
|
||||
printf("Failed creating the /chosen node (0x%08X), aborting.\n", of_flat_tree);
|
||||
return;
|
||||
}
|
||||
#ifdef CONFIG_OF_HAS_UBOOT_ENV
|
||||
if (fdt_env(of_flat_tree) < 0) {
|
||||
printf("Failed creating the /u-boot-env node, aborting.\n");
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_OF_HAS_BD_T
|
||||
if (fdt_bd_t(of_flat_tree) < 0) {
|
||||
printf("Failed creating the /bd_t node, aborting.\n");
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
|
@ -1004,6 +1026,24 @@ do_bootm_linux (cmd_tbl_t *cmdtp, int flag,
|
|||
ft_setup(of_flat_tree, kbd, initrd_start, initrd_end);
|
||||
/* ft_dump_blob(of_flat_tree); */
|
||||
#endif
|
||||
#if defined(CONFIG_OF_LIBFDT)
|
||||
if (fdt_chosen(of_flat_tree, initrd_start, initrd_end, 0) < 0) {
|
||||
printf("Failed creating the /chosen node (0x%08X), aborting.\n", of_flat_tree);
|
||||
return;
|
||||
}
|
||||
#ifdef CONFIG_OF_HAS_UBOOT_ENV
|
||||
if (fdt_env(of_flat_tree) < 0) {
|
||||
printf("Failed creating the /u-boot-env node, aborting.\n");
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
#ifdef CONFIG_OF_HAS_BD_T
|
||||
if (fdt_bd_t(of_flat_tree) < 0) {
|
||||
printf("Failed creating the /bd_t node, aborting.\n");
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
#endif /* if defined(CONFIG_OF_LIBFDT) */
|
||||
|
||||
(*kernel) ((bd_t *)of_flat_tree, (ulong)kernel, 0, 0, 0);
|
||||
#endif
|
||||
|
|
301
common/cmd_fdt.c
301
common/cmd_fdt.c
|
@ -30,9 +30,11 @@
|
|||
#include <linux/types.h>
|
||||
|
||||
#ifdef CONFIG_OF_LIBFDT
|
||||
|
||||
#include <asm/global_data.h>
|
||||
#include <fdt.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
|
||||
#define MAX_LEVEL 32 /* how deeply nested we will go */
|
||||
#define SCRATCHPAD 1024 /* bytes of scratchpad memory */
|
||||
|
@ -53,9 +55,6 @@ static char data[SCRATCHPAD];
|
|||
*/
|
||||
static int fdt_valid(void);
|
||||
static void print_data(const void *data, int len);
|
||||
static int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end);
|
||||
static int fdt_env(void *fdt);
|
||||
static int fdt_bd_t(void *fdt);
|
||||
|
||||
|
||||
/*
|
||||
|
@ -437,7 +436,7 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
|||
* Create a chosen node
|
||||
********************************************************************/
|
||||
} else if (op == 'c') {
|
||||
fdt_chosen(fdt, 0, 0);
|
||||
fdt_chosen(fdt, 0, 0, 1);
|
||||
|
||||
/********************************************************************
|
||||
* Create a u-boot-env node
|
||||
|
@ -466,25 +465,36 @@ int do_fdt (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
|||
|
||||
static int fdt_valid(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
if (fdt == NULL) {
|
||||
printf ("The address of the fdt is invalid.\n");
|
||||
printf ("The address of the fdt is invalid (NULL).\n");
|
||||
return 0;
|
||||
}
|
||||
if (!fdt || (fdt_magic(fdt) != FDT_MAGIC)) {
|
||||
fdt = NULL;
|
||||
printf ("Unrecognized fdt: bad magic\n");
|
||||
return 0;
|
||||
}
|
||||
if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION) {
|
||||
printf ("Unsupported fdt version: $d < %d\n",
|
||||
FDT_FIRST_SUPPORTED_VERSION, fdt_version(fdt));
|
||||
fdt = NULL;
|
||||
return 0;
|
||||
}
|
||||
if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION) {
|
||||
printf ("Unsupported fdt version: $d > %d\n",
|
||||
fdt_version(fdt), FDT_LAST_SUPPORTED_VERSION);
|
||||
fdt = NULL;
|
||||
|
||||
err = fdt_check_header(fdt);
|
||||
if (err == 0)
|
||||
return 1; /* valid */
|
||||
|
||||
if (err < 0) {
|
||||
printf("libfdt: %s", fdt_strerror(err));
|
||||
/*
|
||||
* Be more informative on bad version.
|
||||
*/
|
||||
if (err == -FDT_ERR_BADVERSION) {
|
||||
if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION) {
|
||||
printf (" - too old, fdt $d < %d",
|
||||
fdt_version(fdt), FDT_FIRST_SUPPORTED_VERSION);
|
||||
fdt = NULL;
|
||||
}
|
||||
if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION) {
|
||||
printf (" - too new, fdt $d > %d",
|
||||
fdt_version(fdt), FDT_LAST_SUPPORTED_VERSION);
|
||||
fdt = NULL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
printf("\n");
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
|
@ -593,255 +603,6 @@ static void print_data(const void *data, int len)
|
|||
|
||||
/********************************************************************/
|
||||
|
||||
static int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end)
|
||||
{
|
||||
bd_t *bd = gd->bd;
|
||||
int nodeoffset;
|
||||
int err;
|
||||
u32 tmp; /* used to set 32 bit integer properties */
|
||||
char *str; /* used to set string properties */
|
||||
ulong clock;
|
||||
|
||||
if (initrd_start && initrd_end) {
|
||||
err = fdt_add_reservemap_entry(fdt,
|
||||
initrd_start, initrd_end - initrd_start + 1);
|
||||
if (err < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* See if we already have a "chosen" node, create it if not.
|
||||
*/
|
||||
nodeoffset = fdt_path_offset (fdt, "/chosen");
|
||||
if (nodeoffset < 0) {
|
||||
/*
|
||||
* Create a new node "/chosen" (offset 0 is root level)
|
||||
*/
|
||||
nodeoffset = fdt_add_subnode(fdt, 0, "chosen");
|
||||
if (nodeoffset < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(nodeoffset));
|
||||
return nodeoffset;
|
||||
}
|
||||
}
|
||||
|
||||
str = getenv("bootargs");
|
||||
if (str != NULL) {
|
||||
err = fdt_setprop(fdt, nodeoffset, "bootargs", str, strlen(str)+1);
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
}
|
||||
if (initrd_start && initrd_end) {
|
||||
tmp = __cpu_to_be32(initrd_start);
|
||||
err = fdt_setprop(fdt, nodeoffset, "linux,initrd-start", &tmp, sizeof(tmp));
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
tmp = __cpu_to_be32(initrd_end);
|
||||
err = fdt_setprop(fdt, nodeoffset, "linux,initrd-end", &tmp, sizeof(tmp));
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
}
|
||||
#ifdef OF_STDOUT_PATH
|
||||
err = fdt_setprop(fdt, nodeoffset, "linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1);
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
#endif
|
||||
|
||||
nodeoffset = fdt_path_offset (fdt, "/cpus");
|
||||
if (nodeoffset >= 0) {
|
||||
clock = cpu_to_be32(bd->bi_intfreq);
|
||||
err = fdt_setprop(fdt, nodeoffset, "clock-frequency", &clock, 4);
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
}
|
||||
#ifdef OF_TBCLK
|
||||
nodeoffset = fdt_path_offset (fdt, "/cpus/" OF_CPU "/timebase-frequency");
|
||||
if (nodeoffset >= 0) {
|
||||
clock = cpu_to_be32(OF_TBCLK);
|
||||
err = fdt_setprop(fdt, nodeoffset, "clock-frequency", &clock, 4);
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#ifdef CONFIG_OF_HAS_BD_T
|
||||
|
||||
/* Function that returns a character from the environment */
|
||||
extern uchar(*env_get_char) (int);
|
||||
|
||||
#define BDM(x) { .name = #x, .offset = offsetof(bd_t, bi_ ##x ) }
|
||||
|
||||
static const struct {
|
||||
const char *name;
|
||||
int offset;
|
||||
} bd_map[] = {
|
||||
BDM(memstart),
|
||||
BDM(memsize),
|
||||
BDM(flashstart),
|
||||
BDM(flashsize),
|
||||
BDM(flashoffset),
|
||||
BDM(sramstart),
|
||||
BDM(sramsize),
|
||||
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
|
||||
|| defined(CONFIG_E500)
|
||||
BDM(immr_base),
|
||||
#endif
|
||||
#if defined(CONFIG_MPC5xxx)
|
||||
BDM(mbar_base),
|
||||
#endif
|
||||
#if defined(CONFIG_MPC83XX)
|
||||
BDM(immrbar),
|
||||
#endif
|
||||
#if defined(CONFIG_MPC8220)
|
||||
BDM(mbar_base),
|
||||
BDM(inpfreq),
|
||||
BDM(pcifreq),
|
||||
BDM(pevfreq),
|
||||
BDM(flbfreq),
|
||||
BDM(vcofreq),
|
||||
#endif
|
||||
BDM(bootflags),
|
||||
BDM(ip_addr),
|
||||
BDM(intfreq),
|
||||
BDM(busfreq),
|
||||
#ifdef CONFIG_CPM2
|
||||
BDM(cpmfreq),
|
||||
BDM(brgfreq),
|
||||
BDM(sccfreq),
|
||||
BDM(vco),
|
||||
#endif
|
||||
#if defined(CONFIG_MPC5xxx)
|
||||
BDM(ipbfreq),
|
||||
BDM(pcifreq),
|
||||
#endif
|
||||
BDM(baudrate),
|
||||
};
|
||||
|
||||
static int fdt_env(void *fdt)
|
||||
{
|
||||
int nodeoffset;
|
||||
int err;
|
||||
int k, nxt;
|
||||
int i;
|
||||
static char tmpenv[256];
|
||||
|
||||
/*
|
||||
* See if we already have a "u-boot-env" node, delete it if so.
|
||||
* Then create a new empty node.
|
||||
*/
|
||||
nodeoffset = fdt_path_offset (fdt, "/u-boot-env");
|
||||
if (nodeoffset >= 0) {
|
||||
err = fdt_del_node(fdt, nodeoffset);
|
||||
if (err < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
}
|
||||
/*
|
||||
* Create a new node "/u-boot-env" (offset 0 is root level)
|
||||
*/
|
||||
nodeoffset = fdt_add_subnode(fdt, 0, "u-boot-env");
|
||||
if (nodeoffset < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(nodeoffset));
|
||||
return nodeoffset;
|
||||
}
|
||||
|
||||
for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
|
||||
char *s, *lval, *rval;
|
||||
|
||||
/*
|
||||
* Find the end of the name=definition
|
||||
*/
|
||||
for (nxt = i; env_get_char(nxt) != '\0'; ++nxt)
|
||||
;
|
||||
s = tmpenv;
|
||||
for (k = i; k < nxt && s < &tmpenv[sizeof(tmpenv) - 1]; ++k)
|
||||
*s++ = env_get_char(k);
|
||||
*s++ = '\0';
|
||||
lval = tmpenv;
|
||||
/*
|
||||
* Find the first '=': it separates the name from the value
|
||||
*/
|
||||
s = strchr(tmpenv, '=');
|
||||
if (s != NULL) {
|
||||
*s++ = '\0';
|
||||
rval = s;
|
||||
} else
|
||||
continue;
|
||||
err = fdt_setprop(fdt, nodeoffset, lval, rval, strlen(rval)+1);
|
||||
if (err < 0) {
|
||||
printf("\"%s\" - libfdt: %s\n", lval, fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_OF_HAS_UBOOT_ENV */
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#ifdef CONFIG_OF_HAS_BD_T
|
||||
static int fdt_bd_t(void *fdt)
|
||||
{
|
||||
bd_t *bd = gd->bd;
|
||||
int nodeoffset;
|
||||
int err;
|
||||
u32 tmp; /* used to set 32 bit integer properties */
|
||||
int i;
|
||||
|
||||
/*
|
||||
* See if we already have a "bd_t" node, delete it if so.
|
||||
* Then create a new empty node.
|
||||
*/
|
||||
nodeoffset = fdt_path_offset (fdt, "/bd_t");
|
||||
if (nodeoffset >= 0) {
|
||||
err = fdt_del_node(fdt, nodeoffset);
|
||||
if (err < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
}
|
||||
/*
|
||||
* Create a new node "/bd_t" (offset 0 is root level)
|
||||
*/
|
||||
nodeoffset = fdt_add_subnode(fdt, 0, "bd_t");
|
||||
if (nodeoffset < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(nodeoffset));
|
||||
return nodeoffset;
|
||||
}
|
||||
/*
|
||||
* Use the string/pointer structure to create the entries...
|
||||
*/
|
||||
for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) {
|
||||
tmp = cpu_to_be32(getenv("bootargs"));
|
||||
err = fdt_setprop(fdt, nodeoffset, bd_map[i].name, &tmp, sizeof(tmp));
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
}
|
||||
/*
|
||||
* Add a couple of oddball entries...
|
||||
*/
|
||||
err = fdt_setprop(fdt, nodeoffset, "enetaddr", &bd->bi_enetaddr, 6);
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
err = fdt_setprop(fdt, nodeoffset, "ethspeed", &bd->bi_ethspeed, 4);
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
ft_board_setup(fdt, bd);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_OF_HAS_BD_T */
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
U_BOOT_CMD(
|
||||
fdt, 5, 0, do_fdt,
|
||||
"fdt - flattened device tree utility commands\n",
|
||||
|
@ -871,4 +632,4 @@ U_BOOT_CMD(
|
|||
" fdt set /cpus \"#address-cells\" \"[00 00 00 01]\"\n"
|
||||
);
|
||||
|
||||
#endif /* CONFIG_OF_FLAT_TREE */
|
||||
#endif /* CONFIG_OF_LIBFDT */
|
||||
|
|
|
@ -0,0 +1,347 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#ifdef CONFIG_OF_LIBFDT
|
||||
|
||||
#include <asm/global_data.h>
|
||||
#include <fdt.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
|
||||
/*
|
||||
* Global data (for the gd->bd)
|
||||
*/
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
int fdt_chosen(void *fdt, ulong initrd_start, ulong initrd_end, int force)
|
||||
{
|
||||
bd_t *bd = gd->bd;
|
||||
int nodeoffset;
|
||||
int err;
|
||||
u32 tmp; /* used to set 32 bit integer properties */
|
||||
char *str; /* used to set string properties */
|
||||
ulong clock;
|
||||
|
||||
err = fdt_check_header(fdt);
|
||||
if (err < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
|
||||
if (initrd_start && initrd_end) {
|
||||
struct fdt_reserve_entry re;
|
||||
int used;
|
||||
int total;
|
||||
int j;
|
||||
|
||||
err = fdt_num_reservemap(fdt, &used, &total);
|
||||
if (err < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
if (used >= total) {
|
||||
printf("fdt_chosen: no room in the reserved map (%d of %d)\n",
|
||||
used, total);
|
||||
return -1;
|
||||
}
|
||||
/*
|
||||
* Look for an existing entry and update it. If we don't find
|
||||
* the entry, we will j be the next available slot.
|
||||
*/
|
||||
for (j = 0; j < used; j++) {
|
||||
err = fdt_get_reservemap(fdt, j, &re);
|
||||
if (re.address == initrd_start) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
err = fdt_replace_reservemap_entry(fdt, j,
|
||||
initrd_start, initrd_end - initrd_start + 1);
|
||||
if (err < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Find the "chosen" node.
|
||||
*/
|
||||
nodeoffset = fdt_path_offset (fdt, "/chosen");
|
||||
|
||||
/*
|
||||
* If we have a "chosen" node already the "force the writing"
|
||||
* is not set, our job is done.
|
||||
*/
|
||||
if ((nodeoffset >= 0) && !force)
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* No "chosen" node in the blob: create it.
|
||||
*/
|
||||
if (nodeoffset < 0) {
|
||||
/*
|
||||
* Create a new node "/chosen" (offset 0 is root level)
|
||||
*/
|
||||
nodeoffset = fdt_add_subnode(fdt, 0, "chosen");
|
||||
if (nodeoffset < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(nodeoffset));
|
||||
return nodeoffset;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Update pre-existing properties, create them if non-existant.
|
||||
*/
|
||||
str = getenv("bootargs");
|
||||
if (str != NULL) {
|
||||
err = fdt_setprop(fdt, nodeoffset, "bootargs", str, strlen(str)+1);
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
}
|
||||
if (initrd_start && initrd_end) {
|
||||
tmp = __cpu_to_be32(initrd_start);
|
||||
err = fdt_setprop(fdt, nodeoffset, "linux,initrd-start", &tmp, sizeof(tmp));
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
tmp = __cpu_to_be32(initrd_end);
|
||||
err = fdt_setprop(fdt, nodeoffset, "linux,initrd-end", &tmp, sizeof(tmp));
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
}
|
||||
#ifdef OF_STDOUT_PATH
|
||||
err = fdt_setprop(fdt, nodeoffset, "linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1);
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
#endif
|
||||
|
||||
nodeoffset = fdt_path_offset (fdt, "/cpus");
|
||||
if (nodeoffset >= 0) {
|
||||
clock = cpu_to_be32(bd->bi_intfreq);
|
||||
err = fdt_setprop(fdt, nodeoffset, "clock-frequency", &clock, 4);
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
}
|
||||
#ifdef OF_TBCLK
|
||||
nodeoffset = fdt_path_offset (fdt, "/cpus/" OF_CPU "/timebase-frequency");
|
||||
if (nodeoffset >= 0) {
|
||||
clock = cpu_to_be32(OF_TBCLK);
|
||||
err = fdt_setprop(fdt, nodeoffset, "clock-frequency", &clock, 4);
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
}
|
||||
#endif
|
||||
return err;
|
||||
}
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#ifdef CONFIG_OF_HAS_UBOOT_ENV
|
||||
|
||||
/* Function that returns a character from the environment */
|
||||
extern uchar(*env_get_char) (int);
|
||||
|
||||
|
||||
int fdt_env(void *fdt)
|
||||
{
|
||||
int nodeoffset;
|
||||
int err;
|
||||
int k, nxt;
|
||||
int i;
|
||||
static char tmpenv[256];
|
||||
|
||||
err = fdt_check_header(fdt);
|
||||
if (err < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* See if we already have a "u-boot-env" node, delete it if so.
|
||||
* Then create a new empty node.
|
||||
*/
|
||||
nodeoffset = fdt_path_offset (fdt, "/u-boot-env");
|
||||
if (nodeoffset >= 0) {
|
||||
err = fdt_del_node(fdt, nodeoffset);
|
||||
if (err < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
}
|
||||
/*
|
||||
* Create a new node "/u-boot-env" (offset 0 is root level)
|
||||
*/
|
||||
nodeoffset = fdt_add_subnode(fdt, 0, "u-boot-env");
|
||||
if (nodeoffset < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(nodeoffset));
|
||||
return nodeoffset;
|
||||
}
|
||||
|
||||
for (i = 0; env_get_char(i) != '\0'; i = nxt + 1) {
|
||||
char *s, *lval, *rval;
|
||||
|
||||
/*
|
||||
* Find the end of the name=definition
|
||||
*/
|
||||
for (nxt = i; env_get_char(nxt) != '\0'; ++nxt)
|
||||
;
|
||||
s = tmpenv;
|
||||
for (k = i; k < nxt && s < &tmpenv[sizeof(tmpenv) - 1]; ++k)
|
||||
*s++ = env_get_char(k);
|
||||
*s++ = '\0';
|
||||
lval = tmpenv;
|
||||
/*
|
||||
* Find the first '=': it separates the name from the value
|
||||
*/
|
||||
s = strchr(tmpenv, '=');
|
||||
if (s != NULL) {
|
||||
*s++ = '\0';
|
||||
rval = s;
|
||||
} else
|
||||
continue;
|
||||
err = fdt_setprop(fdt, nodeoffset, lval, rval, strlen(rval)+1);
|
||||
if (err < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif /* ifdef CONFIG_OF_HAS_UBOOT_ENV */
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#ifdef CONFIG_OF_HAS_BD_T
|
||||
|
||||
#define BDM(x) { .name = #x, .offset = offsetof(bd_t, bi_ ##x ) }
|
||||
|
||||
static const struct {
|
||||
const char *name;
|
||||
int offset;
|
||||
} bd_map[] = {
|
||||
BDM(memstart),
|
||||
BDM(memsize),
|
||||
BDM(flashstart),
|
||||
BDM(flashsize),
|
||||
BDM(flashoffset),
|
||||
BDM(sramstart),
|
||||
BDM(sramsize),
|
||||
#if defined(CONFIG_5xx) || defined(CONFIG_8xx) || defined(CONFIG_8260) \
|
||||
|| defined(CONFIG_E500)
|
||||
BDM(immr_base),
|
||||
#endif
|
||||
#if defined(CONFIG_MPC5xxx)
|
||||
BDM(mbar_base),
|
||||
#endif
|
||||
#if defined(CONFIG_MPC83XX)
|
||||
BDM(immrbar),
|
||||
#endif
|
||||
#if defined(CONFIG_MPC8220)
|
||||
BDM(mbar_base),
|
||||
BDM(inpfreq),
|
||||
BDM(pcifreq),
|
||||
BDM(pevfreq),
|
||||
BDM(flbfreq),
|
||||
BDM(vcofreq),
|
||||
#endif
|
||||
BDM(bootflags),
|
||||
BDM(ip_addr),
|
||||
BDM(intfreq),
|
||||
BDM(busfreq),
|
||||
#ifdef CONFIG_CPM2
|
||||
BDM(cpmfreq),
|
||||
BDM(brgfreq),
|
||||
BDM(sccfreq),
|
||||
BDM(vco),
|
||||
#endif
|
||||
#if defined(CONFIG_MPC5xxx)
|
||||
BDM(ipbfreq),
|
||||
BDM(pcifreq),
|
||||
#endif
|
||||
BDM(baudrate),
|
||||
};
|
||||
|
||||
|
||||
int fdt_bd_t(void *fdt)
|
||||
{
|
||||
bd_t *bd = gd->bd;
|
||||
int nodeoffset;
|
||||
int err;
|
||||
u32 tmp; /* used to set 32 bit integer properties */
|
||||
int i;
|
||||
|
||||
err = fdt_check_header(fdt);
|
||||
if (err < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* See if we already have a "bd_t" node, delete it if so.
|
||||
* Then create a new empty node.
|
||||
*/
|
||||
nodeoffset = fdt_path_offset (fdt, "/bd_t");
|
||||
if (nodeoffset >= 0) {
|
||||
err = fdt_del_node(fdt, nodeoffset);
|
||||
if (err < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
}
|
||||
/*
|
||||
* Create a new node "/bd_t" (offset 0 is root level)
|
||||
*/
|
||||
nodeoffset = fdt_add_subnode(fdt, 0, "bd_t");
|
||||
if (nodeoffset < 0) {
|
||||
printf("libfdt: %s\n", fdt_strerror(nodeoffset));
|
||||
return nodeoffset;
|
||||
}
|
||||
/*
|
||||
* Use the string/pointer structure to create the entries...
|
||||
*/
|
||||
for (i = 0; i < sizeof(bd_map)/sizeof(bd_map[0]); i++) {
|
||||
tmp = cpu_to_be32(getenv("bootargs"));
|
||||
err = fdt_setprop(fdt, nodeoffset, bd_map[i].name, &tmp, sizeof(tmp));
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
}
|
||||
/*
|
||||
* Add a couple of oddball entries...
|
||||
*/
|
||||
err = fdt_setprop(fdt, nodeoffset, "enetaddr", &bd->bi_enetaddr, 6);
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
err = fdt_setprop(fdt, nodeoffset, "ethspeed", &bd->bi_ethspeed, 4);
|
||||
if (err < 0)
|
||||
printf("libfdt: %s\n", fdt_strerror(err));
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* ifdef CONFIG_OF_HAS_BD_T */
|
||||
|
||||
#endif /* CONFIG_OF_LIBFDT */
|
|
@ -44,6 +44,10 @@
|
|||
#include <74xx_7xx.h>
|
||||
#include <asm/cache.h>
|
||||
|
||||
#if defined(CONFIG_OF_FLAT_TREE)
|
||||
#include <ft_build.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_AMIGAONEG3SE
|
||||
#include "../board/MAI/AmigaOneG3SE/via686.h"
|
||||
#include "../board/MAI/AmigaOneG3SE/memio.h"
|
||||
|
@ -101,6 +105,10 @@ get_cpu_type(void)
|
|||
type = CPU_7457;
|
||||
break;
|
||||
|
||||
case 0x8003:
|
||||
type = CPU_7447A;
|
||||
break;
|
||||
|
||||
case 0x8004:
|
||||
type = CPU_7448;
|
||||
break;
|
||||
|
@ -156,6 +164,10 @@ int checkcpu (void)
|
|||
str = "MPC7410";
|
||||
break;
|
||||
|
||||
case CPU_7447A:
|
||||
str = "MPC7447A";
|
||||
break;
|
||||
|
||||
case CPU_7448:
|
||||
str = "MPC7448";
|
||||
break;
|
||||
|
@ -264,20 +276,19 @@ do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
|||
/*
|
||||
* For the 7400 the TB clock runs at 1/4 the cpu bus speed.
|
||||
*/
|
||||
#ifdef CONFIG_AMIGAONEG3SE
|
||||
#if defined(CONFIG_AMIGAONEG3SE) || defined(CFG_CONFIG_BUS_CLK)
|
||||
unsigned long get_tbclk(void)
|
||||
{
|
||||
return (gd->bus_clk / 4);
|
||||
}
|
||||
#else /* ! CONFIG_AMIGAONEG3SE */
|
||||
#else /* ! CONFIG_AMIGAONEG3SE and !CFG_CONFIG_BUS_CLK*/
|
||||
|
||||
unsigned long get_tbclk (void)
|
||||
{
|
||||
return CFG_BUS_HZ / 4;
|
||||
}
|
||||
#endif /* CONFIG_AMIGAONEG3SE */
|
||||
#endif /* CONFIG_AMIGAONEG3SE or CFG_CONFIG_BUS_CLK*/
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#if defined(CONFIG_WATCHDOG)
|
||||
#if !defined(CONFIG_PCIPPC2) && !defined(CONFIG_BAB7xx)
|
||||
void
|
||||
|
@ -289,3 +300,30 @@ watchdog_reset(void)
|
|||
#endif /* CONFIG_WATCHDOG */
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
#ifdef CONFIG_OF_FLAT_TREE
|
||||
void
|
||||
ft_cpu_setup (void *blob, bd_t *bd)
|
||||
{
|
||||
u32 *p;
|
||||
ulong clock;
|
||||
int len;
|
||||
|
||||
clock = bd->bi_busfreq;
|
||||
|
||||
p = ft_get_prop (blob, "/cpus/" OF_CPU "/bus-frequency", &len);
|
||||
if (p != NULL)
|
||||
*p = cpu_to_be32 (clock);
|
||||
|
||||
#if defined(CONFIG_TSI108_ETH)
|
||||
p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6200/address", &len);
|
||||
memcpy (p, bd->bi_enetaddr, 6);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_HAS_ETH1)
|
||||
p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6600/address", &len);
|
||||
memcpy (p, bd->bi_enet1addr, 6);
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
|
|
@ -43,6 +43,7 @@ cpu_init_f (void)
|
|||
case CPU_7450:
|
||||
case CPU_7455:
|
||||
case CPU_7457:
|
||||
case CPU_7447A:
|
||||
case CPU_7448:
|
||||
/* enable the timebase bit in HID0 */
|
||||
set_hid0(get_hid0() | 0x4000000);
|
||||
|
|
|
@ -31,6 +31,8 @@
|
|||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
extern unsigned long get_board_bus_clk (void);
|
||||
|
||||
static const int hid1_multipliers_x_10[] = {
|
||||
25, /* 0000 - 2.5x */
|
||||
75, /* 0001 - 7.5x */
|
||||
|
@ -50,6 +52,42 @@ static const int hid1_multipliers_x_10[] = {
|
|||
0 /* 1111 - off */
|
||||
};
|
||||
|
||||
/* PLL_CFG[0:4] table for cpu 7448/7447A/7455/7457 */
|
||||
static const int hid1_74xx_multipliers_x_10[] = {
|
||||
115, /* 00000 - 11.5x */
|
||||
170, /* 00001 - 17x */
|
||||
75, /* 00010 - 7.5x */
|
||||
150, /* 00011 - 15x */
|
||||
70, /* 00100 - 7x */
|
||||
180, /* 00101 - 18x */
|
||||
10, /* 00110 - bypass */
|
||||
200, /* 00111 - 20x */
|
||||
20, /* 01000 - 2x */
|
||||
210, /* 01001 - 21x */
|
||||
65, /* 01010 - 6.5x */
|
||||
130, /* 01011 - 13x */
|
||||
85, /* 01100 - 8.5x */
|
||||
240, /* 01101 - 24x */
|
||||
95, /* 01110 - 9.5x */
|
||||
90, /* 01111 - 9x */
|
||||
30, /* 10000 - 3x */
|
||||
105, /* 10001 - 10.5x */
|
||||
55, /* 10010 - 5.5x */
|
||||
110, /* 10011 - 11x */
|
||||
40, /* 10100 - 4x */
|
||||
100, /* 10101 - 10x */
|
||||
50, /* 10110 - 5x */
|
||||
120, /* 10111 - 12x */
|
||||
80, /* 11000 - 8x */
|
||||
140, /* 11001 - 14x */
|
||||
60, /* 11010 - 6x */
|
||||
160, /* 11011 - 16x */
|
||||
135, /* 11100 - 13.5x */
|
||||
280, /* 11101 - 28x */
|
||||
0, /* 11110 - off */
|
||||
125 /* 11111 - 12.5x */
|
||||
};
|
||||
|
||||
static const int hid1_fx_multipliers_x_10[] = {
|
||||
00, /* 0000 - off */
|
||||
00, /* 0001 - off */
|
||||
|
@ -89,22 +127,30 @@ int get_clocks (void)
|
|||
{
|
||||
ulong clock = 0;
|
||||
|
||||
#ifdef CFG_BUS_CLK
|
||||
gd->bus_clk = CFG_BUS_CLK; /* bus clock is a fixed frequency */
|
||||
#else
|
||||
gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */
|
||||
#endif
|
||||
|
||||
/* calculate the clock frequency based upon the CPU type */
|
||||
switch (get_cpu_type()) {
|
||||
case CPU_7447A:
|
||||
case CPU_7448:
|
||||
case CPU_7455:
|
||||
case CPU_7457:
|
||||
/*
|
||||
* It is assumed that the PLL_EXT line is zero.
|
||||
* Make sure division is done before multiplication to prevent 32-bit
|
||||
* arithmetic overflows which will cause a negative number
|
||||
*/
|
||||
clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF];
|
||||
clock = (gd->bus_clk / 10) *
|
||||
hid1_74xx_multipliers_x_10[(get_hid1 () >> 12) & 0x1F];
|
||||
break;
|
||||
|
||||
case CPU_750GX:
|
||||
case CPU_750FX:
|
||||
clock = CFG_BUS_CLK * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
|
||||
clock = gd->bus_clk *
|
||||
hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
|
||||
break;
|
||||
|
||||
case CPU_7450:
|
||||
|
@ -121,7 +167,8 @@ int get_clocks (void)
|
|||
* Make sure division is done before multiplication to prevent 32-bit
|
||||
* arithmetic overflows which will cause a negative number
|
||||
*/
|
||||
clock = (CFG_BUS_CLK / 10) * hid1_multipliers_x_10[get_hid1 () >> 28];
|
||||
clock = (gd->bus_clk / 10) *
|
||||
hid1_multipliers_x_10[get_hid1 () >> 28];
|
||||
break;
|
||||
|
||||
case CPU_UNKNOWN:
|
||||
|
@ -131,7 +178,6 @@ int get_clocks (void)
|
|||
}
|
||||
|
||||
gd->cpu_clk = clock;
|
||||
gd->bus_clk = CFG_BUS_CLK;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
|
|
@ -30,7 +30,7 @@ LIB := $(obj)lib$(CPU).a
|
|||
START := start.o
|
||||
SOBJS := entry.o
|
||||
COBJS := cpu.o hsdramc.o exception.o cache.o
|
||||
COBJS += interrupts.o device.o pm.o pio.o
|
||||
COBJS += interrupts.o pio.o atmel_mci.o
|
||||
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
START := $(addprefix $(obj),$(START))
|
||||
|
|
|
@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
|
|||
|
||||
LIB := $(obj)lib$(SOC).a
|
||||
|
||||
COBJS := hebi.o devices.o
|
||||
COBJS := gpio.o
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
||||
|
|
|
@ -1,448 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2006 Atmel Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
|
||||
#include <asm/arch/memory-map.h>
|
||||
#include <asm/arch/platform.h>
|
||||
|
||||
#include "../sm.h"
|
||||
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
|
||||
const struct clock_domain chip_clock[] = {
|
||||
[CLOCK_CPU] = {
|
||||
.reg = SM_PM_CPU_MASK,
|
||||
.id = CLOCK_CPU,
|
||||
.bridge = NO_DEVICE,
|
||||
},
|
||||
[CLOCK_HSB] = {
|
||||
.reg = SM_PM_HSB_MASK,
|
||||
.id = CLOCK_HSB,
|
||||
.bridge = NO_DEVICE,
|
||||
},
|
||||
[CLOCK_PBA] = {
|
||||
.reg = SM_PM_PBA_MASK,
|
||||
.id = CLOCK_PBA,
|
||||
.bridge = DEVICE_PBA_BRIDGE,
|
||||
},
|
||||
[CLOCK_PBB] = {
|
||||
.reg = SM_PM_PBB_MASK,
|
||||
.id = CLOCK_PBB,
|
||||
.bridge = DEVICE_PBB_BRIDGE,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct resource hebi_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_HSB, 0 },
|
||||
},
|
||||
}, {
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBB, 13 },
|
||||
},
|
||||
}, {
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBB, 14 },
|
||||
},
|
||||
}, {
|
||||
.type = RESOURCE_GPIO,
|
||||
.u = {
|
||||
.gpio = { 27, DEVICE_PIOE, GPIO_FUNC_A, 0 },
|
||||
},
|
||||
},
|
||||
};
|
||||
static const struct resource pba_bridge_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_HSB, 1 },
|
||||
}
|
||||
}, {
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
/* HSB-HSB Bridge */
|
||||
.clock = { CLOCK_HSB, 4 },
|
||||
},
|
||||
},
|
||||
};
|
||||
static const struct resource pbb_bridge_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_HSB, 2 },
|
||||
},
|
||||
},
|
||||
};
|
||||
static const struct resource hramc_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_HSB, 3 },
|
||||
},
|
||||
},
|
||||
};
|
||||
static const struct resource pioa_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBA, 10 },
|
||||
},
|
||||
},
|
||||
};
|
||||
static const struct resource piob_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBA, 11 },
|
||||
},
|
||||
},
|
||||
};
|
||||
static const struct resource pioc_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBA, 12 },
|
||||
},
|
||||
},
|
||||
};
|
||||
static const struct resource piod_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBA, 13 },
|
||||
},
|
||||
},
|
||||
};
|
||||
static const struct resource pioe_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBA, 14 },
|
||||
},
|
||||
},
|
||||
};
|
||||
static const struct resource sm_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBB, 0 },
|
||||
},
|
||||
},
|
||||
};
|
||||
static const struct resource intc_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBB, 1 },
|
||||
},
|
||||
},
|
||||
};
|
||||
static const struct resource hmatrix_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBB, 2 },
|
||||
},
|
||||
},
|
||||
};
|
||||
#if defined(CFG_HPDC)
|
||||
static const struct resource hpdc_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBA, 16 },
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#if defined(CFG_MACB0)
|
||||
static const struct resource macb0_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_HSB, 8 },
|
||||
},
|
||||
}, {
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBB, 6 },
|
||||
},
|
||||
}, {
|
||||
.type = RESOURCE_GPIO,
|
||||
.u = {
|
||||
.gpio = { 19, DEVICE_PIOC, GPIO_FUNC_A, 0 },
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#if defined(CFG_MACB1)
|
||||
static const struct resource macb1_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_HSB, 9 },
|
||||
},
|
||||
}, {
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBB, 7 },
|
||||
},
|
||||
}, {
|
||||
.type = RESOURCE_GPIO,
|
||||
.u = {
|
||||
.gpio = { 12, DEVICE_PIOC, GPIO_FUNC_B, 19 },
|
||||
},
|
||||
}, {
|
||||
.type = RESOURCE_GPIO,
|
||||
.u = {
|
||||
.gpio = { 14, DEVICE_PIOD, GPIO_FUNC_B, 2 },
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#if defined(CFG_LCDC)
|
||||
static const struct resource lcdc_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_HSB, 7 },
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#if defined(CFG_USART0)
|
||||
static const struct resource usart0_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBA, 3 },
|
||||
},
|
||||
}, {
|
||||
.type = RESOURCE_GPIO,
|
||||
.u = {
|
||||
.gpio = { 2, DEVICE_PIOA, GPIO_FUNC_B, 8 },
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#if defined(CFG_USART1)
|
||||
static const struct resource usart1_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBA, 4 },
|
||||
},
|
||||
}, {
|
||||
.type = RESOURCE_GPIO,
|
||||
.u = {
|
||||
.gpio = { 2, DEVICE_PIOA, GPIO_FUNC_A, 17 },
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#if defined(CFG_USART2)
|
||||
static const struct resource usart2_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBA, 5 },
|
||||
},
|
||||
}, {
|
||||
.type = RESOURCE_GPIO,
|
||||
.u = {
|
||||
.gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 26 },
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#if defined(CFG_USART3)
|
||||
static const struct resource usart3_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBA, 6 },
|
||||
},
|
||||
}, {
|
||||
.type = RESOURCE_GPIO,
|
||||
.u = {
|
||||
.gpio = { 2, DEVICE_PIOB, GPIO_FUNC_B, 17 },
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#if defined(CFG_MMCI)
|
||||
static const struct resource mmci_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_PBB, 9 },
|
||||
},
|
||||
}, {
|
||||
.type = RESOURCE_GPIO,
|
||||
.u = {
|
||||
.gpio = { 6, DEVICE_PIOA, GPIO_FUNC_A, 10 },
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#if defined(CFG_DMAC)
|
||||
static const struct resource dmac_resource[] = {
|
||||
{
|
||||
.type = RESOURCE_CLOCK,
|
||||
.u = {
|
||||
.clock = { CLOCK_HSB, 10 },
|
||||
},
|
||||
},
|
||||
};
|
||||
#endif
|
||||
|
||||
const struct device chip_device[] = {
|
||||
[DEVICE_HEBI] = {
|
||||
.regs = (void *)HSMC_BASE,
|
||||
.nr_resources = ARRAY_SIZE(hebi_resource),
|
||||
.resource = hebi_resource,
|
||||
},
|
||||
[DEVICE_PBA_BRIDGE] = {
|
||||
.nr_resources = ARRAY_SIZE(pba_bridge_resource),
|
||||
.resource = pba_bridge_resource,
|
||||
},
|
||||
[DEVICE_PBB_BRIDGE] = {
|
||||
.nr_resources = ARRAY_SIZE(pbb_bridge_resource),
|
||||
.resource = pbb_bridge_resource,
|
||||
},
|
||||
[DEVICE_HRAMC] = {
|
||||
.nr_resources = ARRAY_SIZE(hramc_resource),
|
||||
.resource = hramc_resource,
|
||||
},
|
||||
[DEVICE_PIOA] = {
|
||||
.regs = (void *)PIOA_BASE,
|
||||
.nr_resources = ARRAY_SIZE(pioa_resource),
|
||||
.resource = pioa_resource,
|
||||
},
|
||||
[DEVICE_PIOB] = {
|
||||
.regs = (void *)PIOB_BASE,
|
||||
.nr_resources = ARRAY_SIZE(piob_resource),
|
||||
.resource = piob_resource,
|
||||
},
|
||||
[DEVICE_PIOC] = {
|
||||
.regs = (void *)PIOC_BASE,
|
||||
.nr_resources = ARRAY_SIZE(pioc_resource),
|
||||
.resource = pioc_resource,
|
||||
},
|
||||
[DEVICE_PIOD] = {
|
||||
.regs = (void *)PIOD_BASE,
|
||||
.nr_resources = ARRAY_SIZE(piod_resource),
|
||||
.resource = piod_resource,
|
||||
},
|
||||
[DEVICE_PIOE] = {
|
||||
.regs = (void *)PIOE_BASE,
|
||||
.nr_resources = ARRAY_SIZE(pioe_resource),
|
||||
.resource = pioe_resource,
|
||||
},
|
||||
[DEVICE_SM] = {
|
||||
.regs = (void *)SM_BASE,
|
||||
.nr_resources = ARRAY_SIZE(sm_resource),
|
||||
.resource = sm_resource,
|
||||
},
|
||||
[DEVICE_INTC] = {
|
||||
.regs = (void *)INTC_BASE,
|
||||
.nr_resources = ARRAY_SIZE(intc_resource),
|
||||
.resource = intc_resource,
|
||||
},
|
||||
[DEVICE_HMATRIX] = {
|
||||
.regs = (void *)HMATRIX_BASE,
|
||||
.nr_resources = ARRAY_SIZE(hmatrix_resource),
|
||||
.resource = hmatrix_resource,
|
||||
},
|
||||
#if defined(CFG_HPDC)
|
||||
[DEVICE_HPDC] = {
|
||||
.nr_resources = ARRAY_SIZE(hpdc_resource),
|
||||
.resource = hpdc_resource,
|
||||
},
|
||||
#endif
|
||||
#if defined(CFG_MACB0)
|
||||
[DEVICE_MACB0] = {
|
||||
.regs = (void *)MACB0_BASE,
|
||||
.nr_resources = ARRAY_SIZE(macb0_resource),
|
||||
.resource = macb0_resource,
|
||||
},
|
||||
#endif
|
||||
#if defined(CFG_MACB1)
|
||||
[DEVICE_MACB1] = {
|
||||
.regs = (void *)MACB1_BASE,
|
||||
.nr_resources = ARRAY_SIZE(macb1_resource),
|
||||
.resource = macb1_resource,
|
||||
},
|
||||
#endif
|
||||
#if defined(CFG_LCDC)
|
||||
[DEVICE_LCDC] = {
|
||||
.nr_resources = ARRAY_SIZE(lcdc_resource),
|
||||
.resource = lcdc_resource,
|
||||
},
|
||||
#endif
|
||||
#if defined(CFG_USART0)
|
||||
[DEVICE_USART0] = {
|
||||
.regs = (void *)USART0_BASE,
|
||||
.nr_resources = ARRAY_SIZE(usart0_resource),
|
||||
.resource = usart0_resource,
|
||||
},
|
||||
#endif
|
||||
#if defined(CFG_USART1)
|
||||
[DEVICE_USART1] = {
|
||||
.regs = (void *)USART1_BASE,
|
||||
.nr_resources = ARRAY_SIZE(usart1_resource),
|
||||
.resource = usart1_resource,
|
||||
},
|
||||
#endif
|
||||
#if defined(CFG_USART2)
|
||||
[DEVICE_USART2] = {
|
||||
.regs = (void *)USART2_BASE,
|
||||
.nr_resources = ARRAY_SIZE(usart2_resource),
|
||||
.resource = usart2_resource,
|
||||
},
|
||||
#endif
|
||||
#if defined(CFG_USART3)
|
||||
[DEVICE_USART3] = {
|
||||
.regs = (void *)USART3_BASE,
|
||||
.nr_resources = ARRAY_SIZE(usart3_resource),
|
||||
.resource = usart3_resource,
|
||||
},
|
||||
#endif
|
||||
#if defined(CFG_MMCI)
|
||||
[DEVICE_MMCI] = {
|
||||
.regs = (void *)MMCI_BASE,
|
||||
.nr_resources = ARRAY_SIZE(mmci_resource),
|
||||
.resource = mmci_resource,
|
||||
},
|
||||
#endif
|
||||
#if defined(CFG_DMAC)
|
||||
[DEVICE_DMAC] = {
|
||||
.regs = (void *)DMAC_BASE,
|
||||
.nr_resources = ARRAY_SIZE(dmac_resource),
|
||||
.resource = dmac_resource,
|
||||
},
|
||||
#endif
|
||||
};
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* Copyright (C) 2006 Atmel Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
|
||||
#include <asm/arch/gpio.h>
|
||||
|
||||
/*
|
||||
* Lots of small functions here. We depend on --gc-sections getting
|
||||
* rid of the ones we don't need.
|
||||
*/
|
||||
void gpio_enable_ebi(void)
|
||||
{
|
||||
#ifdef CFG_HSDRAMC
|
||||
#ifndef CFG_SDRAM_16BIT
|
||||
gpio_select_periph_A(GPIO_PIN_PE0, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE1, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE2, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE3, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE4, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE5, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE6, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE7, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE8, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE9, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE10, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE11, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE12, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE13, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE14, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PE15, 0);
|
||||
#endif
|
||||
gpio_select_periph_A(GPIO_PIN_PE26, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void gpio_enable_usart0(void)
|
||||
{
|
||||
gpio_select_periph_B(GPIO_PIN_PA8, 0);
|
||||
gpio_select_periph_B(GPIO_PIN_PA9, 0);
|
||||
}
|
||||
|
||||
void gpio_enable_usart1(void)
|
||||
{
|
||||
gpio_select_periph_A(GPIO_PIN_PA17, 0);
|
||||
gpio_select_periph_A(GPIO_PIN_PA18, 0);
|
||||
}
|
||||
|
||||
void gpio_enable_usart2(void)
|
||||
{
|
||||
gpio_select_periph_B(GPIO_PIN_PB26, 0);
|
||||
gpio_select_periph_B(GPIO_PIN_PB27, 0);
|
||||
}
|
||||
|
||||
void gpio_enable_usart3(void)
|
||||
{
|
||||
gpio_select_periph_B(GPIO_PIN_PB18, 0);
|
||||
gpio_select_periph_B(GPIO_PIN_PB19, 0);
|
||||
}
|
||||
|
||||
void gpio_enable_macb0(void)
|
||||
{
|
||||
gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */
|
||||
gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */
|
||||
gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */
|
||||
gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */
|
||||
gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */
|
||||
gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */
|
||||
gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */
|
||||
gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */
|
||||
gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */
|
||||
gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */
|
||||
#if !defined(CONFIG_RMII)
|
||||
gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */
|
||||
gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */
|
||||
gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */
|
||||
gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */
|
||||
gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */
|
||||
gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */
|
||||
gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */
|
||||
gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */
|
||||
gpio_select_periph_A(GPIO_PIN_PC18, 0); /* SPD */
|
||||
#endif
|
||||
}
|
||||
|
||||
void gpio_enable_macb1(void)
|
||||
{
|
||||
gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */
|
||||
gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */
|
||||
gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */
|
||||
gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */
|
||||
gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */
|
||||
gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */
|
||||
gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */
|
||||
gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */
|
||||
gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */
|
||||
gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */
|
||||
#if !defined(CONFIG_RMII)
|
||||
gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */
|
||||
gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */
|
||||
gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */
|
||||
gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */
|
||||
gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */
|
||||
gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */
|
||||
gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */
|
||||
gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */
|
||||
gpio_select_periph_B(GPIO_PIN_PD15, 0); /* SPD */
|
||||
#endif
|
||||
}
|
||||
|
||||
void gpio_enable_mmci(void)
|
||||
{
|
||||
gpio_select_periph_A(GPIO_PIN_PA10, 0); /* CLK */
|
||||
gpio_select_periph_A(GPIO_PIN_PA11, 0); /* CMD */
|
||||
gpio_select_periph_A(GPIO_PIN_PA12, 0); /* DATA0 */
|
||||
gpio_select_periph_A(GPIO_PIN_PA13, 0); /* DATA1 */
|
||||
gpio_select_periph_A(GPIO_PIN_PA14, 0); /* DATA2 */
|
||||
gpio_select_periph_A(GPIO_PIN_PA15, 0); /* DATA3 */
|
||||
}
|
|
@ -0,0 +1,477 @@
|
|||
/*
|
||||
* Copyright (C) 2004-2006 Atmel Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
|
||||
#include <part.h>
|
||||
#include <mmc.h>
|
||||
|
||||
#include <asm/io.h>
|
||||
#include <asm/errno.h>
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#include <asm/arch/memory-map.h>
|
||||
|
||||
#include "atmel_mci.h"
|
||||
|
||||
#ifdef DEBUG
|
||||
#define pr_debug(fmt, args...) printf(fmt, ##args)
|
||||
#else
|
||||
#define pr_debug(...) do { } while(0)
|
||||
#endif
|
||||
|
||||
#ifndef CFG_MMC_CLK_OD
|
||||
#define CFG_MMC_CLK_OD 150000
|
||||
#endif
|
||||
|
||||
#ifndef CFG_MMC_CLK_PP
|
||||
#define CFG_MMC_CLK_PP 5000000
|
||||
#endif
|
||||
|
||||
#ifndef CFG_MMC_OP_COND
|
||||
#define CFG_MMC_OP_COND 0x00100000
|
||||
#endif
|
||||
|
||||
#define MMC_DEFAULT_BLKLEN 512
|
||||
#define MMC_DEFAULT_RCA 1
|
||||
|
||||
static unsigned int mmc_rca;
|
||||
static block_dev_desc_t mmc_blkdev;
|
||||
|
||||
block_dev_desc_t *mmc_get_dev(int dev)
|
||||
{
|
||||
return &mmc_blkdev;
|
||||
}
|
||||
|
||||
static void mci_set_mode(unsigned long hz, unsigned long blklen)
|
||||
{
|
||||
unsigned long bus_hz;
|
||||
unsigned long clkdiv;
|
||||
|
||||
bus_hz = get_mci_clk_rate();
|
||||
clkdiv = (bus_hz / hz) / 2 - 1;
|
||||
|
||||
pr_debug("mmc: setting clock %lu Hz, block size %lu\n",
|
||||
hz, blklen);
|
||||
|
||||
if (clkdiv & ~255UL) {
|
||||
clkdiv = 255;
|
||||
printf("mmc: clock %lu too low; setting CLKDIV to 255\n",
|
||||
hz);
|
||||
}
|
||||
|
||||
blklen &= 0xfffc;
|
||||
mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv)
|
||||
| MMCI_BF(BLKLEN, blklen)));
|
||||
}
|
||||
|
||||
#define RESP_NO_CRC 1
|
||||
#define R1 MMCI_BF(RSPTYP, 1)
|
||||
#define R2 MMCI_BF(RSPTYP, 2)
|
||||
#define R3 (R1 | RESP_NO_CRC)
|
||||
#define R6 R1
|
||||
#define NID MMCI_BF(MAXLAT, 0)
|
||||
#define NCR MMCI_BF(MAXLAT, 1)
|
||||
#define TRCMD_START MMCI_BF(TRCMD, 1)
|
||||
#define TRDIR_READ MMCI_BF(TRDIR, 1)
|
||||
#define TRTYP_BLOCK MMCI_BF(TRTYP, 0)
|
||||
#define INIT_CMD MMCI_BF(SPCMD, 1)
|
||||
#define OPEN_DRAIN MMCI_BF(OPDCMD, 1)
|
||||
|
||||
#define ERROR_FLAGS (MMCI_BIT(DTOE) \
|
||||
| MMCI_BIT(RDIRE) \
|
||||
| MMCI_BIT(RENDE) \
|
||||
| MMCI_BIT(RINDE) \
|
||||
| MMCI_BIT(RTOE))
|
||||
|
||||
static int
|
||||
mmc_cmd(unsigned long cmd, unsigned long arg,
|
||||
void *resp, unsigned long flags)
|
||||
{
|
||||
unsigned long *response = resp;
|
||||
int i, response_words = 0;
|
||||
unsigned long error_flags;
|
||||
u32 status;
|
||||
|
||||
pr_debug("mmc: CMD%lu 0x%lx (flags 0x%lx)\n",
|
||||
cmd, arg, flags);
|
||||
|
||||
error_flags = ERROR_FLAGS;
|
||||
if (!(flags & RESP_NO_CRC))
|
||||
error_flags |= MMCI_BIT(RCRCE);
|
||||
|
||||
flags &= ~MMCI_BF(CMDNB, ~0UL);
|
||||
|
||||
if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_48_BIT_RESP)
|
||||
response_words = 1;
|
||||
else if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_136_BIT_RESP)
|
||||
response_words = 4;
|
||||
|
||||
mmci_writel(ARGR, arg);
|
||||
mmci_writel(CMDR, cmd | flags);
|
||||
do {
|
||||
udelay(40);
|
||||
status = mmci_readl(SR);
|
||||
} while (!(status & MMCI_BIT(CMDRDY)));
|
||||
|
||||
pr_debug("mmc: status 0x%08lx\n", status);
|
||||
|
||||
if (status & ERROR_FLAGS) {
|
||||
printf("mmc: command %lu failed (status: 0x%08lx)\n",
|
||||
cmd, status);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (response_words)
|
||||
pr_debug("mmc: response:");
|
||||
|
||||
for (i = 0; i < response_words; i++) {
|
||||
response[i] = mmci_readl(RSPR);
|
||||
pr_debug(" %08lx", response[i]);
|
||||
}
|
||||
pr_debug("\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mmc_acmd(unsigned long cmd, unsigned long arg,
|
||||
void *resp, unsigned long flags)
|
||||
{
|
||||
unsigned long aresp[4];
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* Seems like the APP_CMD part of an ACMD has 64 cycles max
|
||||
* latency even though the ACMD part doesn't. This isn't
|
||||
* entirely clear in the SD Card spec, but some cards refuse
|
||||
* to work if we attempt to use 5 cycles max latency here...
|
||||
*/
|
||||
ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp,
|
||||
R1 | NCR | (flags & OPEN_DRAIN));
|
||||
if (ret)
|
||||
return ret;
|
||||
if ((aresp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) != R1_APP_CMD)
|
||||
return -ENODEV;
|
||||
|
||||
ret = mmc_cmd(cmd, arg, resp, flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static unsigned long
|
||||
mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
|
||||
unsigned long *buffer)
|
||||
{
|
||||
int ret, i = 0;
|
||||
unsigned long resp[4];
|
||||
unsigned long card_status, data;
|
||||
unsigned long wordcount;
|
||||
u32 status;
|
||||
|
||||
if (blkcnt == 0)
|
||||
return 0;
|
||||
|
||||
pr_debug("mmc_bread: dev %d, start %lx, blkcnt %lx\n",
|
||||
dev, start, blkcnt);
|
||||
|
||||
/* Put the device into Transfer state */
|
||||
ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR);
|
||||
if (ret) goto fail;
|
||||
|
||||
/* Set block length */
|
||||
ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR);
|
||||
if (ret) goto fail;
|
||||
|
||||
pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR));
|
||||
|
||||
for (i = 0; i < blkcnt; i++, start++) {
|
||||
ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK,
|
||||
start * mmc_blkdev.blksz, resp,
|
||||
(R1 | NCR | TRCMD_START | TRDIR_READ
|
||||
| TRTYP_BLOCK));
|
||||
if (ret) goto fail;
|
||||
|
||||
ret = -EIO;
|
||||
wordcount = 0;
|
||||
do {
|
||||
do {
|
||||
status = mmci_readl(SR);
|
||||
if (status & (ERROR_FLAGS | MMCI_BIT(OVRE)))
|
||||
goto fail;
|
||||
} while (!(status & MMCI_BIT(RXRDY)));
|
||||
|
||||
if (status & MMCI_BIT(RXRDY)) {
|
||||
data = mmci_readl(RDR);
|
||||
/* pr_debug("%x\n", data); */
|
||||
*buffer++ = data;
|
||||
wordcount++;
|
||||
}
|
||||
} while(wordcount < (512 / 4));
|
||||
|
||||
pr_debug("mmc: read %u words, waiting for BLKE\n", wordcount);
|
||||
|
||||
do {
|
||||
status = mmci_readl(SR);
|
||||
} while (!(status & MMCI_BIT(BLKE)));
|
||||
|
||||
putc('.');
|
||||
}
|
||||
|
||||
out:
|
||||
/* Put the device back into Standby state */
|
||||
mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR);
|
||||
return i;
|
||||
|
||||
fail:
|
||||
mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR);
|
||||
printf("mmc: bread failed, card status = ", card_status);
|
||||
goto out;
|
||||
}
|
||||
|
||||
static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp)
|
||||
{
|
||||
cid->mid = resp[0] >> 24;
|
||||
cid->oid = (resp[0] >> 8) & 0xffff;
|
||||
cid->pnm[0] = resp[0];
|
||||
cid->pnm[1] = resp[1] >> 24;
|
||||
cid->pnm[2] = resp[1] >> 16;
|
||||
cid->pnm[3] = resp[1] >> 8;
|
||||
cid->pnm[4] = resp[1];
|
||||
cid->pnm[5] = resp[2] >> 24;
|
||||
cid->pnm[6] = 0;
|
||||
cid->prv = resp[2] >> 16;
|
||||
cid->psn = (resp[2] << 16) | (resp[3] >> 16);
|
||||
cid->mdt = resp[3] >> 8;
|
||||
}
|
||||
|
||||
static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp)
|
||||
{
|
||||
cid->mid = resp[0] >> 24;
|
||||
cid->oid = (resp[0] >> 8) & 0xffff;
|
||||
cid->pnm[0] = resp[0];
|
||||
cid->pnm[1] = resp[1] >> 24;
|
||||
cid->pnm[2] = resp[1] >> 16;
|
||||
cid->pnm[3] = resp[1] >> 8;
|
||||
cid->pnm[4] = resp[1];
|
||||
cid->pnm[5] = 0;
|
||||
cid->pnm[6] = 0;
|
||||
cid->prv = resp[2] >> 24;
|
||||
cid->psn = (resp[2] << 8) | (resp[3] >> 24);
|
||||
cid->mdt = (resp[3] >> 8) & 0x0fff;
|
||||
}
|
||||
|
||||
static void mmc_dump_cid(const struct mmc_cid *cid)
|
||||
{
|
||||
printf("Manufacturer ID: %02lX\n", cid->mid);
|
||||
printf("OEM/Application ID: %04lX\n", cid->oid);
|
||||
printf("Product name: %s\n", cid->pnm);
|
||||
printf("Product Revision: %lu.%lu\n",
|
||||
cid->prv >> 4, cid->prv & 0x0f);
|
||||
printf("Product Serial Number: %lu\n", cid->psn);
|
||||
printf("Manufacturing Date: %02lu/%02lu\n",
|
||||
cid->mdt >> 4, cid->mdt & 0x0f);
|
||||
}
|
||||
|
||||
static void mmc_dump_csd(const struct mmc_csd *csd)
|
||||
{
|
||||
unsigned long *csd_raw = (unsigned long *)csd;
|
||||
printf("CSD data: %08lx %08lx %08lx %08lx\n",
|
||||
csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]);
|
||||
printf("CSD structure version: 1.%u\n", csd->csd_structure);
|
||||
printf("MMC System Spec version: %u\n", csd->spec_vers);
|
||||
printf("Card command classes: %03x\n", csd->ccc);
|
||||
printf("Read block length: %u\n", 1 << csd->read_bl_len);
|
||||
if (csd->read_bl_partial)
|
||||
puts("Supports partial reads\n");
|
||||
else
|
||||
puts("Does not support partial reads\n");
|
||||
printf("Write block length: %u\n", 1 << csd->write_bl_len);
|
||||
if (csd->write_bl_partial)
|
||||
puts("Supports partial writes\n");
|
||||
else
|
||||
puts("Does not support partial writes\n");
|
||||
if (csd->wp_grp_enable)
|
||||
printf("Supports group WP: %u\n", csd->wp_grp_size + 1);
|
||||
else
|
||||
puts("Does not support group WP\n");
|
||||
printf("Card capacity: %u bytes\n",
|
||||
(csd->c_size + 1) * (1 << (csd->c_size_mult + 2)) *
|
||||
(1 << csd->read_bl_len));
|
||||
printf("File format: %u/%u\n",
|
||||
csd->file_format_grp, csd->file_format);
|
||||
puts("Write protection: ");
|
||||
if (csd->perm_write_protect)
|
||||
puts(" permanent");
|
||||
if (csd->tmp_write_protect)
|
||||
puts(" temporary");
|
||||
putc('\n');
|
||||
}
|
||||
|
||||
static int mmc_idle_cards(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* Reset and initialize all cards */
|
||||
ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Keep the bus idle for 74 clock cycles */
|
||||
return mmc_cmd(0, 0, NULL, INIT_CMD);
|
||||
}
|
||||
|
||||
static int sd_init_card(struct mmc_cid *cid, int verbose)
|
||||
{
|
||||
unsigned long resp[4];
|
||||
int i, ret = 0;
|
||||
|
||||
mmc_idle_cards();
|
||||
for (i = 0; i < 1000; i++) {
|
||||
ret = mmc_acmd(MMC_ACMD_SD_SEND_OP_COND, CFG_MMC_OP_COND,
|
||||
resp, R3 | NID);
|
||||
if (ret || (resp[0] & 0x80000000))
|
||||
break;
|
||||
ret = -ETIMEDOUT;
|
||||
}
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID);
|
||||
if (ret)
|
||||
return ret;
|
||||
sd_parse_cid(cid, resp);
|
||||
if (verbose)
|
||||
mmc_dump_cid(cid);
|
||||
|
||||
/* Get RCA of the card that responded */
|
||||
ret = mmc_cmd(MMC_CMD_SD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mmc_rca = resp[0] >> 16;
|
||||
if (verbose)
|
||||
printf("SD Card detected (RCA %u)\n", mmc_rca);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mmc_init_card(struct mmc_cid *cid, int verbose)
|
||||
{
|
||||
unsigned long resp[4];
|
||||
int i, ret = 0;
|
||||
|
||||
mmc_idle_cards();
|
||||
for (i = 0; i < 1000; i++) {
|
||||
ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CFG_MMC_OP_COND, resp,
|
||||
R3 | NID | OPEN_DRAIN);
|
||||
if (ret || (resp[0] & 0x80000000))
|
||||
break;
|
||||
ret = -ETIMEDOUT;
|
||||
}
|
||||
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Get CID of all cards. FIXME: Support more than one card */
|
||||
ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN);
|
||||
if (ret)
|
||||
return ret;
|
||||
mmc_parse_cid(cid, resp);
|
||||
if (verbose)
|
||||
mmc_dump_cid(cid);
|
||||
|
||||
/* Set Relative Address of the card that responded */
|
||||
ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp,
|
||||
R1 | NCR | OPEN_DRAIN);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int mmc_init(int verbose)
|
||||
{
|
||||
struct mmc_cid cid;
|
||||
struct mmc_csd csd;
|
||||
int ret;
|
||||
|
||||
/* Initialize controller */
|
||||
mmci_writel(CR, MMCI_BIT(SWRST));
|
||||
mmci_writel(CR, MMCI_BIT(MCIEN));
|
||||
mmci_writel(DTOR, 0x5f);
|
||||
mmci_writel(IDR, ~0UL);
|
||||
mci_set_mode(CFG_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
|
||||
|
||||
ret = sd_init_card(&cid, verbose);
|
||||
if (ret) {
|
||||
mmc_rca = MMC_DEFAULT_RCA;
|
||||
ret = mmc_init_card(&cid, verbose);
|
||||
}
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Get CSD from the card */
|
||||
ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, &csd, R2 | NCR);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (verbose)
|
||||
mmc_dump_csd(&csd);
|
||||
|
||||
/* Initialize the blockdev structure */
|
||||
mmc_blkdev.if_type = IF_TYPE_MMC;
|
||||
mmc_blkdev.part_type = PART_TYPE_DOS;
|
||||
mmc_blkdev.block_read = mmc_bread;
|
||||
sprintf((char *)mmc_blkdev.vendor,
|
||||
"Man %02x%04x Snr %08x",
|
||||
cid.mid, cid.oid, cid.psn);
|
||||
strncpy((char *)mmc_blkdev.product, cid.pnm,
|
||||
sizeof(mmc_blkdev.product));
|
||||
sprintf((char *)mmc_blkdev.revision, "%x %x",
|
||||
cid.prv >> 4, cid.prv & 0x0f);
|
||||
mmc_blkdev.blksz = 1 << csd.read_bl_len;
|
||||
mmc_blkdev.lba = (csd.c_size + 1) * (1 << (csd.c_size_mult + 2));
|
||||
|
||||
mci_set_mode(CFG_MMC_CLK_PP, mmc_blkdev.blksz);
|
||||
|
||||
#if 0
|
||||
if (fat_register_device(&mmc_blkdev, 1))
|
||||
printf("Could not register MMC fat device\n");
|
||||
#else
|
||||
init_part(&mmc_blkdev);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc_read(ulong src, uchar *dst, int size)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
int mmc_write(uchar *src, ulong dst, int size)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
int mmc2info(ulong addr)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_MMC */
|
|
@ -0,0 +1,197 @@
|
|||
/*
|
||||
* Copyright (C) 2005-2006 Atmel Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __CPU_AT32AP_ATMEL_MCI_H__
|
||||
#define __CPU_AT32AP_ATMEL_MCI_H__
|
||||
|
||||
/* Atmel MultiMedia Card Interface (MCI) registers */
|
||||
#define MMCI_CR 0x0000
|
||||
#define MMCI_MR 0x0004
|
||||
#define MMCI_DTOR 0x0008
|
||||
#define MMCI_SDCR 0x000c
|
||||
#define MMCI_ARGR 0x0010
|
||||
#define MMCI_CMDR 0x0014
|
||||
#define MMCI_RSPR 0x0020
|
||||
#define MMCI_RSPR1 0x0024
|
||||
#define MMCI_RSPR2 0x0028
|
||||
#define MMCI_RSPR3 0x002c
|
||||
#define MMCI_RDR 0x0030
|
||||
#define MMCI_TDR 0x0034
|
||||
#define MMCI_SR 0x0040
|
||||
#define MMCI_IER 0x0044
|
||||
#define MMCI_IDR 0x0048
|
||||
#define MMCI_IMR 0x004c
|
||||
|
||||
/* Bitfields in CR */
|
||||
#define MMCI_MCIEN_OFFSET 0
|
||||
#define MMCI_MCIEN_SIZE 1
|
||||
#define MMCI_MCIDIS_OFFSET 1
|
||||
#define MMCI_MCIDIS_SIZE 1
|
||||
#define MMCI_PWSEN_OFFSET 2
|
||||
#define MMCI_PWSEN_SIZE 1
|
||||
#define MMCI_PWSDIS_OFFSET 3
|
||||
#define MMCI_PWSDIS_SIZE 1
|
||||
#define MMCI_SWRST_OFFSET 7
|
||||
#define MMCI_SWRST_SIZE 1
|
||||
|
||||
/* Bitfields in MR */
|
||||
#define MMCI_CLKDIV_OFFSET 0
|
||||
#define MMCI_CLKDIV_SIZE 8
|
||||
#define MMCI_PWSDIV_OFFSET 8
|
||||
#define MMCI_PWSDIV_SIZE 3
|
||||
#define MMCI_PDCPADV_OFFSET 14
|
||||
#define MMCI_PDCPADV_SIZE 1
|
||||
#define MMCI_PDCMODE_OFFSET 15
|
||||
#define MMCI_PDCMODE_SIZE 1
|
||||
#define MMCI_BLKLEN_OFFSET 16
|
||||
#define MMCI_BLKLEN_SIZE 16
|
||||
|
||||
/* Bitfields in DTOR */
|
||||
#define MMCI_DTOCYC_OFFSET 0
|
||||
#define MMCI_DTOCYC_SIZE 4
|
||||
#define MMCI_DTOMUL_OFFSET 4
|
||||
#define MMCI_DTOMUL_SIZE 3
|
||||
|
||||
/* Bitfields in SDCR */
|
||||
#define MMCI_SCDSEL_OFFSET 0
|
||||
#define MMCI_SCDSEL_SIZE 4
|
||||
#define MMCI_SCDBUS_OFFSET 7
|
||||
#define MMCI_SCDBUS_SIZE 1
|
||||
|
||||
/* Bitfields in ARGR */
|
||||
#define MMCI_ARG_OFFSET 0
|
||||
#define MMCI_ARG_SIZE 32
|
||||
|
||||
/* Bitfields in CMDR */
|
||||
#define MMCI_CMDNB_OFFSET 0
|
||||
#define MMCI_CMDNB_SIZE 6
|
||||
#define MMCI_RSPTYP_OFFSET 6
|
||||
#define MMCI_RSPTYP_SIZE 2
|
||||
#define MMCI_SPCMD_OFFSET 8
|
||||
#define MMCI_SPCMD_SIZE 3
|
||||
#define MMCI_OPDCMD_OFFSET 11
|
||||
#define MMCI_OPDCMD_SIZE 1
|
||||
#define MMCI_MAXLAT_OFFSET 12
|
||||
#define MMCI_MAXLAT_SIZE 1
|
||||
#define MMCI_TRCMD_OFFSET 16
|
||||
#define MMCI_TRCMD_SIZE 2
|
||||
#define MMCI_TRDIR_OFFSET 18
|
||||
#define MMCI_TRDIR_SIZE 1
|
||||
#define MMCI_TRTYP_OFFSET 19
|
||||
#define MMCI_TRTYP_SIZE 2
|
||||
|
||||
/* Bitfields in RSPRx */
|
||||
#define MMCI_RSP_OFFSET 0
|
||||
#define MMCI_RSP_SIZE 32
|
||||
|
||||
/* Bitfields in SR/IER/IDR/IMR */
|
||||
#define MMCI_CMDRDY_OFFSET 0
|
||||
#define MMCI_CMDRDY_SIZE 1
|
||||
#define MMCI_RXRDY_OFFSET 1
|
||||
#define MMCI_RXRDY_SIZE 1
|
||||
#define MMCI_TXRDY_OFFSET 2
|
||||
#define MMCI_TXRDY_SIZE 1
|
||||
#define MMCI_BLKE_OFFSET 3
|
||||
#define MMCI_BLKE_SIZE 1
|
||||
#define MMCI_DTIP_OFFSET 4
|
||||
#define MMCI_DTIP_SIZE 1
|
||||
#define MMCI_NOTBUSY_OFFSET 5
|
||||
#define MMCI_NOTBUSY_SIZE 1
|
||||
#define MMCI_ENDRX_OFFSET 6
|
||||
#define MMCI_ENDRX_SIZE 1
|
||||
#define MMCI_ENDTX_OFFSET 7
|
||||
#define MMCI_ENDTX_SIZE 1
|
||||
#define MMCI_RXBUFF_OFFSET 14
|
||||
#define MMCI_RXBUFF_SIZE 1
|
||||
#define MMCI_TXBUFE_OFFSET 15
|
||||
#define MMCI_TXBUFE_SIZE 1
|
||||
#define MMCI_RINDE_OFFSET 16
|
||||
#define MMCI_RINDE_SIZE 1
|
||||
#define MMCI_RDIRE_OFFSET 17
|
||||
#define MMCI_RDIRE_SIZE 1
|
||||
#define MMCI_RCRCE_OFFSET 18
|
||||
#define MMCI_RCRCE_SIZE 1
|
||||
#define MMCI_RENDE_OFFSET 19
|
||||
#define MMCI_RENDE_SIZE 1
|
||||
#define MMCI_RTOE_OFFSET 20
|
||||
#define MMCI_RTOE_SIZE 1
|
||||
#define MMCI_DCRCE_OFFSET 21
|
||||
#define MMCI_DCRCE_SIZE 1
|
||||
#define MMCI_DTOE_OFFSET 22
|
||||
#define MMCI_DTOE_SIZE 1
|
||||
#define MMCI_OVRE_OFFSET 30
|
||||
#define MMCI_OVRE_SIZE 1
|
||||
#define MMCI_UNRE_OFFSET 31
|
||||
#define MMCI_UNRE_SIZE 1
|
||||
|
||||
/* Constants for DTOMUL */
|
||||
#define MMCI_DTOMUL_1_CYCLE 0
|
||||
#define MMCI_DTOMUL_16_CYCLES 1
|
||||
#define MMCI_DTOMUL_128_CYCLES 2
|
||||
#define MMCI_DTOMUL_256_CYCLES 3
|
||||
#define MMCI_DTOMUL_1024_CYCLES 4
|
||||
#define MMCI_DTOMUL_4096_CYCLES 5
|
||||
#define MMCI_DTOMUL_65536_CYCLES 6
|
||||
#define MMCI_DTOMUL_1048576_CYCLES 7
|
||||
|
||||
/* Constants for RSPTYP */
|
||||
#define MMCI_RSPTYP_NO_RESP 0
|
||||
#define MMCI_RSPTYP_48_BIT_RESP 1
|
||||
#define MMCI_RSPTYP_136_BIT_RESP 2
|
||||
|
||||
/* Constants for SPCMD */
|
||||
#define MMCI_SPCMD_NO_SPEC_CMD 0
|
||||
#define MMCI_SPCMD_INIT_CMD 1
|
||||
#define MMCI_SPCMD_SYNC_CMD 2
|
||||
#define MMCI_SPCMD_INT_CMD 4
|
||||
#define MMCI_SPCMD_INT_RESP 5
|
||||
|
||||
/* Constants for TRCMD */
|
||||
#define MMCI_TRCMD_NO_TRANS 0
|
||||
#define MMCI_TRCMD_START_TRANS 1
|
||||
#define MMCI_TRCMD_STOP_TRANS 2
|
||||
|
||||
/* Constants for TRTYP */
|
||||
#define MMCI_TRTYP_BLOCK 0
|
||||
#define MMCI_TRTYP_MULTI_BLOCK 1
|
||||
#define MMCI_TRTYP_STREAM 2
|
||||
|
||||
/* Bit manipulation macros */
|
||||
#define MMCI_BIT(name) \
|
||||
(1 << MMCI_##name##_OFFSET)
|
||||
#define MMCI_BF(name,value) \
|
||||
(((value) & ((1 << MMCI_##name##_SIZE) - 1)) \
|
||||
<< MMCI_##name##_OFFSET)
|
||||
#define MMCI_BFEXT(name,value) \
|
||||
(((value) >> MMCI_##name##_OFFSET)\
|
||||
& ((1 << MMCI_##name##_SIZE) - 1))
|
||||
#define MMCI_BFINS(name,value,old) \
|
||||
(((old) & ~(((1 << MMCI_##name##_SIZE) - 1) \
|
||||
<< MMCI_##name##_OFFSET)) \
|
||||
| MMCI_BF(name,value))
|
||||
|
||||
/* Register access macros */
|
||||
#define mmci_readl(reg) \
|
||||
readl((void *)MMCI_BASE + MMCI_##reg)
|
||||
#define mmci_writel(reg,value) \
|
||||
writel((value), (void *)MMCI_BASE + MMCI_##reg)
|
||||
|
||||
#endif /* __CPU_AT32AP_ATMEL_MCI_H__ */
|
|
@ -26,33 +26,79 @@
|
|||
#include <asm/sections.h>
|
||||
#include <asm/sysreg.h>
|
||||
|
||||
#include <asm/arch/clk.h>
|
||||
#include <asm/arch/memory-map.h>
|
||||
#include <asm/arch/platform.h>
|
||||
|
||||
#include "hsmc3.h"
|
||||
#include "sm.h"
|
||||
|
||||
/* Sanity checks */
|
||||
#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \
|
||||
|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \
|
||||
|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB)
|
||||
# error Constraint fCPU >= fHSB >= fPB{A,B} violated
|
||||
#endif
|
||||
#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1))
|
||||
# error Invalid PLL multiplier and/or divider
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static void pm_init(void)
|
||||
{
|
||||
uint32_t cksel;
|
||||
|
||||
#ifdef CONFIG_PLL
|
||||
/* Initialize the PLL */
|
||||
sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
|
||||
| SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
|
||||
| SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
|
||||
| SM_BF(PLLOPT, CFG_PLL0_OPT)
|
||||
| SM_BF(PLLOSC, 0)
|
||||
| SM_BIT(PLLEN)));
|
||||
|
||||
/* Wait for lock */
|
||||
while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
|
||||
#endif
|
||||
|
||||
/* Set up clocks for the CPU and all peripheral buses */
|
||||
cksel = 0;
|
||||
if (CFG_CLKDIV_CPU)
|
||||
cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
|
||||
if (CFG_CLKDIV_HSB)
|
||||
cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
|
||||
if (CFG_CLKDIV_PBA)
|
||||
cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
|
||||
if (CFG_CLKDIV_PBB)
|
||||
cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
|
||||
sm_writel(PM_CKSEL, cksel);
|
||||
|
||||
gd->cpu_hz = get_cpu_clk_rate();
|
||||
|
||||
#ifdef CONFIG_PLL
|
||||
/* Use PLL0 as main clock */
|
||||
sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
|
||||
#endif
|
||||
}
|
||||
|
||||
int cpu_init(void)
|
||||
{
|
||||
const struct device *hebi;
|
||||
extern void _evba(void);
|
||||
char *p;
|
||||
|
||||
gd->cpu_hz = CFG_OSC0_HZ;
|
||||
|
||||
/* fff03400: 00010001 04030402 00050005 10011103 */
|
||||
hebi = get_device(DEVICE_HEBI);
|
||||
hsmc3_writel(hebi, MODE0, 0x00031103);
|
||||
hsmc3_writel(hebi, CYCLE0, 0x000c000d);
|
||||
hsmc3_writel(hebi, PULSE0, 0x0b0a0906);
|
||||
hsmc3_writel(hebi, SETUP0, 0x00010002);
|
||||
/* TODO: Move somewhere else, but needs to be run before we
|
||||
* increase the clock frequency. */
|
||||
hsmc3_writel(MODE0, 0x00031103);
|
||||
hsmc3_writel(CYCLE0, 0x000c000d);
|
||||
hsmc3_writel(PULSE0, 0x0b0a0906);
|
||||
hsmc3_writel(SETUP0, 0x00010002);
|
||||
|
||||
pm_init();
|
||||
|
||||
sysreg_write(EVBA, (unsigned long)&_evba);
|
||||
asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
|
||||
gd->console_uart = get_device(CFG_CONSOLE_UART_DEV);
|
||||
|
||||
/* Lock everything that mess with the flash in the icache */
|
||||
for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ);
|
||||
|
|
|
@ -1,126 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2006 Atmel Corporation
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#include <common.h>
|
||||
|
||||
#include <asm/arch/platform.h>
|
||||
|
||||
#include "sm.h"
|
||||
|
||||
struct device_state {
|
||||
int refcount;
|
||||
};
|
||||
|
||||
static struct device_state device_state[NR_DEVICES];
|
||||
|
||||
static int claim_resource(const struct resource *res)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
switch (res->type) {
|
||||
case RESOURCE_GPIO:
|
||||
ret = gpio_set_func(res->u.gpio.gpio_dev,
|
||||
res->u.gpio.start,
|
||||
res->u.gpio.nr_pins,
|
||||
res->u.gpio.func);
|
||||
break;
|
||||
case RESOURCE_CLOCK:
|
||||
ret = pm_enable_clock(res->u.clock.id, res->u.clock.index);
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void free_resource(const struct resource *res)
|
||||
{
|
||||
switch (res->type) {
|
||||
case RESOURCE_GPIO:
|
||||
gpio_free(res->u.gpio.gpio_dev, res->u.gpio.start,
|
||||
res->u.gpio.nr_pins);
|
||||
break;
|
||||
case RESOURCE_CLOCK:
|
||||
pm_disable_clock(res->u.clock.id, res->u.clock.index);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static int init_dev(const struct device *dev)
|
||||
{
|
||||
unsigned int i;
|
||||
int ret = 0;
|
||||
|
||||
for (i = 0; i < dev->nr_resources; i++) {
|
||||
ret = claim_resource(&dev->resource[i]);
|
||||
if (ret)
|
||||
goto cleanup;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
cleanup:
|
||||
while (i--)
|
||||
free_resource(&dev->resource[i]);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
const struct device *get_device(enum device_id devid)
|
||||
{
|
||||
struct device_state *devstate;
|
||||
const struct device *dev;
|
||||
unsigned long flags;
|
||||
int initialized = 0;
|
||||
int ret = 0;
|
||||
|
||||
devstate = &device_state[devid];
|
||||
dev = &chip_device[devid];
|
||||
|
||||
flags = disable_interrupts();
|
||||
if (devstate->refcount++)
|
||||
initialized = 1;
|
||||
if (flags)
|
||||
enable_interrupts();
|
||||
|
||||
if (!initialized)
|
||||
ret = init_dev(dev);
|
||||
|
||||
return ret ? NULL : dev;
|
||||
}
|
||||
|
||||
void put_device(const struct device *dev)
|
||||
{
|
||||
struct device_state *devstate;
|
||||
unsigned long devid, flags;
|
||||
|
||||
devid = (unsigned long)(dev - chip_device) / sizeof(struct device);
|
||||
devstate = &device_state[devid];
|
||||
|
||||
flags = disable_interrupts();
|
||||
devstate--;
|
||||
if (!devstate) {
|
||||
unsigned int i;
|
||||
for (i = 0; i < dev->nr_resources; i++)
|
||||
free_resource(&dev->resource[i]);
|
||||
}
|
||||
if (flags)
|
||||
enable_interrupts();
|
||||
}
|
|
@ -42,8 +42,7 @@ timer_interrupt_handler:
|
|||
* We're running at interrupt level 3, so we don't need to save
|
||||
* r8-r12 or lr to the stack.
|
||||
*/
|
||||
mov r8, lo(timer_overflow)
|
||||
orh r8, hi(timer_overflow)
|
||||
lda.w r8, timer_overflow
|
||||
ld.w r9, r8[0]
|
||||
mov r10, -1
|
||||
mtsr SYSREG_COMPARE, r10
|
||||
|
|
|
@ -24,6 +24,8 @@
|
|||
#include <asm/sysreg.h>
|
||||
#include <asm/ptrace.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static const char * const cpu_modes[8] = {
|
||||
"Application", "Supervisor", "Interrupt level 0", "Interrupt level 1",
|
||||
"Interrupt level 2", "Interrupt level 3", "Exception", "NMI"
|
||||
|
@ -109,11 +111,10 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
|
|||
printf("CPU Mode: %s\n", cpu_modes[mode]);
|
||||
|
||||
/* Avoid exception loops */
|
||||
if (regs->sp >= CFG_INIT_SP_ADDR
|
||||
|| regs->sp < (CFG_INIT_SP_ADDR - CONFIG_STACKSIZE))
|
||||
if (regs->sp < CFG_SDRAM_BASE || regs->sp >= gd->stack_end)
|
||||
printf("\nStack pointer seems bogus, won't do stack dump\n");
|
||||
else
|
||||
dump_mem("\nStack: ", regs->sp, CFG_INIT_SP_ADDR);
|
||||
dump_mem("\nStack: ", regs->sp, gd->stack_end);
|
||||
|
||||
panic("Unhandled exception\n");
|
||||
}
|
||||
|
|
|
@ -25,17 +25,11 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/sdram.h>
|
||||
|
||||
#include <asm/arch/platform.h>
|
||||
#include <asm/arch/clk.h>
|
||||
#include <asm/arch/memory-map.h>
|
||||
|
||||
#include "hsdramc1.h"
|
||||
|
||||
struct hsdramc {
|
||||
const struct device *hebi;
|
||||
void *regs;
|
||||
};
|
||||
|
||||
static struct hsdramc hsdramc;
|
||||
|
||||
unsigned long sdram_init(const struct sdram_info *info)
|
||||
{
|
||||
unsigned long *sdram = (unsigned long *)uncached(info->phys_addr);
|
||||
|
@ -44,16 +38,6 @@ unsigned long sdram_init(const struct sdram_info *info)
|
|||
unsigned long bus_hz;
|
||||
unsigned int i;
|
||||
|
||||
hsdramc.hebi = get_device(DEVICE_HEBI);
|
||||
if (!hsdramc.hebi)
|
||||
return 0;
|
||||
|
||||
/* FIXME: Both of these lines are complete hacks */
|
||||
hsdramc.regs = hsdramc.hebi->regs + 0x400;
|
||||
bus_hz = pm_get_clock_freq(hsdramc.hebi->resource[0].u.clock.id);
|
||||
|
||||
cpu_enable_sdram();
|
||||
|
||||
tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
|
||||
| HSDRAMC1_BF(NR, info->row_bits - 11)
|
||||
| HSDRAMC1_BF(NB, info->bank_bits - 1)
|
||||
|
@ -74,7 +58,7 @@ unsigned long sdram_init(const struct sdram_info *info)
|
|||
+ info->bank_bits + 2);
|
||||
#endif
|
||||
|
||||
hsdramc1_writel(&hsdramc, CR, tmp);
|
||||
hsdramc1_writel(CR, tmp);
|
||||
|
||||
/*
|
||||
* Initialization sequence for SDRAM, from the data sheet:
|
||||
|
@ -87,15 +71,15 @@ unsigned long sdram_init(const struct sdram_info *info)
|
|||
/*
|
||||
* 2. A Precharge All command is issued to the SDRAM
|
||||
*/
|
||||
hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
|
||||
hsdramc1_readl(&hsdramc, MR);
|
||||
hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
|
||||
hsdramc1_readl(MR);
|
||||
writel(0, sdram);
|
||||
|
||||
/*
|
||||
* 3. Eight auto-refresh (CBR) cycles are provided
|
||||
*/
|
||||
hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_AUTO_REFRESH);
|
||||
hsdramc1_readl(&hsdramc, MR);
|
||||
hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
|
||||
hsdramc1_readl(MR);
|
||||
for (i = 0; i < 8; i++)
|
||||
writel(0, sdram);
|
||||
|
||||
|
@ -106,8 +90,8 @@ unsigned long sdram_init(const struct sdram_info *info)
|
|||
*
|
||||
* CAS from info struct, burst length 1, serial burst type
|
||||
*/
|
||||
hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_LOAD_MODE);
|
||||
hsdramc1_readl(&hsdramc, MR);
|
||||
hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
|
||||
hsdramc1_readl(MR);
|
||||
writel(0, sdram + (info->cas << 4));
|
||||
|
||||
/*
|
||||
|
@ -117,9 +101,9 @@ unsigned long sdram_init(const struct sdram_info *info)
|
|||
* From the timing diagram, it looks like tMRD is 3
|
||||
* cycles...try a dummy read from the peripheral bus.
|
||||
*/
|
||||
hsdramc1_readl(&hsdramc, MR);
|
||||
hsdramc1_writel(&hsdramc, MR, HSDRAMC1_MODE_NORMAL);
|
||||
hsdramc1_readl(&hsdramc, MR);
|
||||
hsdramc1_readl(MR);
|
||||
hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
|
||||
hsdramc1_readl(MR);
|
||||
writel(0, sdram);
|
||||
|
||||
/*
|
||||
|
@ -128,7 +112,8 @@ unsigned long sdram_init(const struct sdram_info *info)
|
|||
*
|
||||
* 15.6 us is a typical value for a burst of length one
|
||||
*/
|
||||
hsdramc1_writel(&hsdramc, TR, (156 * (bus_hz / 1000)) / 10000);
|
||||
bus_hz = get_sdram_clk_rate();
|
||||
hsdramc1_writel(TR, (156 * (bus_hz / 1000)) / 10000);
|
||||
|
||||
printf("SDRAM: %u MB at address 0x%08lx\n",
|
||||
sdram_size >> 20, info->phys_addr);
|
||||
|
|
|
@ -135,9 +135,9 @@
|
|||
| HSDRAMC1_BF(name,value))
|
||||
|
||||
/* Register access macros */
|
||||
#define hsdramc1_readl(port,reg) \
|
||||
readl((port)->regs + HSDRAMC1_##reg)
|
||||
#define hsdramc1_writel(port,reg,value) \
|
||||
writel((value), (port)->regs + HSDRAMC1_##reg)
|
||||
#define hsdramc1_readl(reg) \
|
||||
readl((void *)HSDRAMC_BASE + HSDRAMC1_##reg)
|
||||
#define hsdramc1_writel(reg,value) \
|
||||
writel((value), (void *)HSDRAMC_BASE + HSDRAMC1_##reg)
|
||||
|
||||
#endif /* __ASM_AVR32_HSDRAMC1_H__ */
|
||||
|
|
|
@ -118,9 +118,9 @@
|
|||
| HSMC3_BF(name,value))
|
||||
|
||||
/* Register access macros */
|
||||
#define hsmc3_readl(port,reg) \
|
||||
readl((port)->regs + HSMC3_##reg)
|
||||
#define hsmc3_writel(port,reg,value) \
|
||||
writel((value), (port)->regs + HSMC3_##reg)
|
||||
#define hsmc3_readl(reg) \
|
||||
readl((void *)HSMC_BASE + HSMC3_##reg)
|
||||
#define hsmc3_writel(reg,value) \
|
||||
writel((value), (void *)HSMC_BASE + HSMC3_##reg)
|
||||
|
||||
#endif /* __CPU_AT32AP_HSMC3_H__ */
|
||||
|
|
|
@ -27,7 +27,7 @@
|
|||
#include <asm/processor.h>
|
||||
#include <asm/sysreg.h>
|
||||
|
||||
#include <asm/arch/platform.h>
|
||||
#include <asm/arch/memory-map.h>
|
||||
|
||||
#define HANDLER_MASK 0x00ffffff
|
||||
#define INTLEV_SHIFT 30
|
||||
|
@ -44,8 +44,6 @@ volatile unsigned long timer_overflow;
|
|||
*/
|
||||
static unsigned long tb_factor;
|
||||
|
||||
static const struct device *intc_dev;
|
||||
|
||||
unsigned long get_tbclk(void)
|
||||
{
|
||||
return gd->cpu_hz;
|
||||
|
@ -117,16 +115,19 @@ void udelay(unsigned long usec)
|
|||
static int set_interrupt_handler(unsigned int nr, void (*handler)(void),
|
||||
unsigned int priority)
|
||||
{
|
||||
extern void _evba(void);
|
||||
unsigned long intpr;
|
||||
unsigned long handler_addr = (unsigned long)handler;
|
||||
|
||||
handler_addr -= (unsigned long)&_evba;
|
||||
|
||||
if ((handler_addr & HANDLER_MASK) != handler_addr
|
||||
|| (priority & INTLEV_MASK) != priority)
|
||||
return -EINVAL;
|
||||
|
||||
intpr = (handler_addr & HANDLER_MASK);
|
||||
intpr |= (priority & INTLEV_MASK) << INTLEV_SHIFT;
|
||||
writel(intpr, intc_dev->regs + 4 * nr);
|
||||
writel(intpr, (void *)INTC_BASE + 4 * nr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -143,10 +144,7 @@ void timer_init(void)
|
|||
do_div(tmp, gd->cpu_hz);
|
||||
tb_factor = (u32)tmp;
|
||||
|
||||
intc_dev = get_device(DEVICE_INTC);
|
||||
|
||||
if (!intc_dev
|
||||
|| set_interrupt_handler(0, &timer_interrupt_handler, 3))
|
||||
if (set_interrupt_handler(0, &timer_interrupt_handler, 3))
|
||||
return;
|
||||
|
||||
/* For all practical purposes, this gives us an overflow interrupt */
|
||||
|
|
|
@ -21,74 +21,40 @@
|
|||
*/
|
||||
#include <common.h>
|
||||
|
||||
#include <asm/errno.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/platform.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/memory-map.h>
|
||||
|
||||
#include "pio2.h"
|
||||
|
||||
struct pio_state {
|
||||
const struct device *dev;
|
||||
u32 alloc_mask;
|
||||
};
|
||||
|
||||
static struct pio_state pio_state[CFG_NR_PIOS];
|
||||
|
||||
int gpio_set_func(enum device_id gpio_devid, unsigned int start,
|
||||
unsigned int nr_pins, enum gpio_func func)
|
||||
void gpio_select_periph_A(unsigned int pin, int use_pullup)
|
||||
{
|
||||
const struct device *gpio;
|
||||
struct pio_state *state;
|
||||
u32 mask;
|
||||
void *base = gpio_pin_to_addr(pin);
|
||||
uint32_t mask = 1 << (pin & 0x1f);
|
||||
|
||||
state = &pio_state[gpio_devid - DEVICE_PIOA];
|
||||
if (!base)
|
||||
panic("Invalid GPIO pin %u\n", pin);
|
||||
|
||||
gpio = get_device(gpio_devid);
|
||||
if (!gpio)
|
||||
return -EBUSY;
|
||||
|
||||
state->dev = gpio;
|
||||
mask = ((1 << nr_pins) - 1) << start;
|
||||
|
||||
if (mask & state->alloc_mask) {
|
||||
put_device(gpio);
|
||||
return -EBUSY;
|
||||
}
|
||||
state->alloc_mask |= mask;
|
||||
|
||||
switch (func) {
|
||||
case GPIO_FUNC_GPIO:
|
||||
/* TODO */
|
||||
return -EINVAL;
|
||||
case GPIO_FUNC_A:
|
||||
pio2_writel(gpio, ASR, mask);
|
||||
pio2_writel(gpio, PDR, mask);
|
||||
pio2_writel(gpio, PUDR, mask);
|
||||
break;
|
||||
case GPIO_FUNC_B:
|
||||
pio2_writel(gpio, BSR, mask);
|
||||
pio2_writel(gpio, PDR, mask);
|
||||
pio2_writel(gpio, PUDR, mask);
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
pio2_writel(base, ASR, mask);
|
||||
pio2_writel(base, PDR, mask);
|
||||
if (use_pullup)
|
||||
pio2_writel(base, PUER, mask);
|
||||
else
|
||||
pio2_writel(base, PUDR, mask);
|
||||
}
|
||||
|
||||
void gpio_free(enum device_id gpio_devid, unsigned int start,
|
||||
unsigned int nr_pins)
|
||||
void gpio_select_periph_B(unsigned int pin, int use_pullup)
|
||||
{
|
||||
const struct device *gpio;
|
||||
struct pio_state *state;
|
||||
u32 mask;
|
||||
void *base = gpio_pin_to_addr(pin);
|
||||
uint32_t mask = 1 << (pin & 0x1f);
|
||||
|
||||
state = &pio_state[gpio_devid - DEVICE_PIOA];
|
||||
gpio = state->dev;
|
||||
mask = ((1 << nr_pins) - 1) << start;
|
||||
if (!base)
|
||||
panic("Invalid GPIO pin %u\n", pin);
|
||||
|
||||
pio2_writel(gpio, ODR, mask);
|
||||
pio2_writel(gpio, PER, mask);
|
||||
|
||||
state->alloc_mask &= ~mask;
|
||||
put_device(gpio);
|
||||
pio2_writel(base, BSR, mask);
|
||||
pio2_writel(base, PDR, mask);
|
||||
if (use_pullup)
|
||||
pio2_writel(base, PUER, mask);
|
||||
else
|
||||
pio2_writel(base, PUDR, mask);
|
||||
}
|
||||
|
|
|
@ -36,9 +36,9 @@
|
|||
#define PIO2_OWSR 0x00a8
|
||||
|
||||
/* Register access macros */
|
||||
#define pio2_readl(port,reg) \
|
||||
readl((port)->regs + PIO2_##reg)
|
||||
#define pio2_writel(port,reg,value) \
|
||||
writel((value), (port)->regs + PIO2_##reg)
|
||||
#define pio2_readl(base,reg) \
|
||||
readl((void *)base + PIO2_##reg)
|
||||
#define pio2_writel(base,reg,value) \
|
||||
writel((value), (void *)base + PIO2_##reg)
|
||||
|
||||
#endif /* __CPU_AT32AP_PIO2_H__ */
|
||||
|
|
131
cpu/at32ap/pm.c
131
cpu/at32ap/pm.c
|
@ -26,138 +26,17 @@
|
|||
#include <asm/io.h>
|
||||
|
||||
#include <asm/arch/memory-map.h>
|
||||
#include <asm/arch/platform.h>
|
||||
|
||||
#include "sm.h"
|
||||
|
||||
/* Sanity checks */
|
||||
#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \
|
||||
|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \
|
||||
|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB)
|
||||
# error Constraint fCPU >= fHSB >= fPB{A,B} violated
|
||||
#endif
|
||||
#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1))
|
||||
# error Invalid PLL multiplier and/or divider
|
||||
|
||||
#ifdef CONFIG_PLL
|
||||
#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
|
||||
#else
|
||||
#define MAIN_CLK_RATE (CFG_OSC0_HZ)
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
struct clock_domain_state {
|
||||
const struct device *bridge;
|
||||
unsigned long freq;
|
||||
u32 mask;
|
||||
};
|
||||
static struct clock_domain_state ckd_state[NR_CLOCK_DOMAINS];
|
||||
|
||||
int pm_enable_clock(enum clock_domain_id id, unsigned int index)
|
||||
{
|
||||
const struct clock_domain *ckd = &chip_clock[id];
|
||||
struct clock_domain_state *state = &ckd_state[id];
|
||||
|
||||
if (ckd->bridge != NO_DEVICE) {
|
||||
state->bridge = get_device(ckd->bridge);
|
||||
if (!state->bridge)
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
state->mask |= 1 << index;
|
||||
if (gd->sm)
|
||||
writel(state->mask, gd->sm->regs + ckd->reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void pm_disable_clock(enum clock_domain_id id, unsigned int index)
|
||||
{
|
||||
const struct clock_domain *ckd = &chip_clock[id];
|
||||
struct clock_domain_state *state = &ckd_state[id];
|
||||
|
||||
state->mask &= ~(1 << index);
|
||||
if (gd->sm)
|
||||
writel(state->mask, gd->sm->regs + ckd->reg);
|
||||
|
||||
if (ckd->bridge)
|
||||
put_device(state->bridge);
|
||||
}
|
||||
|
||||
unsigned long pm_get_clock_freq(enum clock_domain_id domain)
|
||||
{
|
||||
return ckd_state[domain].freq;
|
||||
}
|
||||
|
||||
void pm_init(void)
|
||||
{
|
||||
uint32_t cksel = 0;
|
||||
unsigned long main_clock;
|
||||
|
||||
/* Make sure we don't disable any device we're already using */
|
||||
get_device(DEVICE_HRAMC);
|
||||
get_device(DEVICE_HEBI);
|
||||
|
||||
/* Enable the PICO as well */
|
||||
ckd_state[CLOCK_CPU].mask |= 1;
|
||||
|
||||
gd->sm = get_device(DEVICE_SM);
|
||||
if (!gd->sm)
|
||||
panic("Unable to claim system manager device!\n");
|
||||
|
||||
/* Disable any devices that haven't been explicitly claimed */
|
||||
sm_writel(gd->sm, PM_PBB_MASK, ckd_state[CLOCK_PBB].mask);
|
||||
sm_writel(gd->sm, PM_PBA_MASK, ckd_state[CLOCK_PBA].mask);
|
||||
sm_writel(gd->sm, PM_HSB_MASK, ckd_state[CLOCK_HSB].mask);
|
||||
sm_writel(gd->sm, PM_CPU_MASK, ckd_state[CLOCK_CPU].mask);
|
||||
|
||||
#ifdef CONFIG_PLL
|
||||
/* Initialize the PLL */
|
||||
main_clock = (CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL;
|
||||
|
||||
sm_writel(gd->sm, PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
|
||||
| SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
|
||||
| SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
|
||||
| SM_BF(PLLOPT, CFG_PLL0_OPT)
|
||||
| SM_BF(PLLOSC, 0)
|
||||
| SM_BIT(PLLEN)));
|
||||
|
||||
/* Wait for lock */
|
||||
while (!(sm_readl(gd->sm, PM_ISR) & SM_BIT(LOCK0))) ;
|
||||
#else
|
||||
main_clock = CFG_OSC0_HZ;
|
||||
#endif
|
||||
|
||||
/* Set up clocks for the CPU and all peripheral buses */
|
||||
if (CFG_CLKDIV_CPU) {
|
||||
cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
|
||||
ckd_state[CLOCK_CPU].freq = main_clock / (1 << CFG_CLKDIV_CPU);
|
||||
} else {
|
||||
ckd_state[CLOCK_CPU].freq = main_clock;
|
||||
}
|
||||
if (CFG_CLKDIV_HSB) {
|
||||
cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
|
||||
ckd_state[CLOCK_HSB].freq = main_clock / (1 << CFG_CLKDIV_HSB);
|
||||
} else {
|
||||
ckd_state[CLOCK_HSB].freq = main_clock;
|
||||
}
|
||||
if (CFG_CLKDIV_PBA) {
|
||||
cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
|
||||
ckd_state[CLOCK_PBA].freq = main_clock / (1 << CFG_CLKDIV_PBA);
|
||||
} else {
|
||||
ckd_state[CLOCK_PBA].freq = main_clock;
|
||||
}
|
||||
if (CFG_CLKDIV_PBB) {
|
||||
cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
|
||||
ckd_state[CLOCK_PBB].freq = main_clock / (1 << CFG_CLKDIV_PBB);
|
||||
} else {
|
||||
ckd_state[CLOCK_PBB].freq = main_clock;
|
||||
}
|
||||
sm_writel(gd->sm, PM_CKSEL, cksel);
|
||||
|
||||
/* CFG_HZ currently depends on cpu_hz */
|
||||
gd->cpu_hz = ckd_state[CLOCK_CPU].freq;
|
||||
|
||||
#ifdef CONFIG_PLL
|
||||
/* Use PLL0 as main clock */
|
||||
sm_writel(gd->sm, PM_MCCTRL, SM_BIT(PLLSEL));
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* CFG_POWER_MANAGER */
|
||||
|
|
|
@ -196,9 +196,9 @@
|
|||
| SM_BF(name,value))
|
||||
|
||||
/* Register access macros */
|
||||
#define sm_readl(port,reg) \
|
||||
readl((port)->regs + SM_##reg)
|
||||
#define sm_writel(port,reg,value) \
|
||||
writel((value), (port)->regs + SM_##reg)
|
||||
#define sm_readl(reg) \
|
||||
readl((void *)SM_BASE + SM_##reg)
|
||||
#define sm_writel(reg,value) \
|
||||
writel((value), (void *)SM_BASE + SM_##reg)
|
||||
|
||||
#endif /* __CPU_AT32AP_SM_H__ */
|
||||
|
|
|
@ -70,32 +70,12 @@ _start:
|
|||
|
||||
2: lddpc sp, sp_init
|
||||
|
||||
/*
|
||||
* Relocate the data section and initialize .bss. Everything
|
||||
* is guaranteed to be at least doubleword aligned by the
|
||||
* linker script.
|
||||
*/
|
||||
lddpc r12, .Ldata_vma
|
||||
lddpc r11, .Ldata_lma
|
||||
lddpc r10, .Ldata_end
|
||||
sub r10, r12
|
||||
4: ld.d r8, r11++
|
||||
sub r10, 8
|
||||
st.d r12++, r8
|
||||
brne 4b
|
||||
|
||||
mov r8, 0
|
||||
mov r9, 0
|
||||
lddpc r10, .Lbss_end
|
||||
sub r10, r12
|
||||
4: sub r10, 8
|
||||
st.d r12++, r8
|
||||
brne 4b
|
||||
|
||||
/* Initialize the GOT pointer */
|
||||
lddpc r6, got_init
|
||||
3: rsub r6, pc
|
||||
ld.w pc, r6[start_u_boot@got]
|
||||
|
||||
/* Let's go */
|
||||
rjmp board_init_f
|
||||
|
||||
.align 2
|
||||
.type sp_init,@object
|
||||
|
@ -103,11 +83,82 @@ sp_init:
|
|||
.long CFG_INIT_SP_ADDR
|
||||
got_init:
|
||||
.long 3b - _GLOBAL_OFFSET_TABLE_
|
||||
.Ldata_lma:
|
||||
.long __data_lma
|
||||
.Ldata_vma:
|
||||
.long _data
|
||||
.Ldata_end:
|
||||
.long _edata
|
||||
.Lbss_end:
|
||||
.long _end
|
||||
|
||||
/*
|
||||
* void relocate_code(new_sp, new_gd, monitor_addr)
|
||||
*
|
||||
* Relocate the u-boot image into RAM and continue from there.
|
||||
* Does not return.
|
||||
*/
|
||||
.global relocate_code
|
||||
.type relocate_code,@function
|
||||
relocate_code:
|
||||
mov sp, r12 /* use new stack */
|
||||
mov r12, r11 /* save new_gd */
|
||||
mov r11, r10 /* save destination address */
|
||||
|
||||
/* copy .text section and flush the cache along the way */
|
||||
lda.w r8, _text
|
||||
lda.w r9, _etext
|
||||
sub lr, r10, r8 /* relocation offset */
|
||||
|
||||
1: ldm r8++, r0-r3
|
||||
stm r10, r0-r3
|
||||
sub r10, -16
|
||||
ldm r8++, r0-r3
|
||||
stm r10, r0-r3
|
||||
sub r10, -16
|
||||
cp.w r8, r9
|
||||
cache r10[-4], 0x0d /* dcache clean/invalidate */
|
||||
cache r10[-4], 0x01 /* icache invalidate */
|
||||
brlt 1b
|
||||
|
||||
/* flush write buffer */
|
||||
sync 0
|
||||
|
||||
/* copy data sections */
|
||||
lda.w r9, _edata
|
||||
1: ld.d r0, r8++
|
||||
st.d r10++, r0
|
||||
cp.w r8, r9
|
||||
brlt 1b
|
||||
|
||||
/* zero out .bss */
|
||||
mov r0, 0
|
||||
mov r1, 0
|
||||
lda.w r9, _end
|
||||
sub r9, r8
|
||||
1: st.d r10++, r0
|
||||
sub r9, 8
|
||||
brgt 1b
|
||||
|
||||
/* jump to RAM */
|
||||
sub r0, pc, . - in_ram
|
||||
add pc, r0, lr
|
||||
|
||||
.align 2
|
||||
in_ram:
|
||||
/* find the new GOT and relocate it */
|
||||
lddpc r6, got_init_reloc
|
||||
3: rsub r6, pc
|
||||
mov r8, r6
|
||||
lda.w r9, _egot
|
||||
lda.w r10, _got
|
||||
sub r9, r10
|
||||
1: ld.w r0, r8[0]
|
||||
add r0, lr
|
||||
st.w r8++, r0
|
||||
sub r9, 4
|
||||
brgt 1b
|
||||
|
||||
/* Move the exception handlers */
|
||||
mfsr r2, SYSREG_EVBA
|
||||
add r2, lr
|
||||
mtsr SYSREG_EVBA, r2
|
||||
|
||||
/* Do the rest of the initialization sequence */
|
||||
call board_init_r
|
||||
|
||||
.align 2
|
||||
got_init_reloc:
|
||||
.long 3b - _GLOBAL_OFFSET_TABLE_
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
# U-boot - Makefile
|
||||
#
|
||||
# Copyright (c) 2005 blackfin.uclinux.org
|
||||
# Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
#
|
||||
# (C) Copyright 2000-2006
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -20,8 +20,8 @@
|
|||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - bf533_serial.h Serial Driver defines
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on
|
||||
* bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
|
||||
|
@ -38,8 +38,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _Bf533_SERIAL_H
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
# U-boot - config.mk
|
||||
#
|
||||
# Copyright (c) 2005 blackfin.uclinux.org
|
||||
# Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -20,8 +20,8 @@
|
|||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -mcpu=bf533 -ffixed-P5
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - cpu.c CPU specific functions
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -21,8 +21,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
@ -93,7 +93,7 @@ void icache_enable(void)
|
|||
|
||||
/* Fill the rest with invalid entry */
|
||||
if (j <= 15) {
|
||||
for (; j <= 16; j++) {
|
||||
for (; j < 16; j++) {
|
||||
debug("filling %i with 0", j);
|
||||
*I1++ = 0x0;
|
||||
}
|
||||
|
@ -169,7 +169,7 @@ void dcache_enable(void)
|
|||
|
||||
/* Fill the rest with invalid entry */
|
||||
if (j <= 15) {
|
||||
for (; j <= 16; j++) {
|
||||
for (; j < 16; j++) {
|
||||
debug("filling %i with 0", j);
|
||||
*I1++ = 0x0;
|
||||
}
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - cpu.h
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -18,8 +18,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _CPU_H_
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
|
||||
* Copyright (C) 2004 LG SOft India. All Rights Reserved.
|
||||
/* Copyright (C) 2003-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License.
|
||||
*/
|
||||
|
||||
#define ASSEMBLY
|
||||
|
||||
#include <asm/linkage.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - interrupt.S Processing of interrupts and exception handling
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -35,8 +35,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - interrupts.c Interrupt related routines
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on interrupts.c
|
||||
* Copyright 1996 Roman Zippel
|
||||
|
@ -30,8 +30,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - ints.c Interrupt related routines
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on ints.c
|
||||
*
|
||||
|
@ -32,8 +32,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - serial.c Serial driver for BF533
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on
|
||||
* bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART.
|
||||
|
@ -38,8 +38,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - start.S Startup file of u-boot for BF533/BF561
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on head.S
|
||||
* Copyright (c) 2003 Metrowerks/Motorola
|
||||
|
@ -26,8 +26,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - start1.S Code running out of RAM after relocation
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -18,8 +18,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - traps.c Routines related to interrupts and exceptions
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on
|
||||
* No original Copyright holder listed,
|
||||
|
@ -29,8 +29,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
@ -39,7 +39,6 @@
|
|||
#include <asm/irq.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/machdep.h>
|
||||
#include "cpu.h"
|
||||
#include <asm/arch/anomaly.h>
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
# U-boot - Makefile
|
||||
#
|
||||
# Copyright (c) 2005 blackfin.uclinux.org
|
||||
# Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -20,8 +20,8 @@
|
|||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
# U-boot - config.mk
|
||||
#
|
||||
# Copyright (c) 2005 blackfin.uclinux.org
|
||||
# Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -20,8 +20,8 @@
|
|||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -mcpu=bf537 -ffixed-P5
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - cpu.c CPU specific functions
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -21,8 +21,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - cpu.h
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -18,8 +18,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _CPU_H_
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
|
||||
* Copyright (C) 2004 LG SOft India. All Rights Reserved.
|
||||
/* Copyright (C) 2003-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License.
|
||||
*/
|
||||
|
||||
#define ASSEMBLY
|
||||
|
||||
#include <asm/linkage.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - interrupt.S Processing of interrupts and exception handling
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -35,8 +35,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - interrupts.c Interrupt related routines
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on interrupts.c
|
||||
* Copyright 1996 Roman Zippel
|
||||
|
@ -30,8 +30,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - ints.c Interrupt related routines
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on ints.c
|
||||
*
|
||||
|
@ -32,8 +32,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - serial.c Serial driver for BF537
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on
|
||||
* bf537_serial.c: Serial driver for BlackFin BF537 internal UART.
|
||||
|
@ -38,8 +38,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - bf537_serial.h Serial Driver defines
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on
|
||||
* bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
|
||||
|
@ -38,8 +38,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _Bf537_SERIAL_H
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - start.S Startup file of u-boot for BF537
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on head.S
|
||||
* Copyright (c) 2003 Metrowerks/Motorola
|
||||
|
@ -26,8 +26,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - start1.S Code running out of RAM after relocation
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -18,8 +18,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - traps.c Routines related to interrupts and exceptions
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on
|
||||
* No original Copyright holder listed,
|
||||
|
@ -29,8 +29,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
@ -39,7 +39,6 @@
|
|||
#include <asm/irq.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/traps.h>
|
||||
#include <asm/page.h>
|
||||
#include <asm/machdep.h>
|
||||
#include "cpu.h"
|
||||
#include <asm/arch/anomaly.h>
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
# U-boot - Makefile
|
||||
#
|
||||
# Copyright (c) 2005 blackfin.uclinux.org
|
||||
# Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -20,8 +20,8 @@
|
|||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
# U-boot - config.mk
|
||||
#
|
||||
# Copyright (c) 2005 blackfin.uclinux.org
|
||||
# Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
#
|
||||
# (C) Copyright 2000-2004
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -20,8 +20,8 @@
|
|||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
# MA 02110-1301 USA
|
||||
#
|
||||
|
||||
PLATFORM_RELFLAGS += -mcpu=bf561 -ffixed-P5
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - cpu.c CPU specific functions
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -21,8 +21,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - cpu.h
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
@ -18,8 +18,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _CPU_H_
|
||||
|
|
|
@ -1,9 +1,9 @@
|
|||
/* Copyright (C) 2003 Analog Devices, Inc. All Rights Reserved.
|
||||
* Copyright (C) 2004 LG SOft India. All Rights Reserved.
|
||||
/* Copyright (C) 2003-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License.
|
||||
*/
|
||||
|
||||
#define ASSEMBLY
|
||||
|
||||
#include <asm/linkage.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - interrupt.S Processing of interrupts and exception handling
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
@ -35,8 +35,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define ASSEMBLY
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - interrupts.c Interrupt related routines
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on interrupts.c
|
||||
* Copyright 1996 Roman Zippel
|
||||
|
@ -30,8 +30,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - ints.c Interrupt related routines
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on ints.c
|
||||
*
|
||||
|
@ -32,8 +32,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - serial.c Serial driver for BF561
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on
|
||||
* bf533_serial.c: Serial driver for BlackFin BF533 DSP internal UART.
|
||||
|
@ -38,8 +38,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* U-boot - bf561_serial.h Serial Driver defines
|
||||
*
|
||||
* Copyright (c) 2005 blackfin.uclinux.org
|
||||
* Copyright (c) 2005-2007 Analog Devices Inc.
|
||||
*
|
||||
* This file is based on
|
||||
* bf533_serial.h: Definitions for the BlackFin BF533 DSP serial driver.
|
||||
|
@ -38,8 +38,8 @@
|
|||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef _Bf561_SERIAL_H
|
||||
|
|
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Reference in New Issue