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arm: socfpga: reset: Implement unified function to toggle reset 

Implement function socfpga_per_reset(), which allows asserting or
de-asserting reset of each reset manager peripheral in a unified
manner. Use this function throughout reset manager.

Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Marek Vasut 2015-07-09 02:45:15 +02:00
parent 1115cd2de7
commit bdfc2ef64a
2 changed files with 37 additions and 23 deletions
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2
arch/arm/mach-socfpga/include/mach/reset_manager.h
View File

@ -12,6 +12,8 @@ void reset_deassert_peripherals_handoff(void);
void socfpga_bridges_reset(int enable); void socfpga_bridges_reset(int enable);
void socfpga_per_reset(u32 reset, int set);
void socfpga_emac_reset(int enable); void socfpga_emac_reset(int enable);
void socfpga_watchdog_reset(void); void socfpga_watchdog_reset(void);
void socfpga_spim_enable(void); void socfpga_spim_enable(void);

58
arch/arm/mach-socfpga/reset_manager.c
View File

@ -15,16 +15,38 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_reset_manager *reset_manager_base = static const struct socfpga_reset_manager *reset_manager_base =
(void *)SOCFPGA_RSTMGR_ADDRESS; (void *)SOCFPGA_RSTMGR_ADDRESS;
/* Assert or de-assert SoCFPGA reset manager reset. */
void socfpga_per_reset(u32 reset, int set)
{
const void *reg;
if (RSTMGR_BANK(reset) == 0)
reg = &reset_manager_base->mpu_mod_reset;
else if (RSTMGR_BANK(reset) == 1)
reg = &reset_manager_base->per_mod_reset;
else if (RSTMGR_BANK(reset) == 2)
reg = &reset_manager_base->per2_mod_reset;
else if (RSTMGR_BANK(reset) == 3)
reg = &reset_manager_base->brg_mod_reset;
else if (RSTMGR_BANK(reset) == 4)
reg = &reset_manager_base->misc_mod_reset;
else /* Invalid reset register, do nothing */
return;
if (set)
setbits_le32(reg, 1 << RSTMGR_RESET(reset));
else
clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
}
/* Toggle reset signal to watchdog (WDT is disabled after this operation!) */ /* Toggle reset signal to watchdog (WDT is disabled after this operation!) */
void socfpga_watchdog_reset(void) void socfpga_watchdog_reset(void)
{ {
/* assert reset for watchdog */ /* assert reset for watchdog */
setbits_le32(&reset_manager_base->per_mod_reset, socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)));
/* deassert watchdog from reset (watchdog in not running state) */ /* deassert watchdog from reset (watchdog in not running state) */
clrbits_le32(&reset_manager_base->per_mod_reset, socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)));
} }
/* /*
@ -91,16 +113,14 @@ void socfpga_bridges_reset(int enable)
/* Change the reset state for EMAC 0 and EMAC 1 */ /* Change the reset state for EMAC 0 and EMAC 1 */
void socfpga_emac_reset(int enable) void socfpga_emac_reset(int enable)
{ {
const void *reset = &reset_manager_base->per_mod_reset;
if (enable) { if (enable) {
setbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC0))); socfpga_per_reset(SOCFPGA_RESET(EMAC0), 1);
setbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC1))); socfpga_per_reset(SOCFPGA_RESET(EMAC1), 1);
} else { } else {
#if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS) #if (CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS)
clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC0))); socfpga_per_reset(SOCFPGA_RESET(EMAC0), 0);
#elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS) #elif (CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS)
clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(EMAC1))); socfpga_per_reset(SOCFPGA_RESET(EMAC1), 0);
#endif #endif
} }
} }
@ -108,32 +128,24 @@ void socfpga_emac_reset(int enable)
/* SPI Master enable (its held in reset by the preloader) */ /* SPI Master enable (its held in reset by the preloader) */
void socfpga_spim_enable(void) void socfpga_spim_enable(void)
{ {
const void *reset = &reset_manager_base->per_mod_reset; socfpga_per_reset(SOCFPGA_RESET(SPIM0), 0);
socfpga_per_reset(SOCFPGA_RESET(SPIM1), 0);
clrbits_le32(reset, (1 << RSTMGR_RESET(SOCFPGA_RESET(SPIM0))) |
(1 << RSTMGR_RESET(SOCFPGA_RESET(SPIM1))));
} }
/* Bring UART0 out of reset. */ /* Bring UART0 out of reset. */
void socfpga_uart0_enable(void) void socfpga_uart0_enable(void)
{ {
const void *reset = &reset_manager_base->per_mod_reset; socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(UART0)));
} }
/* Bring SDRAM controller out of reset. */ /* Bring SDRAM controller out of reset. */
void socfpga_sdram_enable(void) void socfpga_sdram_enable(void)
{ {
const void *reset = &reset_manager_base->per_mod_reset; socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(SDR)));
} }
/* Bring OSC1 timer out of reset. */ /* Bring OSC1 timer out of reset. */
void socfpga_osc1timer_enable(void) void socfpga_osc1timer_enable(void)
{ {
const void *reset = &reset_manager_base->per_mod_reset; socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
clrbits_le32(reset, 1 << RSTMGR_RESET(SOCFPGA_RESET(OSC1TIMER0)));
} }