MX5: Modify the PLL decoding algorithm
The PLL decoding algorithm didn't take into account many configuration bits. Adjust it according to Linux kernel. Also, add PLL4 for MX53. Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Jason Hui <jason.hui@linaro.org> Tested-by: Jason Liu <Jason.hui@linaro.org>
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@ -29,11 +29,13 @@
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock.h>
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#include <div64.h>
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enum pll_clocks {
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enum pll_clocks {
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PLL1_CLOCK = 0,
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PLL1_CLOCK = 0,
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PLL2_CLOCK,
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PLL2_CLOCK,
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PLL3_CLOCK,
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PLL3_CLOCK,
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PLL4_CLOCK,
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PLL_CLOCKS,
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PLL_CLOCKS,
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};
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};
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@ -41,25 +43,65 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
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[PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
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[PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
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[PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
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[PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
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[PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
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[PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
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#ifdef CONFIG_MX53
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[PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
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#endif
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};
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};
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
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/*
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/*
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* Calculate the frequency of this pll.
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* Calculate the frequency of PLLn.
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*/
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*/
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static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq)
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static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
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{
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{
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u32 mfi, mfn, mfd, pd;
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uint32_t ctrl, op, mfd, mfn, mfi, pdf, ret;
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uint64_t refclk, temp;
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int32_t mfn_abs;
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mfn = __raw_readl(&pll->mfn);
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ctrl = readl(&pll->ctrl);
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mfd = __raw_readl(&pll->mfd) + 1;
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mfi = __raw_readl(&pll->op);
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pd = (mfi & 0xF) + 1;
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mfi = (mfi >> 4) & 0xF;
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mfi = (mfi >= 5) ? mfi : 5;
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return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000;
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if (ctrl & MXC_DPLLC_CTL_HFSM) {
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mfn = __raw_readl(&pll->hfs_mfn);
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mfd = __raw_readl(&pll->hfs_mfd);
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op = __raw_readl(&pll->hfs_op);
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} else {
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mfn = __raw_readl(&pll->mfn);
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mfd = __raw_readl(&pll->mfd);
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op = __raw_readl(&pll->op);
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}
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mfd &= MXC_DPLLC_MFD_MFD_MASK;
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mfn &= MXC_DPLLC_MFN_MFN_MASK;
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pdf = op & MXC_DPLLC_OP_PDF_MASK;
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mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
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/* 21.2.3 */
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if (mfi < 5)
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mfi = 5;
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/* Sign extend */
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if (mfn >= 0x04000000) {
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mfn |= 0xfc000000;
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mfn_abs = -mfn;
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} else
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mfn_abs = mfn;
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refclk = infreq * 2;
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if (ctrl & MXC_DPLLC_CTL_DPDCK0_2_EN)
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refclk *= 2;
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refclk /= pdf + 1;
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temp = refclk * mfn_abs;
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do_div(temp, mfd + 1);
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ret = refclk * mfi;
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if ((int)mfn < 0)
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ret -= temp;
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else
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ret += temp;
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return ret;
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}
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}
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/*
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/*
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@ -279,6 +321,10 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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printf("pll2: %dMHz\n", freq / 1000000);
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printf("pll2: %dMHz\n", freq / 1000000);
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freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
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freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
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printf("pll3: %dMHz\n", freq / 1000000);
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printf("pll3: %dMHz\n", freq / 1000000);
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#ifdef CONFIG_MX53
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freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
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printf("pll4: %dMHz\n", freq / 1000000);
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#endif
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printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
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printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK));
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printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
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printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK));
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@ -200,4 +200,15 @@ struct mxc_ccm_reg {
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/* Define the bits in register CLPCR */
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/* Define the bits in register CLPCR */
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#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
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#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
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#define MXC_DPLLC_CTL_HFSM (1 << 7)
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#define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12)
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#define MXC_DPLLC_OP_PDF_MASK 0xf
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#define MXC_DPLLC_OP_MFI_MASK (0xf << 4)
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#define MXC_DPLLC_OP_MFI_OFFSET 4
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#define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff
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#define MXC_DPLLC_MFN_MFN_MASK 0x7ffffff
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#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
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#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */
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@ -100,6 +100,9 @@
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#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
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#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
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#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
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#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
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#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
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#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
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#ifdef CONFIG_MX53
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#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000)
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#endif
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#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
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#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
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#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
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#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
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#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
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#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
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