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PPC: Change lib_ppc/bat_rw.c to use high bats 

Currently, this code only deals with BATs 0-3, which makes
it useless on systems that support BATs 4-7.  Add the
support for these registers.

Signed-off-by: Becky Bruce <Becky.bruce@freescale.com>
This commit is contained in:
Becky Bruce 2008-05-15 21:29:04 -05:00 committed by Wolfgang Denk
parent 31d8267224
commit c148f24c15
2 changed files with 105 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
include/asm-ppc/mmu.h
View File

@ -140,7 +140,11 @@ extern void _tlbia(void); /* invalidate all TLB entries */
typedef enum {
IBAT0 = 0, IBAT1, IBAT2, IBAT3,
DBAT0, DBAT1, DBAT2, DBAT3
DBAT0, DBAT1, DBAT2, DBAT3,
#ifdef CONFIG_HIGH_BATS
IBAT4, IBAT5, IBAT6, IBAT7,
DBAT4, DBAT5, DBAT6, DBAT7
#endif
} ppc_bat_t;
extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);

148
lib_ppc/bat_rw.c
View File

@ -29,46 +29,72 @@
int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
{
switch (bat) {
case IBAT0:
mtspr (IBAT0L, lower);
mtspr (IBAT0U, upper);
break;
case IBAT1:
mtspr (IBAT1L, lower);
mtspr (IBAT1U, upper);
break;
case IBAT2:
mtspr (IBAT2L, lower);
mtspr (IBAT2U, upper);
break;
case IBAT3:
mtspr (IBAT3L, lower);
mtspr (IBAT3U, upper);
break;
case DBAT0:
mtspr (DBAT0L, lower);
mtspr (DBAT0U, upper);
break;
case IBAT0:
mtspr (IBAT0L, lower);
mtspr (IBAT0U, upper);
break;
case DBAT1:
mtspr (DBAT1L, lower);
mtspr (DBAT1U, upper);
break;
case IBAT1:
mtspr (IBAT1L, lower);
mtspr (IBAT1U, upper);
break;
case DBAT2:
mtspr (DBAT2L, lower);
mtspr (DBAT2U, upper);
break;
case IBAT2:
mtspr (IBAT2L, lower);
mtspr (IBAT2U, upper);
break;
case DBAT3:
mtspr (DBAT3L, lower);
mtspr (DBAT3U, upper);
break;
case IBAT3:
mtspr (IBAT3L, lower);
mtspr (IBAT3U, upper);
break;
#ifdef CONFIG_HIGH_BATS
case DBAT4:
mtspr (DBAT4L, lower);
mtspr (DBAT4U, upper);
break;
case IBAT4:
mtspr (IBAT4L, lower);
mtspr (IBAT4U, upper);
break;
case DBAT5:
mtspr (DBAT5L, lower);
mtspr (DBAT5U, upper);
break;
case IBAT5:
mtspr (IBAT5L, lower);
mtspr (IBAT5U, upper);
break;
case DBAT6:
mtspr (DBAT6L, lower);
mtspr (DBAT6U, upper);
break;
case IBAT6:
mtspr (IBAT6L, lower);
mtspr (IBAT6U, upper);
break;
case DBAT7:
mtspr (DBAT7L, lower);
mtspr (DBAT7U, upper);
break;
case IBAT7:
mtspr (IBAT7L, lower);
mtspr (IBAT7U, upper);
break;
#endif
default:
return (-1);
}
@ -82,46 +108,72 @@ int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower)
unsigned long register l;
switch (bat) {
case IBAT0:
l = mfspr (IBAT0L);
u = mfspr (IBAT0U);
break;
case IBAT1:
l = mfspr (IBAT1L);
u = mfspr (IBAT1U);
break;
case IBAT2:
l = mfspr (IBAT2L);
u = mfspr (IBAT2U);
break;
case IBAT3:
l = mfspr (IBAT3L);
u = mfspr (IBAT3U);
break;
case DBAT0:
l = mfspr (DBAT0L);
u = mfspr (DBAT0U);
break;
case IBAT0:
l = mfspr (IBAT0L);
u = mfspr (IBAT0U);
break;
case DBAT1:
l = mfspr (DBAT1L);
u = mfspr (DBAT1U);
break;
case IBAT1:
l = mfspr (IBAT1L);
u = mfspr (IBAT1U);
break;
case DBAT2:
l = mfspr (DBAT2L);
u = mfspr (DBAT2U);
break;
case IBAT2:
l = mfspr (IBAT2L);
u = mfspr (IBAT2U);
break;
case DBAT3:
l = mfspr (DBAT3L);
u = mfspr (DBAT3U);
break;
case IBAT3:
l = mfspr (IBAT3L);
u = mfspr (IBAT3U);
break;
#ifdef CONFIG_HIGH_BATS
case DBAT4:
l = mfspr (DBAT4L);
u = mfspr (DBAT4U);
break;
case IBAT4:
l = mfspr (IBAT4L);
u = mfspr (IBAT4U);
break;
case DBAT5:
l = mfspr (DBAT5L);
u = mfspr (DBAT5U);
break;
case IBAT5:
l = mfspr (IBAT5L);
u = mfspr (IBAT5U);
break;
case DBAT6:
l = mfspr (DBAT6L);
u = mfspr (DBAT6U);
break;
case IBAT6:
l = mfspr (IBAT6L);
u = mfspr (IBAT6U);
break;
case DBAT7:
l = mfspr (DBAT7L);
u = mfspr (DBAT7U);
break;
case IBAT7:
l = mfspr (IBAT7L);
u = mfspr (IBAT7U);
break;
#endif
default:
return (-1);
}