sc520: Define MMCR address in include file
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0ea76e92e9
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c2cbbaf0b4
4 changed files with 55 additions and 39 deletions
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@ -38,7 +38,7 @@ DECLARE_GLOBAL_DATA_PTR;
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* unsigned long init_sc520_dram(void)
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* unsigned long init_sc520_dram(void)
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*/
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*/
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volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
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sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)SC520_MMCR_BASE;
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int cpu_init_f(void)
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int cpu_init_f(void)
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{
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{
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@ -142,16 +142,9 @@
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*/
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*/
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#include <config.h>
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#include <config.h>
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#include <asm/ic/sc520.h>
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.section .text
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.section .text
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.equ DRCCTL, 0x0fffef010 /* DRAM control register */
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.equ DRCTMCTL, 0x0fffef012 /* DRAM timing control register */
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.equ DRCCFG, 0x0fffef014 /* DRAM bank configuration register */
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.equ DRCBENDADR, 0x0fffef018 /* DRAM bank ending address register */
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.equ ECCCTL, 0x0fffef020 /* DRAM ECC control register */
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.equ ECCINT, 0x0fffefd18 /* DRAM ECC nmi-INT mapping */
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.equ DBCTL, 0x0fffef040 /* DRAM buffer control register */
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.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */
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.equ CACHELINESZ, 0x00000010 /* size of our cache line (read buffer) */
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.equ COL11_ADR, 0x0e001e00 /* 11 col addrs */
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.equ COL11_ADR, 0x0e001e00 /* 11 col addrs */
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.equ COL10_ADR, 0x0e000e00 /* 10 col addrs */
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.equ COL10_ADR, 0x0e000e00 /* 10 col addrs */
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@ -179,27 +172,27 @@ mem_init:
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/* initialize dram controller registers */
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/* initialize dram controller registers */
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xorw %ax, %ax
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xorw %ax, %ax
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movl $DBCTL, %edi
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movl $SC520_DBCTL, %edi
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movb %al, (%edi) /* disable write buffer */
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movb %al, (%edi) /* disable write buffer */
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movl $ECCCTL, %edi
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movl $SC520_ECCCTL, %edi
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movb %al, (%edi) /* disable ECC */
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movb %al, (%edi) /* disable ECC */
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movl $DRCTMCTL, %edi
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movl $SC520_DRCTMCTL, %edi
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movb $0x1e, %al /* Set SDRAM timing for slowest */
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movb $0x1e, %al /* Set SDRAM timing for slowest */
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movb %al, (%edi)
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movb %al, (%edi)
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/* setup loop to do 4 external banks starting with bank 3 */
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/* setup loop to do 4 external banks starting with bank 3 */
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movl $0xff000000, %eax /* enable last bank and setup */
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movl $0xff000000, %eax /* enable last bank and setup */
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movl $DRCBENDADR, %edi /* ending address register */
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movl $SC520_DRCBENDADR, %edi /* ending address register */
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movl %eax, (%edi)
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movl %eax, (%edi)
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movl $DRCCFG, %edi /* setup */
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movl $SC520_DRCCFG, %edi /* setup */
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movw $0xbbbb, %ax /* dram config register for */
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movw $0xbbbb, %ax /* dram config register for */
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movw %ax, (%edi)
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movw %ax, (%edi)
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/* issue a NOP to all DRAMs */
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/* issue a NOP to all DRAMs */
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movl $DRCCTL, %edi /* setup DRAM control register with */
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movl $SC520_DRCCTL, %edi /* setup DRAM control register with */
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movb $0x01, %al /* Disable refresh,disable write buffer */
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movb $0x01, %al /* Disable refresh,disable write buffer */
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movb %al, (%edi)
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movb %al, (%edi)
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movl $CACHELINESZ, %esi /* just a dummy address to write for */
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movl $CACHELINESZ, %esi /* just a dummy address to write for */
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@ -409,7 +402,7 @@ bad_reint:
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/*
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/*
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* issue all banks precharge
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* issue all banks precharge
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*/
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*/
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movl $DRCCTL, %esi /* setup DRAM control register with */
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movl $SC520_DRCCTL, %esi /* setup DRAM control register with */
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movb $0x02, %al /* All banks precharge */
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movb $0x02, %al /* All banks precharge */
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movb %al, (%esi)
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movb %al, (%esi)
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movl $CACHELINESZ, %esi /* address to init read buffer */
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movl $CACHELINESZ, %esi /* address to init read buffer */
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@ -418,7 +411,7 @@ bad_reint:
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/*
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/*
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* update ENDING ADDRESS REGISTER
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* update ENDING ADDRESS REGISTER
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*/
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*/
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movl $DRCBENDADR, %edi /* DRAM ending address register */
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movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */
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movl %ecx, %ebx
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movl %ecx, %ebx
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addl %ebx, %edi
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addl %ebx, %edi
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movb %dh, (%edi)
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movb %dh, (%edi)
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@ -435,7 +428,7 @@ bad_reint:
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shlw %cl, %bx
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shlw %cl, %bx
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notw %bx
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notw %bx
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xchgw %cx, %ax
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xchgw %cx, %ax
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movl $DRCCFG, %edi
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movl $SC520_DRCCFG, %edi
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movw (%edi), %ax
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movw (%edi), %ax
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andw %bx, %ax
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andw %bx, %ax
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orw %dx, %ax
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orw %dx, %ax
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@ -444,7 +437,7 @@ bad_reint:
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decw %cx
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decw %cx
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movl %ecx, %ebx
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movl %ecx, %ebx
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movl $DRCBENDADR, %edi /* DRAM ending address register */
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movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */
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movb $0xff, %al
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movb $0xff, %al
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addl %ebx, %edi
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addl %ebx, %edi
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movb %al, (%edi)
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movb %al, (%edi)
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@ -452,7 +445,7 @@ bad_reint:
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/*
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/*
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* set control register to NORMAL mode
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* set control register to NORMAL mode
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*/
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*/
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movl $DRCCTL, %esi /* setup DRAM control register with */
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movl $SC520_DRCCTL, %esi /* setup DRAM control register with */
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movb $0x00, %al /* Normal mode value */
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movb $0x00, %al /* Normal mode value */
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movb %al, (%esi)
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movb %al, (%esi)
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movl $CACHELINESZ, %esi /* address to init read buffer */
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movl $CACHELINESZ, %esi /* address to init read buffer */
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@ -460,7 +453,7 @@ bad_reint:
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jmp nextbank
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jmp nextbank
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cleanup:
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cleanup:
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movl $DRCBENDADR, %edi /* DRAM ending address register */
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movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */
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movw $0x04, %cx
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movw $0x04, %cx
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xorw %ax, %ax
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xorw %ax, %ax
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cleanuplp:
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cleanuplp:
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@ -482,7 +475,7 @@ emptybank:
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#if defined CONFIG_SYS_SDRAM_DRCTMCTL
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#if defined CONFIG_SYS_SDRAM_DRCTMCTL
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/* just have your hardware desinger _GIVE_ you what you need here! */
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/* just have your hardware desinger _GIVE_ you what you need here! */
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movl $DRCTMCTL, %edi
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movl $SC520_DRCTMCTL, %edi
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movb $CONFIG_SYS_SDRAM_DRCTMCTL, %al
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movb $CONFIG_SYS_SDRAM_DRCTMCTL, %al
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movb %al, (%edi)
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movb %al, (%edi)
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#else
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#else
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@ -491,7 +484,7 @@ emptybank:
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* Set the CAS latency now since it is hard to do
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* Set the CAS latency now since it is hard to do
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* when we run from the RAM
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* when we run from the RAM
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*/
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*/
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movl $DRCTMCTL, %edi /* DRAM timing register */
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movl $SC520_DRCTMCTL, %edi /* DRAM timing register */
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movb (%edi), %al
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movb (%edi), %al
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#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
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#ifdef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
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andb $0xef, %al
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andb $0xef, %al
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@ -502,13 +495,13 @@ emptybank:
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movb %al, (%edi)
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movb %al, (%edi)
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#endif
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#endif
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#endif
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#endif
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movl $DRCCTL, %edi /* DRAM Control register */
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movl $SC520_DRCCTL, %edi /* DRAM Control register */
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movb $0x03, %al /* Load mode register cmd */
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movb $0x03, %al /* Load mode register cmd */
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movb %al, (%edi)
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movb %al, (%edi)
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movw %ax, (%esi)
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movw %ax, (%esi)
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movl $DRCCTL, %edi /* DRAM Control register */
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movl $SC520_DRCCTL, %edi /* DRAM Control register */
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movb $0x18, %al /* Enable refresh and NORMAL mode */
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movb $0x18, %al /* Enable refresh and NORMAL mode */
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movb %al, (%edi)
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movb %al, (%edi)
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@ -553,16 +546,16 @@ set_ecc:
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/* enable read, write buffers */
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/* enable read, write buffers */
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movb $0x11, %al
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movb $0x11, %al
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movl $DBCTL, %edi
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movl $SC520_DBCTL, %edi
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movb %al, (%edi)
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movb %al, (%edi)
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/* enable NMI mapping for ECC */
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/* enable NMI mapping for ECC */
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movl $ECCINT, %edi
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movl $SC520_ECCINT, %edi
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movb $0x10, %al
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movb $0x10, %al
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movb %al, (%edi)
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movb %al, (%edi)
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/* Turn on ECC */
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/* Turn on ECC */
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movl $ECCCTL, %edi
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movl $SC520_ECCCTL, %edi
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movb $0x05, %al
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movb $0x05, %al
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movb %al,(%edi)
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movb %al,(%edi)
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@ -576,7 +569,7 @@ out:
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*/
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*/
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.globl get_mem_size
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.globl get_mem_size
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get_mem_size:
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get_mem_size:
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movl $DRCBENDADR, %edi /* DRAM ending address register */
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movl $SC520_DRCBENDADR, %edi /* DRAM ending address register */
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bank0: movl (%edi), %eax
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bank0: movl (%edi), %eax
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movl %eax, %ecx
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movl %eax, %ecx
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@ -252,16 +252,38 @@ typedef struct sc520_mmcr {
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u8 pad_0xdc0[0x0240];
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u8 pad_0xdc0[0x0240];
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} sc520_mmcr_t;
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} sc520_mmcr_t;
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extern volatile sc520_mmcr_t *sc520_mmcr;
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extern sc520_mmcr_t *sc520_mmcr;
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#endif
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#endif
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/* MMCR Offsets (required for assembler code */
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/* Memory Mapped Control Registers (MMCR) Base Address */
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#define SC520_DBCTL 0x0040 /* SDRAM Buffer Control Register */
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#define SC520_MMCR_BASE 0xfffef000
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#define SC520_PAR14 0x00c0 /* Programmable Address Region 14 Register */
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#define SC520_PAR15 0x00c4 /* Programmable Address Region 15 Register */
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/* MMCR Addresses (required for assembler code) */
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#define SC520_SWTMRMILLI 0x0c60 /* Software Timer Millisecond Count */
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#define SC520_DRCCTL (SC520_MMCR_BASE + 0x010)
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#define SC520_SWTMRMICRO 0x0c62 /* Software Timer Microsecond Count */
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#define SC520_DRCTMCTL (SC520_MMCR_BASE + 0x012)
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#define SC520_DRCCFG (SC520_MMCR_BASE + 0x014)
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#define SC520_DRCBENDADR (SC520_MMCR_BASE + 0x018)
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#define SC520_ECCCTL (SC520_MMCR_BASE + 0x020)
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#define SC520_DBCTL (SC520_MMCR_BASE + 0x040)
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#define SC520_ECCINT (SC520_MMCR_BASE + 0xd18)
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#define SC520_PAR0 (SC520_MMCR_BASE + 0x088)
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#define SC520_PAR1 (SC520_PAR0 + (0x04 * 1))
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#define SC520_PAR2 (SC520_PAR0 + (0x04 * 2))
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#define SC520_PAR3 (SC520_PAR0 + (0x04 * 3))
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#define SC520_PAR4 (SC520_PAR0 + (0x04 * 4))
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#define SC520_PAR5 (SC520_PAR0 + (0x04 * 5))
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#define SC520_PAR6 (SC520_PAR0 + (0x04 * 6))
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#define SC520_PAR7 (SC520_PAR0 + (0x04 * 7))
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#define SC520_PAR8 (SC520_PAR0 + (0x04 * 8))
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#define SC520_PAR9 (SC520_PAR0 + (0x04 * 9))
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#define SC520_PAR10 (SC520_PAR0 + (0x04 * 10))
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#define SC520_PAR11 (SC520_PAR0 + (0x04 * 11))
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#define SC520_PAR12 (SC520_PAR0 + (0x04 * 12))
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#define SC520_PAR13 (SC520_PAR0 + (0x04 * 13))
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#define SC520_PAR14 (SC520_PAR0 + (0x04 * 14))
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#define SC520_PAR15 (SC520_PAR0 + (0x04 * 15))
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/* MMCR Register bits (not all of them :) ) */
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/* MMCR Register bits (not all of them :) ) */
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@ -30,6 +30,7 @@
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/* #include <asm/ic/sc520_defs.h> */
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/* #include <asm/ic/sc520_defs.h> */
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#include "hardware.h"
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#include "hardware.h"
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#include <asm/ic/sc520.h>
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.text
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.text
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.section .start16, "ax"
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.section .start16, "ax"
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@ -46,17 +47,17 @@ board_init16:
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movw %ax, %ds
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movw %ax, %ds
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/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
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/* Map PAR for Boot Flash (BOOTCS, 512kB @ 0x380000000) */
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movl $0x00c0, %edi /* SC520_PAR14 */
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movl $(SC520_PAR14 - SC520_MMCR_BASE), %edi
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movl $0x8bfff800, %eax /* TODO: Check this */
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movl $0x8bfff800, %eax /* TODO: Check this */
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movl %eax, (%di)
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movl %eax, (%di)
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/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
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/* Map PAR for LED, Hex Switches (GPCS6, 20 Bytes @ 0x1000) */
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movl $0x00c4, %edi /* SC520_PAR15 */
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movl $(SC520_PAR15 - SC520_MMCR_BASE), %edi
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movl $0x38201000, %eax
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movl $0x38201000, %eax
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movl %eax, (%di)
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movl %eax, (%di)
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/* Disable SDRAM write buffer */
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/* Disable SDRAM write buffer */
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movw $0x0040, %di /* SC520_DBCTL */
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movw $(SC520_DBCTL - SC520_MMCR_BASE), %di
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xorw %ax, %ax
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xorw %ax, %ax
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movb %al, (%di)
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movb %al, (%di)
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