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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

This commit is contained in:
Wolfgang Denk 2010-04-27 22:57:41 +02:00
parent c88d6ab19f 7e1afb62a7
commit c303176aa0
17 changed files with 202 additions and 63 deletions
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2
arch/powerpc/cpu/mpc83xx/serdes.c
View File

@ -15,7 +15,7 @@
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>
/* SerDes registers */
#define FSL_SRDSCR0_OFFS 0x0

18
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2004,2007-2009 Freescale Semiconductor, Inc.
* Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
* (C) Copyright 2002, 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
@ -44,21 +44,19 @@ int checkcpu (void)
uint major, minor;
struct cpu_type *cpu;
char buf1[32], buf2[32];
#ifdef CONFIG_DDR_CLK_FREQ
#if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif /* CONFIG_FSL_CORENET */
#ifdef CONFIG_DDR_CLK_FREQ
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#else
#ifdef CONFIG_FSL_CORENET
u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
#else
u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
#endif
#else
#ifdef CONFIG_FSL_CORENET
u32 ddr_sync = 0;
#else
u32 ddr_ratio = 0;
#endif
#endif /* CONFIG_FSL_CORENET */
#endif /* CONFIG_DDR_CLK_FREQ */
int i;

51
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -180,54 +180,54 @@ void cpu_init_f (void)
* has been determined
*/
#if defined(CONFIG_SYS_OR0_REMAP)
memctl->or0 = CONFIG_SYS_OR0_REMAP;
out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
#endif
#if defined(CONFIG_SYS_OR1_REMAP)
memctl->or1 = CONFIG_SYS_OR1_REMAP;
out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
#endif
/* now restrict to preliminary range */
/* if cs1 is already set via debugger, leave cs0/cs1 alone */
if (! memctl->br1 & 1) {
#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
memctl->br0 = CONFIG_SYS_BR0_PRELIM;
memctl->or0 = CONFIG_SYS_OR0_PRELIM;
out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
#endif
#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
memctl->or1 = CONFIG_SYS_OR1_PRELIM;
memctl->br1 = CONFIG_SYS_BR1_PRELIM;
out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
#endif
}
#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
memctl->or2 = CONFIG_SYS_OR2_PRELIM;
memctl->br2 = CONFIG_SYS_BR2_PRELIM;
out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
#endif
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
memctl->or3 = CONFIG_SYS_OR3_PRELIM;
memctl->br3 = CONFIG_SYS_BR3_PRELIM;
out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
#endif
#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
memctl->or4 = CONFIG_SYS_OR4_PRELIM;
memctl->br4 = CONFIG_SYS_BR4_PRELIM;
out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
#endif
#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
memctl->or5 = CONFIG_SYS_OR5_PRELIM;
memctl->br5 = CONFIG_SYS_BR5_PRELIM;
out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
#endif
#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
memctl->or6 = CONFIG_SYS_OR6_PRELIM;
memctl->br6 = CONFIG_SYS_BR6_PRELIM;
out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
#endif
#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
memctl->or7 = CONFIG_SYS_OR7_PRELIM;
memctl->br7 = CONFIG_SYS_BR7_PRELIM;
out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
#endif
#if defined(CONFIG_CPM2)
@ -260,6 +260,10 @@ void cpu_init_f (void)
int cpu_init_r(void)
{
#ifdef CONFIG_SYS_LBC_LCRR
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
#endif
puts ("L2: ");
#if defined(CONFIG_L2_CACHE)
@ -383,6 +387,17 @@ int cpu_init_r(void)
#if defined(CONFIG_MP)
setup_mp();
#endif
#ifdef CONFIG_SYS_LBC_LCRR
/*
* Modify the CLKDIV field of LCRR register to improve the writing
* speed for NOR flash.
*/
clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
__raw_readl(&lbc->lcrr);
isync();
#endif
return 0;
}

28
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
* Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
@ -71,22 +71,30 @@ void get_sys_info (sys_info_t * sysInfo)
[14] = 4, /* CC4 PPL / 4 */
};
uint lcrr_div, i, freqCC_PLL[4], rcw_tmp;
uint ratio[4];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
uint mem_pll_rat;
sysInfo->freqSystemBus = sysclk;
sysInfo->freqDDRBus = sysclk;
freqCC_PLL[0] = sysclk;
freqCC_PLL[1] = sysclk;
freqCC_PLL[2] = sysclk;
freqCC_PLL[3] = sysclk;
sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
sysInfo->freqDDRBus *= ((in_be32(&gur->rcwsr[0]) >> 17) & 0x1f);
freqCC_PLL[0] *= (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
freqCC_PLL[1] *= (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
freqCC_PLL[2] *= (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
freqCC_PLL[3] *= (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> 17) & 0x1f;
if (mem_pll_rat > 2)
sysInfo->freqDDRBus *= mem_pll_rat;
else
sysInfo->freqDDRBus = sysInfo->freqSystemBus * mem_pll_rat;
ratio[0] = (in_be32(&clk->pllc1gsr) >> 1) & 0x3f;
ratio[1] = (in_be32(&clk->pllc2gsr) >> 1) & 0x3f;
ratio[2] = (in_be32(&clk->pllc3gsr) >> 1) & 0x3f;
ratio[3] = (in_be32(&clk->pllc4gsr) >> 1) & 0x3f;
for (i = 0; i < 4; i++) {
if (ratio[i] > 4)
freqCC_PLL[i] = sysclk * ratio[i];
else
freqCC_PLL[i] = sysInfo->freqSystemBus * ratio[i];
}
rcw_tmp = in_be32(&gur->rcwsr[3]);
for (i = 0; i < cpu_numcores(); i++) {
u32 c_pll_sel = (in_be32(&clk->clkc0csr + i*8) >> 27) & 0xf;

2
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
View File

@ -198,6 +198,8 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
pre_pd_exit_mclk = act_pd_exit_mclk;
taxpd_mclk = 8;
tmrd_mclk = 4;
/* set the turnaround time */
trwt_mclk = 1;
#else /* CONFIG_FSL_DDR2 */
/*
* (tXARD and tXARDS). Empirical?

13
arch/powerpc/cpu/mpc8xxx/pci_cfg.c
View File

@ -176,15 +176,14 @@ static struct pci_info pci_config_info[] =
(1 << 0x1d) | (1 << 0x1e) | (1 << 0x1f),
},
[LAW_TRGT_IF_PCIE_2] = {
.cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) |
(1 << 9) | (1 << 0xa) | (1 << 0xb) | (1 << 0xd) |
(1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
(1 << 0x18) | (1 << 0x1c),
.cfg = (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) |
(1 << 0xd) | (1 << 0x15) | (1 << 0x16) | (1 << 0x17) |
(1 << 0x18) | (1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
},
[LAW_TRGT_IF_PCIE_3] = {
.cfg = (1 << 6) | (1 << 7) | (1 << 9) | (1 << 0xd) |
(1 << 0x15) | (1 << 0x16) | (1 << 0x17) | (1 << 0x18) |
(1 << 0x19) | (1 << 0x1a) | (1 << 0x1b),
.cfg = (1 << 0) | (1 << 1) | (1 << 6) | (1 << 7) | (1 << 9) |
(1 << 0xa) | (1 << 0xb) | (1 << 0xd) | (1 << 0x15) |
(1 << 0x16) | (1 << 0x17) | (1 << 0x18) | (1 << 0x1c),
},
};
#elif defined(CONFIG_P2010) || defined(CONFIG_P2020)

8
arch/powerpc/include/asm/fsl_ddr_sdram.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2008-2009 Freescale Semiconductor, Inc.
* Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@ -24,6 +24,12 @@
#define DDR_OTF 6 /* on-the-fly BC4 and BL8 */
#define DDR_BL8 8 /* burst length 8 */
#define DDR3_RTT_60_OHM 1 /* RTT_Nom = RZQ/4 */
#define DDR3_RTT_120_OHM 2 /* RTT_Nom = RZQ/2 */
#define DDR3_RTT_40_OHM 3 /* RTT_Nom = RZQ/6 */
#define DDR3_RTT_20_OHM 4 /* RTT_Nom = RZQ/12 */
#define DDR3_RTT_30_OHM 5 /* RTT_Nom = RZQ/8 */
#if defined(CONFIG_FSL_DDR1)
#define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR (1)
typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;

6
arch/powerpc/include/asm/fsl_lbc.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
* Copyright (C) 2004-2008,2010 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -125,8 +125,12 @@
#define OR_GPCM_SETA_SHIFT 3
#define OR_GPCM_TRLX 0x00000004
#define OR_GPCM_TRLX_SHIFT 2
#define OR_GPCM_TRLX_CLEAR 0x00000000
#define OR_GPCM_TRLX_SET 0x00000004
#define OR_GPCM_EHTR 0x00000002
#define OR_GPCM_EHTR_SHIFT 1
#define OR_GPCM_EHTR_CLEAR 0x00000000
#define OR_GPCM_EHTR_SET 0x00000002
#define OR_GPCM_EAD 0x00000001
#define OR_GPCM_EAD_SHIFT 0

36
arch/powerpc/include/asm/fsl_mpc83xx_serdes.h Normal file
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@ -0,0 +1,36 @@
/*
* Copyright 2010 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __FSL_MPC83XX_SERDES_H
#define __FSL_MPC83XX_SERDES_H
#include <config.h>
#define FSL_SERDES_CLK_100 (0 << 28)
#define FSL_SERDES_CLK_125 (1 << 28)
#define FSL_SERDES_CLK_150 (3 << 28)
#define FSL_SERDES_PROTO_SATA 0
#define FSL_SERDES_PROTO_PEX 1
#define FSL_SERDES_PROTO_PEX_X2 2
#define FSL_SERDES_PROTO_SGMII 3
#define FSL_SERDES_VDD_1V 1
extern void fsl_setup_serdes(u32 offset, char proto, u32 rfcks, char vdd);
#endif /* __FSL_MPC83XX_SERDES_H */

53
arch/powerpc/include/asm/immap_85xx.h
View File

@ -1,7 +1,7 @@
/*
* MPC85xx Internal Memory Map
*
* Copyright 2007-2009 Freescale Semiconductor, Inc.
* Copyright 2007-2010 Freescale Semiconductor, Inc.
*
* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
@ -1647,7 +1647,7 @@ typedef struct ccsr_gur {
u8 res4[12];
u32 gpindr; /* General-purpose input data */
u8 res5[12];
u32 pmuxcr; /* Alt function signal multiplex control */
u32 alt_pmuxcr; /* Alt function signal multiplex control */
u8 res6[12];
u32 devdisr; /* Device disable control */
#define FSL_CORENET_DEVDISR_PCIE1 0x80000000
@ -1672,7 +1672,23 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR_I2C2 0x00000010
#define FSL_CORENET_DEVDISR_DUART1 0x00000002
#define FSL_CORENET_DEVDISR_DUART2 0x00000001
u8 res7[12];
u32 devdisr2; /* Device disable control 2 */
#define FSL_CORENET_DEVDISR2_PME 0x80000000
#define FSL_CORENET_DEVDISR2_SEC 0x40000000
#define FSL_CORENET_DEVDISR2_QMBM 0x08000000
#define FSL_CORENET_DEVDISR2_FM1 0x02000000
#define FSL_CORENET_DEVDISR2_10GEC1 0x01000000
#define FSL_CORENET_DEVDISR2_DTSEC1_1 0x00800000
#define FSL_CORENET_DEVDISR2_DTSEC1_2 0x00400000
#define FSL_CORENET_DEVDISR2_DTSEC1_3 0x00200000
#define FSL_CORENET_DEVDISR2_DTSEC1_4 0x00100000
#define FSL_CORENET_DEVDISR2_FM2 0x00020000
#define FSL_CORENET_DEVDISR2_10GEC2 0x00010000
#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00008000
#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00004000
#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00002000
#define FSL_CORENET_DEVDISR2_DTSEC2_4 0x00001000
u8 res7[8];
u32 powmgtcsr; /* Power management status & control */
u8 res8[12];
u32 coredisru; /* uppper portion for support of 64 cores */
@ -1697,8 +1713,9 @@ typedef struct ccsr_gur {
u8 res17[24];
u32 rcwsr[16]; /* Reset control word status */
#define FSL_CORENET_RCWSR4_SRDS_PRTCL 0xfc000000
#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00008000
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 15
#define FSL_CORENET_RCWSR5_DDR_SYNC 0x00000080
#define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT 7
#define FSL_CORENET_RCWSR5_SRDS_EN 0x00002000
#define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT 0x00400000
#define FSL_CORENET_RCWSR8_HOST_AGT_B1 0x00e00000
#define FSL_CORENET_RCWSR8_HOST_AGT_B2 0x00100000
@ -1750,7 +1767,17 @@ typedef struct ccsr_gur {
u32 cgencrl; /* Core general control */
u8 res31[184];
u32 sriopstecr; /* SRIO prescaler timer enable control */
u8 res32[2300];
u8 res32[1788];
u32 pmuxcr; /* Pin multiplexing control */
u8 res33[60];
u32 iovselsr; /* I/O voltage selection status */
u8 res34[28];
u32 ddrclkdr; /* DDR clock disable */
u8 res35;
u32 elbcclkdr; /* eLBC clock disable */
u8 res36[20];
u32 sdhcpcr; /* eSDHC polarity configuration */
u8 res37[380];
} ccsr_gur_t;
typedef struct ccsr_clk {
@ -1846,8 +1873,13 @@ typedef struct ccsr_gur {
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
#define MPC85xx_PORDEVSR_PCI1 0x00800000
#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
#else
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
#endif
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000
@ -1942,7 +1974,15 @@ typedef struct serdes_corenet {
#define SRDS_RSTCTL_RST 0x80000000
#define SRDS_RSTCTL_RSTDONE 0x40000000
#define SRDS_RSTCTL_RSTERR 0x20000000
#define SRDS_RSTCTL_SDPD 0x00000020
u32 pllcr0; /* PLL Control Register 0 */
#define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000
#define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
#define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
#define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000
#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
#define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000
u32 pllcr1; /* PLL Control Register 1 */
#define SRDS_PLLCR1_PLL_BWSEL 0x08000000
u32 res[5];
@ -2018,6 +2058,7 @@ enum {
#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x210000
#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000
#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000
#define CONFIG_SYS_TSEC1_OFFSET 0x4e0000 /* FM1@DTSEC0 */
#else
#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000
#define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x2000

2
board/freescale/mpc837xemds/mpc837xemds.c
View File

@ -14,7 +14,7 @@
#include <hwconfig.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>
#include <spd_sdram.h>
#include <tsec.h>
#include <libfdt.h>

2
board/freescale/mpc837xemds/pci.c
View File

@ -18,7 +18,7 @@
#include <i2c.h>
#include <fdt_support.h>
#include <asm/fsl_i2c.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>
static struct pci_region pci_regions[] = {
{

2
board/freescale/mpc837xerdb/mpc837xerdb.c
View File

@ -16,7 +16,7 @@
#include <hwconfig.h>
#include <i2c.h>
#include <asm/io.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_mpc83xx_serdes.h>
#include <fdt_support.h>
#include <spd_sdram.h>
#include <vsc7385.h>

4
board/freescale/p1_p2_rdb/p1_p2_rdb.c
View File

@ -198,6 +198,8 @@ int board_eth_init(bd_t *bis)
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
extern void ft_pci_board_setup(void *blob);
void ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
@ -208,6 +210,8 @@ void ft_board_setup(void *blob, bd_t *bd)
base = getenv_bootm_low();
size = getenv_bootm_size();
ft_pci_board_setup(blob);
fdt_fixup_memory(blob, (u64)base, (u64)size);
}
#endif

22
drivers/block/fsl_sata.c
View File

@ -21,6 +21,7 @@
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <malloc.h>
#include <libata.h>
#include <fis.h>
@ -191,6 +192,27 @@ int init_sata(int dev)
/* Wait the controller offline */
ata_wait_register(&reg->hstatus, HSTATUS_ONOFF, 0, 1000);
#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
/*
* For P1022/1013 Rev1.0 silicon, after power on SATA host
* controller is configured in legacy mode instead of the
* expected enterprise mode. software needs to clear bit[28]
* of HControl register to change to enterprise mode from
* legacy mode.
*/
{
u32 svr = get_svr();
if (IS_SVR_REV(svr, 1, 0) &&
((SVR_SOC_VER(svr) == SVR_P1022) ||
(SVR_SOC_VER(svr) == SVR_P1022_E) ||
(SVR_SOC_VER(svr) == SVR_P1013) ||
(SVR_SOC_VER(svr) == SVR_P1013_E))) {
out_le32(&reg->hstatus, 0x20000000);
out_le32(&reg->hcontrol, 0x00000100);
}
}
#endif
/* Set the command header base address to CHBA register to tell DMA */
out_le32(&reg->chba, (u32)cmd_hdr & ~0x3);

8
drivers/block/fsl_sata.h
View File

@ -243,8 +243,12 @@ typedef struct prd_entry {
/* ext_c_ddc
*/
#define PRD_ENTRY_EXT 0x80000000 /* extension flag or called indirect descriptor flag */
#define PRD_ENTRY_DATA_SNOOP 0x00400000 /* Snoop enable for all data associated with the PRD entry */
#define PRD_ENTRY_EXT 0x80000000 /* extension flag */
#ifdef CONFIG_FSL_SATA_V2
#define PRD_ENTRY_DATA_SNOOP 0x10000000 /* Data snoop enable */
#else
#define PRD_ENTRY_DATA_SNOOP 0x00400000 /* Data snoop enable */
#endif
#define PRD_ENTRY_LEN_MASK 0x003fffff /* Data word count */
#define PRD_ENTRY_MAX_XFER_SZ (PRD_ENTRY_LEN_MASK + 1)

8
include/configs/socrates.h
View File

@ -174,7 +174,7 @@
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
/* FPGA and NAND */
@ -342,19 +342,19 @@
*/
#include <config_cmd_default.h>
#define CONFIG_CMD_BMP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DTT
#undef CONFIG_CMD_EEPROM
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_I2C
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#undef CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_USB
#define CONFIG_CMD_EXT2 /* EXT2 Support */
#define CONFIG_CMD_BMP
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI