ARM: DRA7: EMIF: Add 4GB DDR settings
The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the same. Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
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@ -34,6 +34,8 @@
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#define board_is_dra74x_evm() board_ti_is("5777xCPU")
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#define board_is_dra74x_evm() board_ti_is("5777xCPU")
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#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \
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#define board_is_dra74x_revh_or_later() board_is_dra74x_evm() && \
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(strncmp("H", board_ti_get_rev(), 1) <= 0)
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(strncmp("H", board_ti_get_rev(), 1) <= 0)
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#define board_ti_get_emif_size() board_ti_get_emif1_size() + \
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board_ti_get_emif2_size()
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#ifdef CONFIG_DRIVER_TI_CPSW
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#ifdef CONFIG_DRIVER_TI_CPSW
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#include <cpsw.h>
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#include <cpsw.h>
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@ -125,17 +127,77 @@ static const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
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.emif_rd_wr_exec_thresh = 0x00000305
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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};
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const struct emif_regs emif1_ddr3_532_mhz_1cs_2G = {
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.sdram_config_init = 0x61851ab2,
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.sdram_config = 0x61851ab2,
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.sdram_config2 = 0x08000000,
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.ref_ctrl = 0x000040F1,
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.ref_ctrl_final = 0x00001035,
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.sdram_tim1 = 0xCCCF36B3,
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.sdram_tim2 = 0x30BF7FDA,
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.sdram_tim3 = 0x427F8BA8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x0007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0024400B,
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.emif_ddr_phy_ctlr_1 = 0x0E24400B,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
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.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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const struct emif_regs emif2_ddr3_532_mhz_1cs_2G = {
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.sdram_config_init = 0x61851B32,
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.sdram_config = 0x61851B32,
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.sdram_config2 = 0x08000000,
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.ref_ctrl = 0x000040F1,
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.ref_ctrl_final = 0x00001035,
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.sdram_tim1 = 0xCCCF36B3,
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.sdram_tim2 = 0x308F7FDA,
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.sdram_tim3 = 0x427F88A8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x0007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0024400B,
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.emif_ddr_phy_ctlr_1 = 0x0E24400B,
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.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
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.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
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.emif_ddr_ext_phy_ctrl_4 = 0x009B009B,
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.emif_ddr_ext_phy_ctrl_5 = 0x009E009E,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
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void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
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{
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{
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u64 ram_size;
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ram_size = board_ti_get_emif_size();
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switch (omap_revision()) {
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switch (omap_revision()) {
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case DRA752_ES1_0:
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case DRA752_ES1_0:
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case DRA752_ES1_1:
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case DRA752_ES1_1:
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case DRA752_ES2_0:
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case DRA752_ES2_0:
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switch (emif_nr) {
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switch (emif_nr) {
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case 1:
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case 1:
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if (ram_size > CONFIG_MAX_MEM_MAPPED)
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*regs = &emif1_ddr3_532_mhz_1cs_2G;
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else
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*regs = &emif1_ddr3_532_mhz_1cs;
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*regs = &emif1_ddr3_532_mhz_1cs;
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break;
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break;
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case 2:
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case 2:
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if (ram_size > CONFIG_MAX_MEM_MAPPED)
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*regs = &emif2_ddr3_532_mhz_1cs_2G;
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else
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*regs = &emif2_ddr3_532_mhz_1cs;
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*regs = &emif2_ddr3_532_mhz_1cs;
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break;
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break;
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}
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}
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@ -164,12 +226,27 @@ static const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
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.is_ma_present = 0x1
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.is_ma_present = 0x1
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};
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};
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const struct dmm_lisa_map_regs lisa_map_dra7_2GB = {
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_1 = 0x0,
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.dmm_lisa_map_2 = 0x80740300,
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.dmm_lisa_map_3 = 0xFF020100,
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.is_ma_present = 0x1
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};
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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{
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{
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u64 ram_size;
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ram_size = board_ti_get_emif_size();
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switch (omap_revision()) {
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switch (omap_revision()) {
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case DRA752_ES1_0:
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case DRA752_ES1_0:
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case DRA752_ES1_1:
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case DRA752_ES1_1:
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case DRA752_ES2_0:
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case DRA752_ES2_0:
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if (ram_size > CONFIG_MAX_MEM_MAPPED)
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*dmm_lisa_regs = &lisa_map_dra7_2GB;
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else
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*dmm_lisa_regs = &lisa_map_dra7_1536MB;
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*dmm_lisa_regs = &lisa_map_dra7_1536MB;
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break;
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break;
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case DRA722_ES1_0:
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case DRA722_ES1_0:
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