sysmobts-v2: Correct the DAVINCI_A1CR_VAL8 value
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@ -38,7 +38,7 @@
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#define DAVINCI_AWCCR_VAL (0x000000FF) /* EMIF-A async wait cycle config register value. */
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#define DAVINCI_AWCCR_VAL (0x000000FF) /* EMIF-A async wait cycle config register value. */
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#define DAVINCI_A1CR (0x01E00010) /* EMIF-A CS2 config register. */
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#define DAVINCI_A1CR (0x01E00010) /* EMIF-A CS2 config register. */
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#define DAVINCI_A1CR_VAL (0x44502280) /* EMIF-A CS2 value for NAND. */
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#define DAVINCI_A1CR_VAL (0x44502280) /* EMIF-A CS2 value for NAND. */
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#define DAVINCI_A1CR_VAL8 (0x44502280) /* EMIF-A CS2 value for NAND. */
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#define DAVINCI_A1CR_VAL8 (0x44522290) /* EMIF-A CS2 value for NAND. */
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#define DAVINCI_A2CR (0x01E00014) /* EMIF-A CS3 config register. */
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#define DAVINCI_A2CR (0x01E00014) /* EMIF-A CS3 config register. */
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#define DAVINCI_A2CR_VAL (0x00430491) /* EMIF-A CS3 value for FPGA. */
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#define DAVINCI_A2CR_VAL (0x00430491) /* EMIF-A CS3 value for FPGA. */
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#define DAVINCI_A2CR_VAL8 (0x00630591) /* EMIF-A CS3 value for FPGA. */
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#define DAVINCI_A2CR_VAL8 (0x00630591) /* EMIF-A CS3 value for FPGA. */
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