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ARM: AM43xx: GP-EVM: Correct GPIO used for VTT regulator control 

Schematic indicates GPIO5_7 is to be used for VTT regulator control
rather than GPIO0_21 so modify enable_vtt_regulator to reflect this.
Without this some boards will experience DDR3 corruption and fail to
boot.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
[trini: Rework patch against mainline]
Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
Dave Gerlach 2014-02-10 11:41:49 -05:00 committed by Tom Rini
parent 072cefe07d
commit cd8341b7eb
6 changed files with 24 additions and 14 deletions
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6
arch/arm/cpu/armv7/am33xx/board.c
View File

@ -36,11 +36,15 @@
DECLARE_GLOBAL_DATA_PTR;
static const struct gpio_bank gpio_bank_am33xx[4] = {
static const struct gpio_bank gpio_bank_am33xx[] = {
{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
#ifdef CONFIG_AM43XX
{ (void *)AM33XX_GPIO4_BASE, METHOD_GPIO_24XX },
{ (void *)AM33XX_GPIO5_BASE, METHOD_GPIO_24XX },
#endif
};
const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;

2
arch/arm/cpu/armv7/am33xx/clock_am43xx.c
View File

@ -94,6 +94,8 @@ void enable_basic_clocks(void)
&cmper->gpio1clkctrl,
&cmper->gpio2clkctrl,
&cmper->gpio3clkctrl,
&cmper->gpio4clkctrl,
&cmper->gpio5clkctrl,
&cmper->i2c1clkctrl,
&cmper->emiffwclkctrl,
&cmper->emifclkctrl,

6
arch/arm/include/asm/arch-am33xx/cpu.h
View File

@ -353,7 +353,11 @@ struct cm_perpll {
unsigned int gpio2clkctrl; /* offset 0x480 */
unsigned int resv20;
unsigned int gpio3clkctrl; /* offset 0x488 */
unsigned int resv21[7];
unsigned int resv41;
unsigned int gpio4clkctrl; /* offset 0x490 */
unsigned int resv42;
unsigned int gpio5clkctrl; /* offset 0x498 */
unsigned int resv21[3];
unsigned int i2c1clkctrl; /* offset 0x4A8 */
unsigned int resv22;

4
arch/arm/include/asm/arch-am33xx/gpio.h
View File

@ -12,8 +12,8 @@
#define AM33XX_GPIO1_BASE 0x4804C000
#define AM33XX_GPIO2_BASE 0x481AC000
#define AM33XX_GPIO3_BASE 0x481AE000
#define GPIO_22 22
#define AM33XX_GPIO4_BASE 0x48320000
#define AM33XX_GPIO5_BASE 0x48322000
/* GPIO CTRL register */
#define GPIO_CTRL_DISABLEMODULE_SHIFT 0

14
board/ti/am43xx/board.c
View File

@ -346,14 +346,14 @@ static void enable_vtt_regulator(void)
u32 temp;
/* enable module */
writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO0_BASE + OMAP_GPIO_CTRL);
writel(GPIO_CTRL_ENABLEMODULE, AM33XX_GPIO5_BASE + OMAP_GPIO_CTRL);
/* enable output for GPIO0_22 */
writel(GPIO_SETDATAOUT(GPIO_22),
AM33XX_GPIO0_BASE + OMAP_GPIO_SETDATAOUT);
temp = readl(AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
temp = temp & ~(GPIO_OE_ENABLE(GPIO_22));
writel(temp, AM33XX_GPIO0_BASE + OMAP_GPIO_OE);
/* enable output for GPIO5_7 */
writel(GPIO_SETDATAOUT(7),
AM33XX_GPIO5_BASE + OMAP_GPIO_SETDATAOUT);
temp = readl(AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
temp = temp & ~(GPIO_OE_ENABLE(7));
writel(temp, AM33XX_GPIO5_BASE + OMAP_GPIO_OE);
}
void sdram_init(void)

6
board/ti/am43xx/mux.c
View File

@ -33,8 +33,8 @@ static struct module_pin_mux i2c0_pin_mux[] = {
{-1},
};
static struct module_pin_mux gpio0_22_pin_mux[] = {
{OFFSET(ddr_ba2), (MODE(9) | PULLUP_EN)}, /* GPIO0_22 */
static struct module_pin_mux gpio5_7_pin_mux[] = {
{OFFSET(spi0_cs0), (MODE(7) | PULLUP_EN)}, /* GPIO5_7 */
{-1},
};
@ -49,7 +49,7 @@ void enable_board_pin_mux(void)
configure_module_pin_mux(i2c0_pin_mux);
if (board_is_gpevm())
configure_module_pin_mux(gpio0_22_pin_mux);
configure_module_pin_mux(gpio5_7_pin_mux);
}
void enable_i2c0_pin_mux(void)