mx6qsabreauto: Add parallel NOR flash support
mx6sabreauto boards come with 32 MiB of parallel NOR flash. Add support for it: U-Boot 2015.01-rc1-18107-g1543636-dirty (Nov 14 2014 - 11:11:04) CPU: Freescale i.MX6Q rev1.2 at 792 MHz Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB Flash: 32 MiB NAND: 0 MiB Due to pin conflict with I2C3, only define configure I2C3 IOMUX when flash is not used. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Fabio Estevam
Stefano Babic
parent
573960aca5
commit
cdbdde3f56
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@ -53,6 +53,10 @@ DECLARE_GLOBAL_DATA_PTR;
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
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@ -97,6 +101,7 @@ static struct i2c_pads_info i2c_pad_info1 = {
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}
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};
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#ifndef CONFIG_SYS_FLASH_CFI
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/*
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* I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
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* Compass Sensor, Accelerometer, Res Touch
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@ -113,6 +118,7 @@ static struct i2c_pads_info i2c_pad_info2 = {
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.gp = IMX_GPIO_NR(3, 18)
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}
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};
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#endif
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static iomux_v3_cfg_t const i2c3_pads[] = {
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MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
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@ -160,6 +166,75 @@ static int port_exp_direction_output(unsigned gpio, int value)
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return 0;
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}
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static iomux_v3_cfg_t const eimnor_pads[] = {
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MX6_PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL) ,
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MX6_PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL),
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MX6_PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL),
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MX6_PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void eimnor_cs_setup(void)
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{
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struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
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writel(0x00020181, &weim_regs->cs0gcr1);
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writel(0x00000001, &weim_regs->cs0gcr2);
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writel(0x0a020000, &weim_regs->cs0rcr1);
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writel(0x0000c000, &weim_regs->cs0rcr2);
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writel(0x0804a240, &weim_regs->cs0wcr1);
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writel(0x00000120, &weim_regs->wcr);
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set_chipselect_size(CS0_128);
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}
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static void setup_iomux_eimnor(void)
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{
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imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));
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gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
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eimnor_cs_setup();
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}
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static void setup_iomux_enet(void)
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{
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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
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@ -402,6 +477,7 @@ int board_early_init_f(void)
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#ifdef CONFIG_NAND_MXS
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setup_gpmi_nand();
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#endif
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return 0;
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}
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@ -415,11 +491,13 @@ int board_init(void)
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/* I2C 3 Steer */
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gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
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imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
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#ifndef CONFIG_SYS_FLASH_CFI
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setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
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#endif
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gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
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imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
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setup_iomux_eimnor();
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return 0;
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}
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@ -37,6 +37,16 @@
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#include "mx6sabre_common.h"
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#undef CONFIG_SYS_NO_FLASH
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#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
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#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
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#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#if defined(CONFIG_ENV_IS_IN_MMC)
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#define CONFIG_SYS_MMC_ENV_DEV 0
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