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u-boot
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Merge branch 'denx'

This commit is contained in:
Andy Fleming 2008-02-13 18:36:27 -06:00 committed by Andrew Fleming-AFLEMING
parent ed2cf548ca 10bbb38a40
commit d1bcf9e53b
72 changed files with 534 additions and 270 deletions
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23
Makefile
View File

@ -253,9 +253,7 @@ LIBS += $(shell if [ -d post/board/$(BOARDDIR) ]; then echo \
"post/board/$(BOARDDIR)/libpost$(BOARD).a"; fi)
LIBS += common/libcommon.a
LIBS += libfdt/libfdt.a
ifeq ($(CONFIG_API),y)
LIBS += api/libapi.a
endif
LIBS := $(addprefix $(obj),$(LIBS))
.PHONY : $(LIBS)
@ -266,11 +264,8 @@ PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -
# The "tools" are needed early, so put this first
# Don't include stuff already done in $(LIBS)
SUBDIRS = tools \
examples
ifeq ($(CONFIG_API),y)
SUBDIRS += api_examples
endif
examples \
api_examples
.PHONY : $(SUBDIRS)
@ -2467,20 +2462,8 @@ versatileab_config \
versatilepb_config : unconfig
@board/versatile/split_by_variant.sh $@
voiceblue_smallflash_config \
voiceblue_config: unconfig
@mkdir -p $(obj)include
@mkdir -p $(obj)board/voiceblue
@if [ "$(findstring _smallflash_,$@)" ] ; then \
$(XECHO) "... boot from lower flash bank" ; \
echo "#define VOICEBLUE_SMALL_FLASH" >>$(obj)include/config.h ; \
echo "VOICEBLUE_SMALL_FLASH=y" >$(obj)board/voiceblue/config.tmp ; \
else \
$(XECHO) "... boot from upper flash bank" ; \
>$(obj)include/config.h ; \
echo "VOICEBLUE_SMALL_FLASH=n" >$(obj)board/voiceblue/config.tmp ; \
fi
@$(MKCONFIG) -a voiceblue arm arm925t voiceblue
@$(MKCONFIG) $(@:_config=) arm arm925t voiceblue
cm4008_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm920t cm4008 NULL ks8695

5
api/Makefile
View File

@ -24,13 +24,12 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libapi.a
COBJS = api.o api_net.o api_storage.o api_platform-$(ARCH).o
COBJS-$(CONFIG_API) += api.o api_net.o api_storage.o api_platform-$(ARCH).o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
all: $(LIB)
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)

20
api_examples/Makefile
View File

@ -30,19 +30,25 @@ endif
include $(TOPDIR)/config.mk
ELF += demo
BIN += demo.bin
ELF-$(CONFIG_API) += demo
BIN-$(CONFIG_API) += demo.bin
ELF := $(ELF-y)
BIN := $(BIN-y)
#CFLAGS += -v
COBJS := $(ELF:=.o)
SOBJS := crt0.o
COBJS-$(CONFIG_API) += $(ELF:=.o)
SOBJS-$(CONFIG_API) += crt0.o
ifeq ($(ARCH),ppc)
SOBJS += ppcstring.o
SOBJS-$(CONFIG_API) += ppcstring.o
endif
COBJS := $(COBJS-y)
SOBJS := $(SOBJS-y)
LIB = $(obj)libglue.a
LIBCOBJS= glue.o crc32.o ctype.o string.o vsprintf.o libgenwrap.o
LIBCOBJS-$(CONFIG_API) += glue.o crc32.o ctype.o string.o vsprintf.o \
libgenwrap.o
LIBCOBJS := $(LIBCOBJS-y)
LIBOBJS = $(addprefix $(obj),$(SOBJS) $(LIBCOBJS))
@ -55,7 +61,7 @@ gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
CPPFLAGS += -I..
all: $(obj).depend $(OBJS) $(LIB) $(BIN) $(ELF)
all: $(obj).depend $(OBJS) $(LIB) $(ELF) $(BIN)
#########################################################################
$(LIB): $(obj).depend $(LIBOBJS)

7
api_examples/libgenwrap.c
View File

@ -84,7 +84,12 @@ void do_reset (void)
ub_reset();
}
void *malloc(size_t len)
void *malloc (size_t len)
{
return NULL;
}
void hang (void)
{
while (1) ;
}

34
board/ads5121/ads5121.c
View File

@ -126,24 +126,24 @@ long int fixed_sdram (void)
im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
/* Initialize MDDRC */
@ -156,19 +156,27 @@ long int fixed_sdram (void)
for (i = 0; i < 10; i++)
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_RFSH;
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_RFSH;
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_EM2;
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CFG_MICRON_EM2;
im->mddrc.ddr_command = CFG_MICRON_EM3;
im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
im->mddrc.ddr_command = CFG_MICRON_RST_DLL;
im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CFG_MICRON_RFSH;
im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
im->mddrc.ddr_command = CFG_MICRON_OCD_EXIT;
for (i = 0; i < 10; i++)
im->mddrc.ddr_command = CFG_MICRON_NOP;
im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
im->mddrc.ddr_command = CFG_MICRON_NOP;
/* Start MDDRC */
im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;

2
board/voiceblue/Makefile
View File

@ -62,7 +62,7 @@ clean:
distclean: clean
rm -f $(LIB) core config.tmp *.bak .depend
rm -f $(LIB) core *.bak .depend
#########################################################################

15
board/voiceblue/config.mk
View File

@ -1,16 +1 @@
#
# Linux-Kernel is expected to be at 1000'8000,
# entry 1000'8000 (mem base + reserved)
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifeq ($(VOICEBLUE_SMALL_FLASH),y)
# We load ourself to internal SRAM at 2001'2000
# Check map file when changing TEXT_BASE.
# Everything has fit into 192kB internal SRAM!
TEXT_BASE = 0x20012000
else
# Running in SDRAM...
TEXT_BASE = 0x13FD0000
endif

2
board/voiceblue/setup.S
View File

@ -77,7 +77,7 @@ MUX_CONFIG_VALUES:
.word 0x00000000 @ FUNC_MUX_CTRL_3
.word 0x00000000 @ FUNC_MUX_CTRL_4
.word 0x12082480 @ FUNC_MUX_CTRL_5
.word 0x00000004 @ FUNC_MUX_CTRL_6
.word 0x0000001c @ FUNC_MUX_CTRL_6
.word 0x00000003 @ FUNC_MUX_CTRL_7
.word 0x10001200 @ FUNC_MUX_CTRL_8
.word 0x01201012 @ FUNC_MUX_CTRL_9

2
board/xsengine/xsengine.c
View File

@ -47,7 +47,7 @@ int board_init (void)
return 0;
}
int board_post_init (void)
int board_late_init (void)
{
setenv ("stdout", "serial");
setenv ("stderr", "serial");

2
common/cmd_bdinfo.c
View File

@ -316,6 +316,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
print_num("-> size", bd->bi_dram[i].size);
}
#if defined(CONFIG_CMD_NET)
puts ("ethaddr =");
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
@ -323,6 +324,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
puts ( "\n"
"ip_addr = ");
print_IPaddr (bd->bi_ip_addr);
#endif
printf ("\n"
"baudrate = %d bps\n", bd->bi_baudrate);

2
common/cmd_net.c
View File

@ -51,7 +51,7 @@ int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
U_BOOT_CMD(
tftpboot, 3, 1, do_tftpb,
"tftpboot- boot image via network using TFTP protocol\n",
"[loadAddress] [bootfilename]\n"
"[loadAddress] [[hostIPaddr:]bootfilename]\n"
);
int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])

15
common/serial.c
View File

@ -60,6 +60,16 @@ struct serial_device *__default_serial_console (void)
#else
return &serial0_device;
#endif
#elif defined(CONFIG_S3C2410)
#if defined(CONFIG_SERIAL1)
return &s3c24xx_serial0_device;
#elif defined(CONFIG_SERIAL2)
return &s3c24xx_serial1_device;
#elif defined(CONFIG_SERIAL3)
return &s3c24xx_serial2_device;
#else
#error "CONFIG_SERIAL? missing."
#endif
#else
#error No default console
#endif
@ -122,6 +132,11 @@ void serial_initialize (void)
#endif
#if defined (CONFIG_STUART)
serial_register(&serial_stuart_device);
#endif
#if defined(CONFIG_S3C2410)
serial_register(&s3c24xx_serial0_device);
serial_register(&s3c24xx_serial1_device);
serial_register(&s3c24xx_serial2_device);
#endif
serial_assign (default_serial_console ()->name);
}

7
cpu/arm920t/interrupts.c
View File

@ -161,11 +161,16 @@ void do_fiq (struct pt_regs *pt_regs)
void do_irq (struct pt_regs *pt_regs)
{
#if defined (CONFIG_USE_IRQ) && defined (CONFIG_ARCH_INTEGRATOR)
#if defined (CONFIG_USE_IRQ)
#if defined (ARM920_IRQ_CALLBACK)
ARM920_IRQ_CALLBACK();
return;
#elif defined (CONFIG_ARCH_INTEGRATOR)
/* ASSUMED to be a timer interrupt */
/* Just clear it - count handled in */
/* integratorap.c */
*(volatile ulong *)(CFG_TIMERBASE + 0x0C) = 0;
#endif /* ARCH_INTEGRATOR */
#else
printf ("interrupt request\n");
show_regs (pt_regs);

2
cpu/arm920t/s3c24x0/Makefile
View File

@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS = i2c.o interrupts.o serial.o speed.o \
usb.o usb_ohci.o
usb.o usb_ohci.o nand.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

9
cpu/arm920t/s3c24x0/interrupts.c
View File

@ -216,4 +216,13 @@ void reset_cpu (ulong ignored)
/*NOTREACHED*/
}
#ifdef CONFIG_USE_IRQ
void s3c2410_irq(void)
{
S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT();
u_int32_t intpnd = irq->INTPND;
}
#endif /* USE_IRQ */
#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */

179
cpu/arm920t/s3c24x0/nand.c Normal file
View File

@ -0,0 +1,179 @@
/*
* (C) Copyright 2006 OpenMoko, Inc.
* Author: Harald Welte <laforge@openmoko.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if 0
#define DEBUGN printf
#else
#define DEBUGN(x, args ...) {}
#endif
#if defined(CONFIG_CMD_NAND)
#if !defined(CFG_NAND_LEGACY)
#include <nand.h>
#include <s3c2410.h>
#define __REGb(x) (*(volatile unsigned char *)(x))
#define __REGi(x) (*(volatile unsigned int *)(x))
#define NF_BASE 0x4e000000
#define NFCONF __REGi(NF_BASE + 0x0)
#define NFCMD __REGb(NF_BASE + 0x4)
#define NFADDR __REGb(NF_BASE + 0x8)
#define NFDATA __REGb(NF_BASE + 0xc)
#define NFSTAT __REGb(NF_BASE + 0x10)
#define NFECC0 __REGb(NF_BASE + 0x14)
#define NFECC1 __REGb(NF_BASE + 0x15)
#define NFECC2 __REGb(NF_BASE + 0x16)
#define S3C2410_NFCONF_EN (1<<15)
#define S3C2410_NFCONF_512BYTE (1<<14)
#define S3C2410_NFCONF_4STEP (1<<13)
#define S3C2410_NFCONF_INITECC (1<<12)
#define S3C2410_NFCONF_nFCE (1<<11)
#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd)
{
struct nand_chip *chip = mtd->priv;
DEBUGN("hwcontrol(): 0x%02x: ", cmd);
switch (cmd) {
case NAND_CTL_SETNCE:
NFCONF &= ~S3C2410_NFCONF_nFCE;
DEBUGN("NFCONF=0x%08x\n", NFCONF);
break;
case NAND_CTL_CLRNCE:
NFCONF |= S3C2410_NFCONF_nFCE;
DEBUGN("NFCONF=0x%08x\n", NFCONF);
break;
case NAND_CTL_SETALE:
chip->IO_ADDR_W = NF_BASE + 0x8;
DEBUGN("SETALE\n");
break;
case NAND_CTL_SETCLE:
chip->IO_ADDR_W = NF_BASE + 0x4;
DEBUGN("SETCLE\n");
break;
default:
chip->IO_ADDR_W = NF_BASE + 0xc;
break;
}
return;
}
static int s3c2410_dev_ready(struct mtd_info *mtd)
{
DEBUGN("dev_ready\n");
return (NFSTAT & 0x01);
}
#ifdef CONFIG_S3C2410_NAND_HWECC
void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
{
DEBUGN("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd ,mode);
NFCONF |= S3C2410_NFCONF_INITECC;
}
static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
u_char *ecc_code)
{
ecc_code[0] = NFECC0;
ecc_code[1] = NFECC1;
ecc_code[2] = NFECC2;
DEBUGN("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
return 0;
}
static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
u_char *read_ecc, u_char *calc_ecc)
{
if (read_ecc[0] == calc_ecc[0] &&
read_ecc[1] == calc_ecc[1] &&
read_ecc[2] == calc_ecc[2])
return 0;
printf("s3c2410_nand_correct_data: not implemented\n");
return -1;
}
#endif
int board_nand_init(struct nand_chip *nand)
{
u_int32_t cfg;
u_int8_t tacls, twrph0, twrph1;
S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
DEBUGN("board_nand_init()\n");
clk_power->CLKCON |= (1 << 4);
/* initialize hardware */
twrph0 = 3; twrph1 = 0; tacls = 0;
cfg = S3C2410_NFCONF_EN;
cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
NFCONF = cfg;
/* initialize nand_chip data structure */
nand->IO_ADDR_R = nand->IO_ADDR_W = 0x4e00000c;
/* read_buf and write_buf are default */
/* read_byte and write_byte are default */
/* hwcontrol always must be implemented */
nand->hwcontrol = s3c2410_hwcontrol;
nand->dev_ready = s3c2410_dev_ready;
#ifdef CONFIG_S3C2410_NAND_HWECC
nand->enable_hwecc = s3c2410_nand_enable_hwecc;
nand->calculate_ecc = s3c2410_nand_calculate_ecc;
nand->correct_data = s3c2410_nand_correct_data;
nand->eccmode = NAND_ECC_HW3_512;
#else
nand->eccmode = NAND_ECC_SOFT;
#endif
#ifdef CONFIG_S3C2410_NAND_BBT
nand->options = NAND_USE_FLASH_BBT;
#else
nand->options = 0;
#endif
DEBUGN("end of nand_init\n");
return 0;
}
#else
#error "U-Boot legacy NAND support not available for S3C2410"
#endif
#endif

168
cpu/arm920t/s3c24x0/serial.c
View File

@ -48,18 +48,74 @@ DECLARE_GLOBAL_DATA_PTR;
#error "Bad: you didn't configure serial ..."
#endif
void serial_setbrg (void)
#if defined(CONFIG_SERIAL_MULTI)
#include <serial.h>
/* Multi serial device functions */
#define DECLARE_S3C_SERIAL_FUNCTIONS(port) \
int s3serial##port##_init (void) {\
return serial_init_dev(port);}\
void s3serial##port##_setbrg (void) {\
serial_setbrg_dev(port);}\
int s3serial##port##_getc (void) {\
return serial_getc_dev(port);}\
int s3serial##port##_tstc (void) {\
return serial_tstc_dev(port);}\
void s3serial##port##_putc (const char c) {\
serial_putc_dev(port, c);}\
void s3serial##port##_puts (const char *s) {\
serial_puts_dev(port, s);}
#define INIT_S3C_SERIAL_STRUCTURE(port,name,bus) {\
name,\
bus,\
s3serial##port##_init,\
s3serial##port##_setbrg,\
s3serial##port##_getc,\
s3serial##port##_tstc,\
s3serial##port##_putc,\
s3serial##port##_puts, }
#endif /* CONFIG_SERIAL_MULTI */
void _serial_setbrg(const int dev_index)
{
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
int i;
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
unsigned int reg = 0;
int i;
/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
reg = get_PCLK() / (16 * gd->baudrate) - 1;
uart->UBRDIV = reg;
for (i = 0; i < 100; i++);
}
#if defined(CONFIG_SERIAL_MULTI)
static inline void
serial_setbrg_dev(unsigned int dev_index)
{
_serial_setbrg(dev_index);
}
#else
void serial_setbrg(void)
{
_serial_setbrg(UART_NR);
}
#endif
/* Initialise the serial port. The settings are always 8 data bits, no parity,
* 1 stop bit, no start bits.
*/
static int serial_init_dev(const int dev_index)
{
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
int i;
/* FIFO enable, Tx/Rx FIFO clear */
uart->UFCON = 0x07;
uart->UMCON = 0x0;
/* Normal,No parity,1 stop,8 bit */
uart->ULCON = 0x3;
/*
@ -67,40 +123,57 @@ void serial_setbrg (void)
* normal,interrupt or polling
*/
uart->UCON = 0x245;
uart->UBRDIV = reg;
#ifdef CONFIG_HWFLOW
uart->UMCON = 0x1; /* RTS up */
#endif
for (i = 0; i < 100; i++);
}
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
int serial_init (void)
{
serial_setbrg ();
/* FIXME: This is sooooooooooooooooooo ugly */
#if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2)
/* we need auto hw flow control on the gsm and gps port */
if (dev_index == 0 || dev_index == 1)
uart->UMCON = 0x10;
#endif
_serial_setbrg(dev_index);
return (0);
}
#if !defined(CONFIG_SERIAL_MULTI)
/* Initialise the serial port. The settings are always 8 data bits, no parity,
* 1 stop bit, no start bits.
*/
int serial_init (void)
{
return serial_init_dev(UART_NR);
}
#endif
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
int serial_getc (void)
int _serial_getc (const int dev_index)
{
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
/* wait for character to arrive */
while (!(uart->UTRSTAT & 0x1));
return uart->URXH & 0xff;
}
#if defined(CONFIG_SERIAL_MULTI)
static inline int serial_getc_dev(unsigned int dev_index)
{
return _serial_getc(dev_index);
}
#else
int serial_getc (void)
{
return _serial_getc(UART_NR);
}
#endif
#ifdef CONFIG_HWFLOW
static int hwflow = 0; /* turned off by default */
@ -138,9 +211,9 @@ void enable_putc(void)
/*
* Output a single byte to the serial port.
*/
void serial_putc (const char c)
void _serial_putc (const char c, const int dev_index)
{
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
#ifdef CONFIG_MODEM_SUPPORT
if (be_quiet)
return;
@ -161,23 +234,72 @@ void serial_putc (const char c)
if (c == '\n')
serial_putc ('\r');
}
#if defined(CONFIG_SERIAL_MULTI)
static inline void serial_putc_dev(unsigned int dev_index, const char c)
{
_serial_putc(c, dev_index);
}
#else
void serial_putc(const char c)
{
_serial_putc(c, UART_NR);
}
#endif
/*
* Test whether a character is in the RX buffer
*/
int serial_tstc (void)
int _serial_tstc(const int dev_index)
{
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
return uart->UTRSTAT & 0x1;
}
#if defined(CONFIG_SERIAL_MULTI)
static inline int
serial_tstc_dev(unsigned int dev_index)
{
return _serial_tstc(dev_index);
}
#else
int serial_tstc(void)
{
return _serial_tstc(UART_NR);
}
#endif
void _serial_puts(const char *s, const int dev_index)
{
while (*s) {
_serial_putc (*s++, dev_index);
}
}
#if defined(CONFIG_SERIAL_MULTI)
static inline void
serial_puts_dev(int dev_index, const char *s)
{
_serial_puts(s, dev_index);
}
#else
void
serial_puts (const char *s)
{
while (*s) {
serial_putc (*s++);
}
_serial_puts(s, UART_NR);
}
#endif
#if defined(CONFIG_SERIAL_MULTI)
DECLARE_S3C_SERIAL_FUNCTIONS(0);
struct serial_device s3c24xx_serial0_device =
INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0", "S3UART1");
DECLARE_S3C_SERIAL_FUNCTIONS(1);
struct serial_device s3c24xx_serial1_device =
INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1", "S3UART2");
DECLARE_S3C_SERIAL_FUNCTIONS(2);
struct serial_device s3c24xx_serial2_device =
INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2", "S3UART3");
#endif /* CONFIG_SERIAL_MULTI */
#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */

10
cpu/arm920t/start.S
View File

@ -329,12 +329,12 @@ cpu_init_crit:
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
add r8, sp, #S_PC
stmdb r8, {sp, lr}^ @ Calling SP, LR
str lr, [r8, #0] @ Save calling PC
add r7, sp, #S_PC
stmdb r7, {sp, lr}^ @ Calling SP, LR
str lr, [r7, #0] @ Save calling PC
mrs r6, spsr
str r6, [r8, #4] @ Save CPSR
str r0, [r8, #8] @ Save OLD_R0
str r6, [r7, #4] @ Save CPSR
str r0, [r7, #8] @ Save OLD_R0
mov r0, sp
.endm

6
cpu/mpc512x/cpu.c
View File

@ -138,11 +138,11 @@ void ft_cpu_setup(void *blob, bd_t *bd)
do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
do_fixup_by_path_u32(blob, cpu_path, "ref-frequency", CFG_MPC512X_CLKIN, 1);
do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipsfreq, 1);
do_fixup_by_path_u32(blob, "/" OF_SOC, "ref-frequency", CFG_MPC512X_CLKIN, 1);
do_fixup_by_path(blob, eth_path, "address", bd->bi_enetaddr, 6, 0);
do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0);
/* this is so old kernels with old device trees will boot */
do_fixup_by_path_u32(blob, "/" OF_SOC_OLD, "bus-frequency", bd->bi_ipsfreq, 0);
}
#endif

16
drivers/serial/ns16550.c
View File

@ -21,11 +21,15 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
com_port->mdr1 = 0x7; /* mode select reset TL16C750*/
#endif
com_port->lcr = LCR_BKSE | LCRVAL;
com_port->dll = baud_divisor & 0xff;
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->dll = 0;
com_port->dlm = 0;
com_port->lcr = LCRVAL;
com_port->mcr = MCRVAL;
com_port->fcr = FCRVAL;
com_port->lcr = LCR_BKSE | LCRVAL;
com_port->dll = baud_divisor & 0xff;
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCRVAL;
#if defined(CONFIG_OMAP)
#if defined(CONFIG_APTIX)
com_port->mdr1 = 3; /* /13 mode so Aptix 6MHz can hit 115200 */
@ -38,12 +42,16 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
void NS16550_reinit (NS16550_t com_port, int baud_divisor)
{
com_port->ier = 0x00;
com_port->lcr = LCR_BKSE | LCRVAL;
com_port->dll = 0;
com_port->dlm = 0;
com_port->lcr = LCRVAL;
com_port->mcr = MCRVAL;
com_port->fcr = FCRVAL;
com_port->lcr = LCR_BKSE;
com_port->dll = baud_divisor & 0xff;
com_port->dlm = (baud_divisor >> 8) & 0xff;
com_port->lcr = LCRVAL;
com_port->mcr = MCRVAL;
com_port->fcr = FCRVAL;
}
void NS16550_putc (NS16550_t com_port, char c)

4
drivers/spi/mpc8xxx_spi.c
View File

@ -22,11 +22,11 @@
*/
#include <common.h>
#if defined(CONFIG_MPC8XXX_SPI) && defined(CONFIG_HARD_SPI)
#include <spi.h>
#include <asm/mpc8xxx_spi.h>
#ifdef CONFIG_HARD_SPI
#define SPI_EV_NE (0x80000000 >> 22) /* Receiver Not Empty */
#define SPI_EV_NF (0x80000000 >> 23) /* Transmitter Not Full */

2
include/common.h
View File

@ -479,6 +479,8 @@ ulong get_OPB_freq (void);
ulong get_PCI_freq (void);
#endif
#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || defined(CONFIG_LH7A40X)
void s3c2410_irq(void);
#define ARM920_IRQ_CALLBACK s3c2410_irq
ulong get_FCLK (void);
ulong get_HCLK (void);
ulong get_PCLK (void);

2
include/configs/AP1000.h
View File

@ -22,8 +22,6 @@
* (easy to change)
*/
#undef DEBUG
#define CONFIG_405 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */

1
include/configs/BAB7xx.h
View File

@ -28,7 +28,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
#define GTREGREAD(x) 0xffffffff /* needed for debug */
/*

2
include/configs/EB+MCF-EV123.h
View File

@ -27,9 +27,7 @@
#define CONFIG_EB_MCF_EV123
#undef DEBUG
#undef CFG_HALT_BEFOR_RAM_JUMP
#undef ET_DEBUG
/*
* High Level Configuration Options (easy to change)

1
include/configs/ELPPC.h
View File

@ -28,7 +28,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
#define GTREGREAD(x) 0xffffffff /* needed for debug */
/*

2
include/configs/IPHASE4539.h
View File

@ -30,8 +30,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG /* General debug */
/*-----------------------------------------------------------------------
* High Level Configuration Options
* (easy to change)

2
include/configs/M52277EVB.h
View File

@ -38,8 +38,6 @@
#define CONFIG_M52277 /* define processor type */
#define CONFIG_M52277EVB /* M52277EVB board */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200

2
include/configs/M5235EVB.h
View File

@ -37,8 +37,6 @@
#define CONFIG_MCF523x /* define processor family */
#define CONFIG_M5235 /* define processor type */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200

2
include/configs/M5271EVB.h
View File

@ -31,8 +31,6 @@
#ifndef _M5271EVB_H
#define _M5271EVB_H
#undef DEBUG
/*
* High Level Configuration Options (easy to change)
*/

2
include/configs/M5329EVB.h
View File

@ -37,8 +37,6 @@
#define CONFIG_MCF532x /* define processor family */
#define CONFIG_M5329 /* define processor type */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200

2
include/configs/M5373EVB.h
View File

@ -37,8 +37,6 @@
#define CONFIG_MCF532x /* define processor family */
#define CONFIG_M5373 /* define processor type */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200

2
include/configs/M54455EVB.h
View File

@ -38,8 +38,6 @@
#define CONFIG_M54455 /* define processor type */
#define CONFIG_M54455EVB /* M54455EVB board */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200

2
include/configs/M5475EVB.h
View File

@ -38,8 +38,6 @@
#define CONFIG_M547x /* define processor type */
#define CONFIG_M5475 /* define processor type */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200

2
include/configs/M5485EVB.h
View File

@ -38,8 +38,6 @@
#define CONFIG_M548x /* define processor type */
#define CONFIG_M5485 /* define processor type */
#undef DEBUG
#define CONFIG_MCFUART
#define CFG_UART_PORT (0)
#define CONFIG_BAUDRATE 115200

2
include/configs/MPC8315ERDB.h
View File

@ -25,8 +25,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/*
* High Level Configuration Options
*/

2
include/configs/MPC8323ERDB.h
View File

@ -9,8 +9,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/*
* High Level Configuration Options
*/

2
include/configs/MPC832XEMDS.h
View File

@ -20,8 +20,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/*
* High Level Configuration Options
*/

3
include/configs/MPC8349EMDS.h
View File

@ -29,8 +29,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/*
* High Level Configuration Options
*/
@ -356,6 +354,7 @@
#define CFG_I2C2_OFFSET 0x3100
/* SPI */
#define CONFIG_MPC8XXX_SPI
#define CONFIG_HARD_SPI /* SPI with hardware support */
#undef CONFIG_SOFT_SPI /* SPI bit-banged */

2
include/configs/MPC8360EMDS.h
View File

@ -22,8 +22,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/*
* High Level Configuration Options
*/

2
include/configs/MPC8360ERDK.h
View File

@ -17,8 +17,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/*
* High Level Configuration Options
*/

2
include/configs/MPC837XEMDS.h
View File

@ -21,8 +21,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/*
* High Level Configuration Options
*/

2
include/configs/MPC8540EVAL.h
View File

@ -240,8 +240,6 @@
#define INTEL_LXT971_PHY 1
#endif
#undef DEBUG
/* Environment */
#ifndef CFG_RAMBOOT
#if defined(CONFIG_RAM_AS_FLASH)

2
include/configs/MVBLUE.h
View File

@ -53,8 +53,6 @@
#define ERR_LED(code)
#endif
#undef DEBUG
#define CONFIG_MPC824X 1
#define CONFIG_MPC8245 1
#define CONFIG_MVBLUE 1

1
include/configs/QS823.h
View File

@ -38,7 +38,6 @@
#undef CFG_DEVICE_NULLDEV /* null device */
#undef CONFIG_SILENT_CONSOLE /* silent console */
#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
#undef DEBUG /* debug output code */
#undef DEBUG_FLASH /* debug flash code */
#undef FLASH_DEBUG /* debug fash code */
#undef DEBUG_ENV /* debug environment code */

1
include/configs/QS850.h
View File

@ -38,7 +38,6 @@
#undef CFG_DEVICE_NULLDEV /* null device */
#undef CONFIG_SILENT_CONSOLE /* silent console */
#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
#undef DEBUG /* debug output code */
#undef DEBUG_FLASH /* debug flash code */
#undef FLASH_DEBUG /* debug fash code */
#undef DEBUG_ENV /* debug environment code */

1
include/configs/QS860T.h
View File

@ -38,7 +38,6 @@
#undef CFG_DEVICE_NULLDEV /* null device */
#undef CONFIG_SILENT_CONSOLE /* silent console */
#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
#undef DEBUG /* debug output code */
#undef DEBUG_FLASH /* debug flash code */
#undef FLASH_DEBUG /* debug fash code */
#undef DEBUG_ENV /* debug environment code */

2
include/configs/Rattler.h
View File

@ -37,8 +37,6 @@
#define CONFIG_RATTLER /* Analogue&Micro Rattler board */
#undef DEBUG
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
#define CONFIG_ENV_OVERWRITE

7
include/configs/TQM834x.h
View File

@ -181,7 +181,7 @@ extern int tqm834x_num_flash_banks;
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc */
/*
* Serial Port
@ -302,7 +302,7 @@ extern int tqm834x_num_flash_banks;
#ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#else
#define CFG_NO_FLASH 1 /* Flash is not usable now */
@ -335,6 +335,7 @@ extern int tqm834x_num_flash_banks;
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#if defined(CONFIG_PCI)
#define CONFIG_CMD_PCI
@ -557,7 +558,7 @@ extern int tqm834x_num_flash_banks;
#define MTDIDS_DEFAULT "nor0=TQM834x-0"
/* default mtd partition table */
#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),128k(env),"\
#define MTDPARTS_DEFAULT "mtdparts=TQM834x-0:256k(u-boot),256k(env),"\
"1m(kernel),2m(initrd),"\
"-(user);"\

23
include/configs/ads5121.h
View File

@ -27,9 +27,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#define DEBUG
#undef DEBUG
/*
* Memory map for the ADS5121 board:
*
@ -109,25 +106,22 @@
* [04:00] DRAM tRPA
*/
#define CFG_MDDRC_SYS_CFG 0xF8604200
#define CFG_MDDRC_SYS_CFG_RUN 0xE8604200
#define CFG_MDDRC_SYS_CFG_EN 0x30000000
#define CFG_MDDRC_TIME_CFG0 0x0000281E
#define CFG_MDDRC_TIME_CFG0_RUN 0x01F4281E
#define CFG_MDDRC_SYS_CFG 0xF8604A00
#define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00
#define CFG_MDDRC_SYS_CFG_EN 0xF0000000
#define CFG_MDDRC_TIME_CFG0 0x00003D2E
#define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E
#define CFG_MDDRC_TIME_CFG1 0x54EC1168
#define CFG_MDDRC_TIME_CFG2 0x35210864
#define CFG_MICRON_NOP 0x01380000
#define CFG_MICRON_PCHG_ALL 0x01100400
#define CFG_MICRON_MR 0x01000022
#define CFG_MICRON_EM2 0x01020000
#define CFG_MICRON_EM3 0x01030000
#define CFG_MICRON_EN_DLL 0x01010000
#define CFG_MICRON_RST_DLL 0x01000932
#define CFG_MICRON_RFSH 0x01080000
#define CFG_MICRON_INIT_DEV_OP 0x01000832
#define CFG_MICRON_INIT_DEV_OP 0x01000432
#define CFG_MICRON_OCD_DEFAULT 0x01010780
#define CFG_MICRON_OCD_EXIT 0x01010400
/* DDR Priority Manager Configuration */
#define CFG_MDDRCGRP_PM_CFG1 0x000777AA
@ -415,8 +409,9 @@
#define CONFIG_OF_BOARD_SETUP 1
#define OF_CPU "PowerPC,5121@0"
#define OF_SOC "soc5121@80000000"
#define OF_SOC "soc@80000000"
#define OF_SOC_OLD "soc5121@80000000"
#define OF_TBCLK (bd->bi_busfreq / 4)
#define OF_STDOUT_PATH "/soc5121@80000000/serial@11300"
#define OF_STDOUT_PATH "/soc@80000000/serial@11300"
#endif /* __CONFIG_H */

2
include/configs/assabet.h
View File

@ -29,8 +29,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/*
* High Level Configuration Options
* (easy to change)

2
include/configs/ep8248.h
View File

@ -31,8 +31,6 @@
#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
#undef DEBUG
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */

2
include/configs/ep82xxm.h
View File

@ -31,8 +31,6 @@
#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */
/* 256MB SDRAM / 64MB FLASH */
#undef DEBUG
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */

2
include/configs/gcplus.h
View File

@ -29,8 +29,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/*
* The ADS GCPlus Linux boot ROM loads U-Boot into RAM at 0xc0200000.
* We don't actually init RAM in this case since we're using U-Boot as

1
include/configs/gw8260.h
View File

@ -51,7 +51,6 @@
#define __CONFIG_H
/* Enable debug prints */
#undef DEBUG /* General debug */
#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
/* What is the oscillator's (UX2) frequency in Hz? */

2
include/configs/mgcoge.h
View File

@ -35,8 +35,6 @@
#define CONFIG_CPM2 1 /* Has a CPM2 */
#undef DEBUG
/*
* Select serial console configuration
*

2
include/configs/mpc7448hpc2.h
View File

@ -33,8 +33,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/* Board Configuration Definitions */
/* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */

1
include/configs/ms7720se.h
View File

@ -25,7 +25,6 @@
#ifndef __MS7720SE_H
#define __MS7720SE_H
#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH3 1
#define CONFIG_CPU_SH7720 1

1
include/configs/ms7722se.h
View File

@ -25,7 +25,6 @@
#ifndef __MS7722SE_H
#define __MS7722SE_H
#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH4 1
#define CONFIG_CPU_SH7722 1

1
include/configs/ms7750se.h
View File

@ -25,7 +25,6 @@
#ifndef __MS7750SE_H
#define __MS7750SE_H
#undef DEBUG
#define CONFIG_SH 1
#define CONFIG_SH4 1
#define CONFIG_CPU_SH7750 1

1
include/configs/ppmc7xx.h
View File

@ -30,7 +30,6 @@
* do_bdinfo - Required to build with debug
*/
#undef DEBUG
#ifdef DEBUG
#define GTREGREAD(x) 0xFFFFFFFF
#define do_bdinfo(a,b,c,d)

2
include/configs/qemu-mips.h
View File

@ -32,8 +32,6 @@
#define CONFIG_QEMU_MIPS 1
#define CONFIG_MISC_INIT_R
#undef DEBUG
/*IP address is default used by Qemu*/
#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address*/

1
include/configs/sacsng.h
View File

@ -35,7 +35,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG /* General debug */
#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
#undef CONFIG_LOGBUFFER /* External logbuffer support */

1
include/configs/sbc8260.h
View File

@ -36,7 +36,6 @@
#define __CONFIG_H
/* Enable debug prints */
#undef DEBUG /* General debug */
#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
/*****************************************************************************

2
include/configs/sbc8349.h
View File

@ -31,8 +31,6 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/*
* High Level Configuration Options
*/

100
include/configs/voiceblue.h
View File

@ -26,10 +26,6 @@
#include <configs/omap1510.h>
/*
* High Level Configuration Options
* (easy to change)
*/
#define CONFIG_ARM925T 1 /* This is an arm925t CPU */
#define CONFIG_OMAP 1 /* in a TI OMAP core */
#define CONFIG_OMAP1510 1 /* which is in a 5910 */
@ -54,10 +50,9 @@
*/
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE SZ_64M
#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024)
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define PHYS_FLASH_2 0x0c000000
#define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */
@ -67,50 +62,34 @@
#define CFG_FLASH_CFI /* Flash is CFI conformant */
#define CFG_FLASH_CFI_DRIVER /* Use the common driver */
#define CFG_MAX_FLASH_BANKS 1
#ifdef VOICEBLUE_SMALL_FLASH
#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_2 }
#else
#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
#endif
#define CFG_FLASH_BASE PHYS_FLASH_1
/* FIXME: Does not work on AMD flash */
/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_SECT 512 /* max # of sectors on one chip */
#define CFG_MONITOR_BASE PHYS_FLASH_1
#define CFG_MONITOR_LEN SZ_128K
#define CFG_MONITOR_LEN (256 * 1024)
/*
* Environment settings
*/
#ifdef VOICEBLUE_SMALL_FLASH
#define CFG_ENV_IS_NOWHERE
#define CFG_ENV_SIZE SZ_1K
#else
#define CFG_ENV_IS_IN_FLASH
#define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN)
#define CFG_ENV_SIZE SZ_8K
#define CFG_ENV_SECT_SIZE SZ_64K
#define CFG_ENV_SIZE (8 * 1024)
#define CFG_ENV_SECT_SIZE (64 * 1024)
#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
#define CONFIG_ENV_OVERWRITE
#endif
/*
* Size of malloc() pool and stack
*/
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
#ifdef VOICEBLUE_SMALL_FLASH
#define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)
#define CONFIG_STACKSIZE SZ_8K
#define PHYS_SDRAM_1_RESERVED 0
#else
#define CFG_MALLOC_LEN SZ_4M
#define CONFIG_STACKSIZE SZ_1M
#define CFG_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_STACKSIZE (1 * 1024 * 1024)
#define PHYS_SDRAM_1_RESERVED (CFG_MONITOR_LEN + CFG_MALLOC_LEN + CONFIG_STACKSIZE)
#endif
/*
* Hardware drivers
@ -118,6 +97,14 @@
#define CONFIG_DRIVER_SMC91111
#define CONFIG_SMC91111_BASE 0x08000300
#define CONFIG_HARD_I2C
#define CFG_I2C_SPEED 100000
#define CFG_I2C_SLAVE 1
#define CONFIG_DRIVER_OMAP1510_I2C
#define CONFIG_RTC_DS1307
#define CFG_I2C_RTC_ADDR 0x68
/*
* NS16550 Configuration
*/
@ -138,21 +125,18 @@
#include <config_cmd_default.h>
#define CONFIG_CMD_BDI
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_IMI
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_IMI
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_RUN
#if !defined(VOICEBLUE_SMALL_FLASH)
#define CONFIG_CMD_ENV
#define CONFIG_CMD_JFFS2
#endif
/*
* BOOTP options
@ -165,32 +149,20 @@
#define CONFIG_LOOPW
#ifdef VOICEBLUE_SMALL_FLASH
#define CONFIG_BOOTDELAY 0
#undef CONFIG_BOOTARGS /* the preboot command will set bootargs*/
#define CFG_AUTOLOAD "n" /* no autoload */
#define CONFIG_PREBOOT "run setup"
#define CONFIG_EXTRA_ENV_SETTINGS \
"setup=setenv bootargs console=ttyS0,${baudrate} " \
"root=/dev/nfs ip=dhcp\0" \
"update=erase c000000 c03ffff; " \
"cp.b 10400000 c000000 ${filesize}\0"
#else
#define CONFIG_BOOTDELAY 3
#undef CONFIG_BOOTARGS /* boot command will set bootargs */
#define CFG_AUTOLOAD "n" /* no autoload */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow to break in always */
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
#define CFG_AUTOLOAD "n" /* No autoload */
#define CONFIG_BOOTCOMMAND "run nboot"
#define CONFIG_PREBOOT "run setup"
#define CONFIG_EXTRA_ENV_SETTINGS \
"silent=1\0" \
"ospart=0\0" \
"swapos=no\0" \
"bootfile=/boot/uImage\0" \
"setpart=" \
"if test $swapos = yes; then " \
"if test $ospart -eq 0; then chpart 4; else chpart 3; fi; "\
"setenv swapos no; saveenv; " \
"else " \
"if test $ospart -eq 0; then chpart 3; else chpart 4; fi; "\
"if test -n $swapos; then " \
"setenv swapos; saveenv; " \
"if test $ospart -eq 0; then setenv ospart 1; else setenv ospart 0; fi; "\
"fi\0" \
"setup=setenv bootargs console=ttyS0,$baudrate " \
"mtdparts=$mtdparts\0" \
@ -198,16 +170,14 @@
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
"nfsroot=$rootpath root=/dev/nfs\0" \
"flashargs=run setpart; setenv bootargs $bootargs " \
"root=/dev/mtdblock$partition ro " \
"root=mtd:data$ospart ro " \
"rootfstype=jffs2\0" \
"initrdargs=setenv bootargs $bootargs " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off\0" \
"fboot=run flashargs; fsload /boot/uImage; bootm\0" \
"iboot=bootp; run initrdargs; tftp; bootm\0" \
"fboot=run flashargs; chpart data$ospart; fsload; bootm\0" \
"mboot=bootp; run initrdargs; tftp; bootm\0" \
"nboot=bootp; run nfsargs; tftp; bootm\0"
#endif
#ifndef VOICEBLUE_SMALL_FLASH
#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
#if 1 /* feel free to disable for development */
@ -221,19 +191,15 @@
*/
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT "nor0=omapflash.0"
#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:128k(uboot),64k(env),64k(r_env),16256k(data1),-(data2)"
#endif /* VOICEBLUE_SMALL_FLASH */
#define MTDPARTS_DEFAULT "mtdparts=omapflash.0:256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)"
/*
* Miscellaneous configurable options
*/
#ifndef VOICEBLUE_SMALL_FLASH
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#define CONFIG_AUTO_COMPLETE
#endif
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "# " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */

2
include/configs/xsengine.h
View File

@ -33,7 +33,7 @@
#define CONFIG_XSENGINE 1
#define CONFIG_MMC 1
#define CONFIG_DOS_PARTITION 1
#define BOARD_POST_INIT 1
#define OARD_LATE_INIT 1
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */

2
include/mpc512x.h
View File

@ -185,7 +185,7 @@
/* SCFR1 System Clock Frequency Register 1
*/
#define SCFR1_IPS_DIV 0x4
#define SCFR1_IPS_DIV 0x3
#define SCFR1_IPS_DIV_MASK 0x03800000
#define SCFR1_IPS_DIV_SHIFT 23

5
include/serial.h
View File

@ -36,6 +36,11 @@ extern struct serial_device eserial4_device;
#endif
#if defined(CONFIG_S3C2410)
extern struct serial_device s3c24xx_serial0_device;
extern struct serial_device s3c24xx_serial1_device;
extern struct serial_device s3c24xx_serial2_device;
#endif
extern struct serial_device serial_ffuart_device;
extern struct serial_device serial_btuart_device;

18
lib_arm/board.c
View File

@ -84,6 +84,11 @@ extern void cs8900_get_enetaddr (uchar * addr);
extern void rtl8019_get_enetaddr (uchar * addr);
#endif
#if defined(CONFIG_HARD_I2C) || \
defined(CONFIG_SOFT_I2C)
#include <i2c.h>
#endif
/*
* Begin and End of memory area for malloc(), and current "brk"
*/
@ -209,6 +214,16 @@ static void display_flash_config (ulong size)
}
#endif /* CFG_NO_FLASH */
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
static int init_func_i2c (void)
{
puts ("I2C: ");
i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
puts ("ready\n");
return (0);
}
#endif
/*
* Breathe some life into the board...
*
@ -250,6 +265,9 @@ init_fnc_t *init_sequence[] = {
#endif
#if defined(CONFIG_DISPLAY_BOARDINFO)
checkboard, /* display board info */
#endif
#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
init_func_i2c,
#endif
dram_init, /* configure available RAM banks */
display_dram_config,

40
net/tftp.c
View File

@ -34,7 +34,7 @@
#define TFTP_ERROR 5
#define TFTP_OACK 6
static IPaddr_t TftpServerIP;
static int TftpServerPort; /* The UDP port at their end */
static int TftpOurPort; /* The UDP port at our end */
static int TftpTimeoutCount;
@ -55,7 +55,14 @@ static int TftpState;
#define DEFAULT_NAME_LEN (8 + 4 + 1)
static char default_filename[DEFAULT_NAME_LEN];
static char *tftp_filename;
#ifndef CONFIG_TFTP_FILE_NAME_MAX_LEN
#define MAX_LEN 128
#else
#define MAX_LEN CONFIG_TFTP_FILE_NAME_MAX_LEN
#endif
static char tftp_filename[MAX_LEN];
#ifdef CFG_DIRECT_FLASH_TFTP
extern flash_info_t flash_info[];
@ -231,7 +238,7 @@ TftpSend (void)
break;
}
NetSendUDPPacket(NetServerEther, NetServerIP, TftpServerPort, TftpOurPort, len);
NetSendUDPPacket(NetServerEther, TftpServerIP, TftpServerPort, TftpOurPort, len);
}
@ -372,7 +379,7 @@ TftpHandler (uchar * pkt, unsigned dest, unsigned src, unsigned len)
#ifdef CONFIG_MCAST_TFTP
/* if I am the MasterClient, actively calculate what my next
* needed block is; else I'm passive; not ACKING
*/
*/
if (Multicast) {
if (len < TftpBlkSize) {
TftpEndingBlock = TftpBlock;
@ -453,30 +460,43 @@ TftpStart (void)
char *ep; /* Environment pointer */
#endif
TftpServerIP = NetServerIP;
if (BootFile[0] == '\0') {
sprintf(default_filename, "%02lX%02lX%02lX%02lX.img",
NetOurIP & 0xFF,
(NetOurIP >> 8) & 0xFF,
(NetOurIP >> 16) & 0xFF,
(NetOurIP >> 24) & 0xFF );
tftp_filename = default_filename;
strncpy(tftp_filename, default_filename, MAX_LEN);
tftp_filename[MAX_LEN-1] = 0;
printf ("*** Warning: no boot file name; using '%s'\n",
tftp_filename);
} else {
tftp_filename = BootFile;
char *p = strchr (p, ':');
if (p == NULL) {
strncpy(tftp_filename, BootFile, MAX_LEN);
tftp_filename[MAX_LEN-1] = 0;
} else {
*p++ = '\0';
TftpServerIP = string_to_ip (BootFile);
strncpy(tftp_filename, p, MAX_LEN);
tftp_filename[MAX_LEN-1] = 0;
}
}
#if defined(CONFIG_NET_MULTI)
printf ("Using %s device\n", eth_get_name());
#endif
puts ("TFTP from server "); print_IPaddr (NetServerIP);
puts ("TFTP from server "); print_IPaddr (TftpServerIP);
puts ("; our IP address is "); print_IPaddr (NetOurIP);
/* Check if we need to send across this subnet */
if (NetOurGatewayIP && NetOurSubnetMask) {
IPaddr_t OurNet = NetOurIP & NetOurSubnetMask;
IPaddr_t ServerNet = NetServerIP & NetOurSubnetMask;
IPaddr_t OurNet = NetOurIP & NetOurSubnetMask;
IPaddr_t ServerNet = TftpServerIP & NetOurSubnetMask;
if (OurNet != ServerNet) {
puts ("; sending through gateway ");
@ -522,7 +542,7 @@ TftpStart (void)
/* Revert TftpBlkSize to dflt */
TftpBlkSize = TFTP_BLOCK_SIZE;
#ifdef CONFIG_MCAST_TFTP
mcast_cleanup();
mcast_cleanup();
#endif
TftpSend ();

4
post/tests.c
View File

@ -241,8 +241,8 @@ struct post_test post_list[] =
{
"ECC test",
"ecc",
"This test checks ECC facility of memory.",
POST_ROM | POST_ALWAYS,
"This test checks the ECC facility of memory.",
POST_ROM | POST_ALWAYS | POST_PREREL,
&ecc_post_test,
NULL,
NULL,