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[MIPS] Initialize CP0 Cause before setting up CP0 Status register 

Without this change, we'll be suffering from deffered WATCH exception
once Status.EXL is cleared. Make sure Cause.WP is cleared.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
This commit is contained in:
Shinya Kuribayashi 2008-03-25 21:30:07 +09:00
parent 2613862323
commit d43d43ef28
1 changed files with 3 additions and 3 deletions
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6
cpu/mips/start.S
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@ -211,6 +211,9 @@ reset:
mtc0 zero, CP0_WATCHLO
mtc0 zero, CP0_WATCHHI
/* WP(Watch Pending), SW0/1 should be cleared. */
mtc0 zero, CP0_CAUSE
/* STATUS register */
#ifdef CONFIG_TB0229
li k0, ST0_CU0
@ -221,9 +224,6 @@ reset:
and k0, k1
mtc0 k0, CP0_STATUS
/* CAUSE register */
mtc0 zero, CP0_CAUSE
/* Init Timer */
mtc0 zero, CP0_COUNT
mtc0 zero, CP0_COMPARE