From 9d1d6a34d26c5933bc097ce73c9348f95573cdd4 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Sat, 21 Apr 2007 20:53:31 +0200
Subject: [PATCH 01/17] Change ML401 parameters - Xilinx BSP

---
 board/xilinx/ml401/config.mk     |  2 +-
 board/xilinx/ml401/xparameters.h | 24 ++++++++++++------------
 2 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/board/xilinx/ml401/config.mk b/board/xilinx/ml401/config.mk
index 807f169fa7..c75daaf0b5 100644
--- a/board/xilinx/ml401/config.mk
+++ b/board/xilinx/ml401/config.mk
@@ -25,7 +25,7 @@
 # Version: Xilinx EDK 6.3 EDK_Gmm.12.3
 #
 
-TEXT_BASE = 0x12000000
+TEXT_BASE = 0x29000000
 
 PLATFORM_CPPFLAGS += -mno-xl-soft-mul
 PLATFORM_CPPFLAGS += -mno-xl-soft-div
diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h
index 18d24f9c1d..4fe36f8a9d 100644
--- a/board/xilinx/ml401/xparameters.h
+++ b/board/xilinx/ml401/xparameters.h
@@ -27,41 +27,41 @@
  */
 
 /* System Clock Frequency */
-#define XILINX_CLOCK_FREQ	66666667
+#define XILINX_CLOCK_FREQ	100000000
 
 /* Interrupt controller is intc_0 */
-#define XILINX_INTC_BASEADDR	0xd1000fc0
-#define XILINX_INTC_NUM_INTR_INPUTS	12
+#define XILINX_INTC_BASEADDR	0x41200000
+#define XILINX_INTC_NUM_INTR_INPUTS	4
 
 /* Timer pheriphery is opb_timer_0 */
-#define XILINX_TIMER_BASEADDR	0xa2000000
+#define XILINX_TIMER_BASEADDR	0x41c00000
 #define XILINX_TIMER_IRQ	0
 
 /* Uart pheriphery is console_uart */
-#define XILINX_UART_BASEADDR	0xa0000000
+#define XILINX_UART_BASEADDR	0x40600000
 #define XILINX_UART_BAUDRATE	115200
 
 /* GPIO is opb_gpio_0*/
 #define XILINX_GPIO_BASEADDR	0x90000000
 
 /* Flash Memory is opb_emc_0 */
-#define XILINX_FLASH_START	0x28000000
+#define XILINX_FLASH_START	0x2c000000
 #define XILINX_FLASH_SIZE	0x00800000
 
 /* Main Memory is plb_ddr_0 */
-#define XILINX_RAM_START	0x10000000
-#define XILINX_RAM_SIZE	0x10000000
+#define XILINX_RAM_START	0x28000000
+#define XILINX_RAM_SIZE	0x04000000
 
 /* Sysace Controller is opb_sysace_0 */
-#define XILINX_SYSACE_BASEADDR	0xCF000000
-#define XILINX_SYSACE_HIGHADDR	0xCF0001FF
+#define XILINX_SYSACE_BASEADDR	0x41800000
+#define XILINX_SYSACE_HIGHADDR	0x4180FFFF
 #define XILINX_SYSACE_MEM_WIDTH	16
 
 /* Ethernet controller is opb_ethernet_0 */
 #define XPAR_XEMAC_NUM_INSTANCES	1
 #define XPAR_OPB_ETHERNET_0_DEVICE_ID	0
-#define XPAR_OPB_ETHERNET_0_BASEADDR	0x60000000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR	0x60003FFF
+#define XPAR_OPB_ETHERNET_0_BASEADDR	0x40c00000
+#define XPAR_OPB_ETHERNET_0_HIGHADDR	0x40c0fFFF
 #define XPAR_OPB_ETHERNET_0_DMA_PRESENT	1
 #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST	1
 #define XPAR_OPB_ETHERNET_0_MII_EXIST	1

From 0643631aa1036cd746bf5d15f5a34bc7bc01ea4f Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Sat, 21 Apr 2007 21:02:40 +0200
Subject: [PATCH 02/17] 16bit read/write little endian

---
 cpu/microblaze/start.S | 33 +++++++++++++++++++++++++++++++++
 include/common.h       |  4 ++++
 2 files changed, 37 insertions(+)

diff --git a/cpu/microblaze/start.S b/cpu/microblaze/start.S
index 29481af9ae..453815818d 100644
--- a/cpu/microblaze/start.S
+++ b/cpu/microblaze/start.S
@@ -117,3 +117,36 @@ clear_bss:
 3:	/* jumping to board_init */
 	brai	board_init
 1:	bri	1b
+
+/*
+ * Read 16bit little endian
+ */
+	.text
+	.global	in16
+	.ent	in16
+	.align	2
+in16:	lhu	r3, r0, r5
+	bslli	r4, r3, 8
+	bsrli	r3, r3, 8
+	andi	r4, r4, 0xffff
+	or	r3, r3, r4
+	rtsd	r15, 8
+	sext16	r3, r3
+	.end	in16
+
+/*
+ * Write 16bit little endian
+ * first parameter(r5) - address, second(r6) - short value
+ */
+	.text
+	.global	out16
+	.ent	out16
+	.align	2
+out16:	bslli	r3, r6, 8
+	bsrli	r6, r6, 8
+	andi	r3, r3, 0xffff
+	or	r3, r3, r6
+	sh	r3, r0, r5
+	rtsd	r15, 8
+	or	r0, r0, r0
+	.end	out16
diff --git a/include/common.h b/include/common.h
index b162dbd7cf..40fbba5325 100644
--- a/include/common.h
+++ b/include/common.h
@@ -402,6 +402,10 @@ void		ppcDcbi(unsigned long value);
 void		ppcSync(void);
 void		ppcDcbz(unsigned long value);
 #endif
+#if defined (CONFIG_MICROBLAZE)
+unsigned short	in16(unsigned int);
+void		out16(unsigned int, unsigned short value);
+#endif
 
 #if defined (CONFIG_MPC83XX)
 void		ppcDWload(unsigned int *addr, unsigned int *ret);

From 32556443840f127170e4baa8bdd5b567039f6c36 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Sat, 21 Apr 2007 21:07:22 +0200
Subject: [PATCH 03/17] [PATCH] SystemACE support for Microblaze

---
 drivers/systemace.c      |  6 ++++++
 include/configs/ml401.h  | 26 +++++++++++++++++---------
 include/configs/xupv2p.h | 14 ++++++++------
 3 files changed, 31 insertions(+), 15 deletions(-)

diff --git a/drivers/systemace.c b/drivers/systemace.c
index 3848d9c59c..c9fd5f1670 100644
--- a/drivers/systemace.c
+++ b/drivers/systemace.c
@@ -211,10 +211,16 @@ static unsigned long systemace_read(int dev, unsigned long start,
 		/* Write sector count | ReadMemCardData. */
 		ace_writew((trans & 0xff) | 0x0300, 0x14);
 
+/* 
+ * For FPGA configuration via SystemACE is reset unacceptable
+ * CFGDONE bit in STATUSREG is not set to 1.
+ */
+#ifndef SYSTEMACE_CONFIG_FPGA
 		/* Reset the configruation controller */
 		val = ace_readw(0x18);
 		val |= 0x0080;
 		ace_writew(val, 0x18);
+#endif
 
 		retry = trans * 16;
 		while (retry > 0) {
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index f4a8a1f228..15c2fe7ecd 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -36,7 +36,7 @@
 #define	CFG_BAUDRATE_TABLE	{ CONFIG_BAUDRATE }
 
 /* setting reset address */
-#define	CFG_RESET_ADDRESS	TEXT_BASE
+//#define	CFG_RESET_ADDRESS	TEXT_BASE
 
 /* ethernet */
 #define CONFIG_EMACLITE		1
@@ -66,7 +66,7 @@
  *
  * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
  * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
- * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000 
+ * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
  *
  * 0x1000_0000	CFG_SDRAM_BASE
  *					FREE
@@ -93,7 +93,8 @@
 
 /* global pointer */
 #define	CFG_GBL_DATA_SIZE	0x1000	/* size of global data */
-#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
+/* start of global data */
+#define	CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) 
 
 /* monitor code */
 #define	SIZE			0x40000
@@ -152,6 +153,8 @@
 				CFG_CMD_IMI |\
 				CFG_CMD_NET |\
 				CFG_CMD_CACHE |\
+				CFG_CMD_FAT |\
+				CFG_CMD_EXT2 |\
 				CFG_CMD_IMLS |\
 				CFG_CMD_FLASH |\
 				CFG_CMD_PING \
@@ -174,6 +177,8 @@
 				CFG_CMD_FLASH |\
 				CFG_CMD_PING |\
 				CFG_CMD_ENV |\
+				CFG_CMD_FAT |\
+				CFG_CMD_EXT2 |\
 				CFG_CMD_SAVES \
 				)
 
@@ -189,6 +194,8 @@
 				CFG_CMD_BDI |\
 				CFG_CMD_RUN |\
 				CFG_CMD_LOADS |\
+				CFG_CMD_FAT |\
+				CFG_CMD_EXT2 |\
 				CFG_CMD_LOADB |\
 				CFG_CMD_IMI |\
 				CFG_CMD_NET |\
@@ -221,10 +228,11 @@
 #define CFG_HZ	1000
 
 /* system ace */
-/*#define CONFIG_SYSTEMACE
-#define DEBUG_SYSTEMACE
-#define CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
-#define CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
-#define CONFIG_DOS_PARTITION
-*/
+#define	CONFIG_SYSTEMACE
+/* #define DEBUG_SYSTEMACE */
+#define	SYSTEMACE_CONFIG_FPGA
+#define	CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
+#define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
+#define	CONFIG_DOS_PARTITION
+
 #endif	/* __CONFIG_H */
diff --git a/include/configs/xupv2p.h b/include/configs/xupv2p.h
index 224db5c8be..c89ef7ce5c 100644
--- a/include/configs/xupv2p.h
+++ b/include/configs/xupv2p.h
@@ -132,6 +132,8 @@
 			CFG_CMD_LOADS |\
 			CFG_CMD_LOADB |\
 			CFG_CMD_MISC |\
+			CFG_CMD_FAT |\
+			CFG_CMD_EXT2 |\
 			CFG_CMD_PING \
 			)
 
@@ -163,12 +165,12 @@
 	"base 0;" \
 	"echo"
 
-
 /* system ace */
-/*#define	CONFIG_SYSTEMACE
-#define	DEBUG_SYSTEMACE
-#define	CFG_SYSTEMACE_BASE	0xCF000000
-#define	CFG_SYSTEMACE_WIDTH	16
-#define	CONFIG_DOS_PARTITION*/
+#define	CONFIG_SYSTEMACE
+/* #define DEBUG_SYSTEMACE */
+#define	SYSTEMACE_CONFIG_FPGA
+#define	CFG_SYSTEMACE_BASE	XILINX_SYSACE_BASEADDR
+#define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
+#define	CONFIG_DOS_PARTITION
 
 #endif	/* __CONFIG_H */

From 144876a380f5756f57412caf74c1d6dc201dd796 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Tue, 24 Apr 2007 23:01:02 +0200
Subject: [PATCH 04/17] [PATCH] MTD partition support, JFFS2 support

---
 fs/jffs2/compr_zlib.c   |  2 +-
 include/configs/ml401.h | 29 +++++++++++++++++++++++++++--
 include/linux/stat.h    |  3 ++-
 3 files changed, 30 insertions(+), 4 deletions(-)

diff --git a/fs/jffs2/compr_zlib.c b/fs/jffs2/compr_zlib.c
index 1b35585eee..d88d0f8f36 100644
--- a/fs/jffs2/compr_zlib.c
+++ b/fs/jffs2/compr_zlib.c
@@ -45,7 +45,7 @@
 long zlib_decompress(unsigned char *data_in, unsigned char *cpage_out,
 		      __u32 srclen, __u32 destlen)
 {
-    return (decompress_block(cpage_out, data_in + 2, ldr_memcpy));
+    return (decompress_block(cpage_out, data_in + 2, (void *) ldr_memcpy));
 
 }
 
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index 15c2fe7ecd..acaa1e4f2b 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -40,7 +40,7 @@
 
 /* ethernet */
 #define CONFIG_EMACLITE		1
-#define XPAR_EMAC_0_DEVICE_ID	XPAR_XEMAC_NUM_INSTANCES
+#define XPAR_EMAC_0_DEVICE_ID	XPAR_OPB_ETHERNET_0_DEVICE_ID
 
 /* gpio */
 #define	CFG_GPIO_0		1
@@ -118,6 +118,7 @@
 	#define	CFG_FLASH_EMPTY_INFO	1	/* ?empty sector */
 	#define	CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
 	#define	CFG_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
+	#define	CFG_FLASH_PROTECTION		/* hardware flash protection */
 
 	#ifdef	RAMENV
 		#define	CFG_ENV_IS_NOWHERE	1
@@ -136,6 +137,7 @@
 	#define	CFG_ENV_IS_NOWHERE	1
 	#define	CFG_ENV_SIZE		0x1000
 	#define	CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SIZE)
+	#define	CFG_FLASH_PROTECTION		/* hardware flash protection */
 #endif /* !FLASH */
 
 #ifdef	FLASH
@@ -155,6 +157,8 @@
 				CFG_CMD_CACHE |\
 				CFG_CMD_FAT |\
 				CFG_CMD_EXT2 |\
+				CFG_CMD_JFFS2 |\
+				CFG_CMD_ECHO |\
 				CFG_CMD_IMLS |\
 				CFG_CMD_FLASH |\
 				CFG_CMD_PING \
@@ -179,6 +183,8 @@
 				CFG_CMD_ENV |\
 				CFG_CMD_FAT |\
 				CFG_CMD_EXT2 |\
+				CFG_CMD_JFFS2 |\
+				CFG_CMD_ECHO |\
 				CFG_CMD_SAVES \
 				)
 
@@ -206,6 +212,17 @@
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
 
+#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
+/* JFFS2 partitions */
+#define CONFIG_JFFS2_CMDLINE	/* mtdparts command line support */
+#define MTDIDS_DEFAULT		"nor0=ml401-0"
+
+/* default mtd partition table */
+#define MTDPARTS_DEFAULT	"mtdparts=ml401-0:256k(u-boot),"\
+				"256k(env),3m(kernel),1m(romfs),"\
+				"1m(cramfs),-(jffs2)"
+#endif
+
 /* Miscellaneous configurable options */
 #define	CFG_PROMPT	"U-Boot-mONStR> "
 #define	CFG_CBSIZE	512	/* size of console buffer */
@@ -214,7 +231,7 @@
 #define	CFG_LONGHELP
 #define	CFG_LOAD_ADDR	0x12000000 /* default load address */
 
-#define	CONFIG_BOOTDELAY 	30
+#define	CONFIG_BOOTDELAY	30
 #define	CONFIG_BOOTARGS		"root=romfs"
 #define	CONFIG_HOSTNAME		"ml401"
 #define	CONFIG_BOOTCOMMAND 	"base 0;tftp 11000000 image.img;bootm"
@@ -235,4 +252,12 @@
 #define	CFG_SYSTEMACE_WIDTH	XILINX_SYSACE_MEM_WIDTH
 #define	CONFIG_DOS_PARTITION
 
+#define	CONFIG_PREBOOT		"echo U-BOOT for ML401;setenv preboot;echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS	"unlock=yes\0" /* hardware flash protection */\
+					"nor0=ml401-0\0"\
+					"mtdparts=mtdparts=ml401-0:"\
+					"256k(u-boot),256k(env),3m(kernel),"\
+					"1m(romfs),1m(cramfs),-(jffs2)\0"
+
 #endif	/* __CONFIG_H */
diff --git a/include/linux/stat.h b/include/linux/stat.h
index f9422cb1fa..39386f1220 100644
--- a/include/linux/stat.h
+++ b/include/linux/stat.h
@@ -67,7 +67,8 @@ struct stat {
 
 #endif	/* __PPC__ */
 
-#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__)
+#if defined (__ARM__) || defined (__I386__) || defined (__M68K__) || defined (__blackfin__) ||\
+	defined (__microblaze__)
 
 struct stat {
 	unsigned short st_dev;

From f7e2e0eb0668136305f78bb9c21be79b48a34247 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Sat, 5 May 2007 18:27:16 +0200
Subject: [PATCH 05/17] new: FSL and MSR support

---
 common/cmd_mfsl.c            | 265 +++++++++++++++++++++++++++++++++++
 include/asm-microblaze/asm.h |  37 +++++
 2 files changed, 302 insertions(+)
 create mode 100644 common/cmd_mfsl.c
 create mode 100644 include/asm-microblaze/asm.h

diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c
new file mode 100644
index 0000000000..827b75e6ce
--- /dev/null
+++ b/common/cmd_mfsl.c
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Microblaze FSL support
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/asm.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_MFSL)
+
+int do_frd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int fslnum;
+	unsigned int num;
+	unsigned int blocking;
+
+	if (argc < 2) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	fslnum = (unsigned int)simple_strtoul (argv[1], NULL, 16);
+	blocking = (unsigned int)simple_strtoul (argv[2], NULL, 16);
+	if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) {
+		puts ("Bad number of FSL\n");
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	switch (fslnum) {
+#if (XILINX_FSL_NUMBER > 0)
+	case 0:
+		if (blocking) {
+			GET (num, 0);
+		} else {
+			NGET (num, 0);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 1)
+	case 1:
+		if (blocking) {
+			GET (num, 1);
+		} else {
+			NGET (num, 1);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 2)
+	case 2:
+		if (blocking) {
+			GET (num, 2);
+		} else {
+			NGET (num, 2);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 3)
+	case 3:
+		if (blocking) {
+			GET (num, 3);
+		} else {
+			NGET (num, 3);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 4)
+	case 4:
+		if (blocking) {
+			GET (num, 4);
+		} else {
+			NGET (num, 4);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 5)
+	case 5:
+		if (blocking) {
+			GET (num, 5);
+		} else {
+			NGET (num, 5);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 6)
+	case 6:
+		if (blocking) {
+			GET (num, 6);
+		} else {
+			NGET (num, 6);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 7)
+	case 7:
+		if (blocking) {
+			GET (num, 7);
+		} else {
+			NGET (num, 7);
+		}
+		break;
+#endif
+	default:
+		return 1;
+	}
+
+	printf ("%01x: 0x%08lx - %s read\n", fslnum, num,
+		blocking ? "blocking" : "non blocking");
+	return 0;
+}
+
+int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	unsigned int fslnum;
+	unsigned int num;
+	unsigned int blocking;
+
+	if (argc < 3) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	fslnum = (unsigned int)simple_strtoul (argv[1], NULL, 16);
+	num = (unsigned int)simple_strtoul (argv[2], NULL, 16);
+	blocking = (unsigned int)simple_strtoul (argv[3], NULL, 16);
+	if (fslnum < 0 || fslnum >= XILINX_FSL_NUMBER) {
+		printf ("Bad number of FSL\nUsage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	switch (fslnum) {
+#if (XILINX_FSL_NUMBER > 0)
+	case 0:
+		if (blocking) {
+			PUT (num, 0);
+		} else {
+			NPUT (num, 0);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 1)
+	case 1:
+		if (blocking) {
+			PUT (num, 1);
+		} else {
+			NPUT (num, 1);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 2)
+	case 2:
+		if (blocking) {
+			PUT (num, 2);
+		} else {
+			NPUT (num, 2);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 3)
+	case 3:
+		if (blocking) {
+			PUT (num, 3);
+		} else {
+			NPUT (num, 3);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 4)
+	case 4:
+		if (blocking) {
+			PUT (num, 4);
+		} else {
+			NPUT (num, 4);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 5)
+	case 5:
+		if (blocking) {
+			PUT (num, 5);
+		} else {
+			NPUT (num, 5);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 6)
+	case 6:
+		if (blocking) {
+			PUT (num, 6);
+		} else {
+			NPUT (num, 6);
+		}
+		break;
+#endif
+#if (XILINX_FSL_NUMBER > 7)
+	case 7:
+		if (blocking) {
+			PUT (num, 7);
+		} else {
+			NPUT (num, 7);
+		}
+		break;
+#endif
+	default:
+		return 1;
+	}
+
+	printf ("%01x: 0x%08lx - %s write\n", fslnum, num,
+		blocking ? "blocking" : "non blocking");
+	return 0;
+
+}
+
+int do_rmsr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	int val = 0;
+
+	if (argc < 1) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+	RMSR (val);
+	printf ("rmsr: 0x%08lx\n", val);
+	return 0;
+}
+
+/***************************************************/
+
+U_BOOT_CMD (frd, 3, 1, do_frd,
+	    "frd     - read data from FSL\n",
+	    "- [fslnum [0|x]],  (0 - non blocking|x - blocking).\n");
+
+U_BOOT_CMD (fwr, 4, 1, do_fwr,
+	    "fwr     - write data to FSL\n",
+	    "- [fslnum data [0|x]],  (0 - non blocking|x - blocking).\n");
+
+U_BOOT_CMD (rmsr, 1, 1, do_rmsr,
+	    "rmsr    - read MSR register\n", "- read MSR register.\n");
+
+#endif	/* CONFIG_MICROBLAZE & CFG_CMD_MFSL */
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
new file mode 100644
index 0000000000..67475725e2
--- /dev/null
+++ b/include/asm-microblaze/asm.h
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2007 Michal Simek
+ *
+ * Michal  SIMEK <monstr@monstr.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* FSL macros */
+#define NGET(val, fslnum) \
+	__asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val));
+#define GET(val, fslnum) \
+	__asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val));
+#define NPUT(val, fslnum) \
+	__asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val));
+#define PUT(val, fslnum) \
+	__asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val));
+								
+/* CPU dependent */
+#define RMSR(val) \
+	__asm__ __volatile__ ("mfs %0,rmsr":"=r" (val));

From ffc50f9bb194343c6303517a517708457a5eb6b8 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Sat, 5 May 2007 18:54:42 +0200
Subject: [PATCH 06/17] new: FSL and MSR support #2

---
 README                           | 1 +
 board/xilinx/ml401/xparameters.h | 3 +++
 common/Makefile                  | 2 +-
 include/cmd_confdefs.h           | 2 ++
 include/configs/ml401.h          | 3 +++
 5 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/README b/README
index 15428643ed..33039f1d9c 100644
--- a/README
+++ b/README
@@ -703,6 +703,7 @@ The following options need to be configured:
 		CFG_CMD_VFD	* VFD support (TRAB)
 		CFG_CMD_BSP	* Board SPecific functions
 		CFG_CMD_CDP	* Cisco Discover Protocol support
+		CFG_CMD_FSL	* Microblaze FSL support
 		-----------------------------------------------
 		CFG_CMD_ALL	all
 
diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h
index 4fe36f8a9d..f63ffed3dc 100644
--- a/board/xilinx/ml401/xparameters.h
+++ b/board/xilinx/ml401/xparameters.h
@@ -29,6 +29,9 @@
 /* System Clock Frequency */
 #define XILINX_CLOCK_FREQ	100000000
 
+/* Microblaze is microblaze_0 */
+#define XILINX_FSL_NUMBER	2
+
 /* Interrupt controller is intc_0 */
 #define XILINX_INTC_BASEADDR	0x41200000
 #define XILINX_INTC_NUM_INTR_INPUTS	4
diff --git a/common/Makefile b/common/Makefile
index 6f81c4abcf..c088821a57 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -50,7 +50,7 @@ COBJS	= main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
 	  memsize.o miiphybb.o miiphyutil.o \
 	  s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \
 	  usb.o usb_kbd.o usb_storage.o \
-	  virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o
+	  virtex2.o xilinx.o crc16.o xyzModem.o cmd_mac.o cmd_mfsl.o
 
 SRCS	:= $(AOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(AOBJS) $(COBJS))
diff --git a/include/cmd_confdefs.h b/include/cmd_confdefs.h
index cf36583108..b3ccdcea2b 100644
--- a/include/cmd_confdefs.h
+++ b/include/cmd_confdefs.h
@@ -94,6 +94,7 @@
 #define CFG_CMD_EXT2	0x1000000000000000ULL	/* EXT2 Support			*/
 #define CFG_CMD_SNTP	0x2000000000000000ULL	/* SNTP support			*/
 #define CFG_CMD_DISPLAY	0x4000000000000000ULL	/* Display support		*/
+#define CFG_CMD_MFSL	0x8000000000000000ULL	/* FSL support for Microblaze	*/
 
 #define CFG_CMD_ALL	0xFFFFFFFFFFFFFFFFULL	/* ALL commands			*/
 
@@ -125,6 +126,7 @@
 			CFG_CMD_IRQ	| \
 			CFG_CMD_JFFS2	| \
 			CFG_CMD_KGDB	| \
+			CFG_CMD_MFSL	| \
 			CFG_CMD_MII	| \
 			CFG_CMD_MMC	| \
 			CFG_CMD_NAND	| \
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index acaa1e4f2b..f3ef962a78 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -161,6 +161,7 @@
 				CFG_CMD_ECHO |\
 				CFG_CMD_IMLS |\
 				CFG_CMD_FLASH |\
+				CFG_CMD_MFSL |\
 				CFG_CMD_PING \
 				)
 	#else	/* !RAMENV */
@@ -185,6 +186,7 @@
 				CFG_CMD_EXT2 |\
 				CFG_CMD_JFFS2 |\
 				CFG_CMD_ECHO |\
+				CFG_CMD_MFSL |\
 				CFG_CMD_SAVES \
 				)
 
@@ -206,6 +208,7 @@
 				CFG_CMD_IMI |\
 				CFG_CMD_NET |\
 				CFG_CMD_CACHE |\
+				CFG_CMD_MFSL |\
 				CFG_CMD_PING \
 				)
 #endif	/* !FLASH */

From 48fbd3a4cdabbebc1debd7eed73c00c2caf914f6 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 17:11:09 +0200
Subject: [PATCH 07/17] new: add writing to msr register

---
 board/xilinx/ml401/xparameters.h | 34 ++++++++++++++++++--------------
 common/cmd_mfsl.c                | 14 +++++++++----
 include/asm-microblaze/asm.h     | 12 ++++++++---
 3 files changed, 38 insertions(+), 22 deletions(-)
 mode change 100644 => 100755 board/xilinx/ml401/xparameters.h

diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h
old mode 100644
new mode 100755
index f63ffed3dc..2b0c045b9f
--- a/board/xilinx/ml401/xparameters.h
+++ b/board/xilinx/ml401/xparameters.h
@@ -21,50 +21,54 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  *
- *
  * CAUTION: This file is automatically generated by libgen.
- * Version: Xilinx EDK 6.3 EDK_Gmm.12.3
+ * Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
  */
 
 /* System Clock Frequency */
 #define XILINX_CLOCK_FREQ	100000000
 
 /* Microblaze is microblaze_0 */
-#define XILINX_FSL_NUMBER	2
+#define XILINX_FSL_NUMBER	3
 
-/* Interrupt controller is intc_0 */
+/* Interrupt controller is opb_intc_0 */
 #define XILINX_INTC_BASEADDR	0x41200000
-#define XILINX_INTC_NUM_INTR_INPUTS	4
+#define XILINX_INTC_NUM_INTR_INPUTS	5
 
-/* Timer pheriphery is opb_timer_0 */
+/* Timer pheriphery is opb_timer_1 */
 #define XILINX_TIMER_BASEADDR	0x41c00000
 #define XILINX_TIMER_IRQ	0
 
-/* Uart pheriphery is console_uart */
+/* Uart pheriphery is RS232_Uart */
 #define XILINX_UART_BASEADDR	0x40600000
 #define XILINX_UART_BAUDRATE	115200
 
-/* GPIO is opb_gpio_0*/
-#define XILINX_GPIO_BASEADDR	0x90000000
+/* IIC pheriphery is IIC_EEPROM */
+#define XILINX_IIC_0_BASEADDR	0x40800000
+#define XILINX_IIC_0_FREQ	100000
+#define XILINX_IIC_0_BIT	0
 
-/* Flash Memory is opb_emc_0 */
+/* GPIO is LEDs_4Bit*/
+#define XILINX_GPIO_BASEADDR	0x40000000
+
+/* Flash Memory is FLASH_2Mx32 */
 #define XILINX_FLASH_START	0x2c000000
 #define XILINX_FLASH_SIZE	0x00800000
 
-/* Main Memory is plb_ddr_0 */
+/* Main Memory is DDR_SDRAM_64Mx32 */
 #define XILINX_RAM_START	0x28000000
 #define XILINX_RAM_SIZE	0x04000000
 
-/* Sysace Controller is opb_sysace_0 */
+/* Sysace Controller is SysACE_CompactFlash */
 #define XILINX_SYSACE_BASEADDR	0x41800000
-#define XILINX_SYSACE_HIGHADDR	0x4180FFFF
+#define XILINX_SYSACE_HIGHADDR	0x4180ffff
 #define XILINX_SYSACE_MEM_WIDTH	16
 
-/* Ethernet controller is opb_ethernet_0 */
+/* Ethernet controller is Ethernet_MAC */
 #define XPAR_XEMAC_NUM_INSTANCES	1
 #define XPAR_OPB_ETHERNET_0_DEVICE_ID	0
 #define XPAR_OPB_ETHERNET_0_BASEADDR	0x40c00000
-#define XPAR_OPB_ETHERNET_0_HIGHADDR	0x40c0fFFF
+#define XPAR_OPB_ETHERNET_0_HIGHADDR	0x40c0ffff
 #define XPAR_OPB_ETHERNET_0_DMA_PRESENT	1
 #define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST	1
 #define XPAR_OPB_ETHERNET_0_MII_EXIST	1
diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c
index 827b75e6ce..ca8a8897d5 100644
--- a/common/cmd_mfsl.c
+++ b/common/cmd_mfsl.c
@@ -238,13 +238,19 @@ int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 int do_rmsr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	int val = 0;
+	unsigned int val = 0;
 
+	val = (unsigned int)simple_strtoul (argv[1], NULL, 16);
 	if (argc < 1) {
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
 	}
-	RMSR (val);
+	if (argc > 1) {
+		MTS (val);
+		MFS (val);
+	} else {
+		MFS (val);
+	}
 	printf ("rmsr: 0x%08lx\n", val);
 	return 0;
 }
@@ -259,7 +265,7 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr,
 	    "fwr     - write data to FSL\n",
 	    "- [fslnum data [0|x]],  (0 - non blocking|x - blocking).\n");
 
-U_BOOT_CMD (rmsr, 1, 1, do_rmsr,
+U_BOOT_CMD (rmsr, 3, 1, do_rmsr,
 	    "rmsr    - read MSR register\n", "- read MSR register.\n");
 
-#endif	/* CONFIG_MICROBLAZE & CFG_CMD_MFSL */
+#endif				/* CONFIG_MICROBLAZE & CFG_CMD_MFSL */
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
index 67475725e2..fcda31f4a8 100644
--- a/include/asm-microblaze/asm.h
+++ b/include/asm-microblaze/asm.h
@@ -31,7 +31,13 @@
 	__asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val));
 #define PUT(val, fslnum) \
 	__asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val));
-								
+
 /* CPU dependent */
-#define RMSR(val) \
-	__asm__ __volatile__ ("mfs %0,rmsr":"=r" (val));
+#define MFS(val) \
+	__asm__ __volatile__ ("mfs %0, rmsr":"=r" (val));
+
+#define MTS(val) \
+	__asm__ __volatile__ ("mts rmsr, %0"::"r" (val));
+
+#define R14(val) \
+	__asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));

From 42efed6130c8fcf7da881385b5427065d2801757 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 17:22:25 +0200
Subject: [PATCH 08/17] fix: interrupt handler for multiple sources

---
 cpu/microblaze/interrupts.c              | 19 ++++++++++++-------
 cpu/microblaze/timer.c                   |  4 +---
 include/asm-microblaze/microblaze_intc.h |  2 ++
 3 files changed, 15 insertions(+), 10 deletions(-)

diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c
index 2db847cd02..115e58d7f0 100644
--- a/cpu/microblaze/interrupts.c
+++ b/cpu/microblaze/interrupts.c
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/microblaze_intc.h>
+#include <asm/asm.h>
 
 #undef DEBUG_INT
 
@@ -106,7 +107,6 @@ void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg)
 		act->count = 0;
 		enable_one_interrupt (irq);
 	} else {		/* disable */
-
 		act->handler = (interrupt_handler_t *) def_hdlr;
 		act->arg = (void *)irq;
 		disable_one_interrupt (irq);
@@ -147,12 +147,13 @@ int interrupts_init (void)
 
 void interrupt_handler (void)
 {
-	int irqs;
-	irqs = (intc->isr & intc->ier);	/* find active interrupt */
-
+	int irqs = (intc->isr & intc->ier);	/* find active interrupt */
+	int i = 1;
 #ifdef DEBUG_INT
+	int value;
 	printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
 		intc->iar, intc->mer);
+	R14(value);
 	printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
 #endif
 	struct irq_action *act = vecs;
@@ -165,15 +166,19 @@ void interrupt_handler (void)
 #endif
 			act->handler (act->arg);
 			act->count++;
+			intc->iar = i;
+			return;
 		}
 		irqs >>= 1;
 		act++;
+		i <<= 1;
 	}
-	intc->iar = 0xFFFFFFFF;	/* erase all events */
-#ifdef DEBUG
+
+#ifdef DEBUG_INT
 	printf ("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr,
 		intc->ier, intc->iar, intc->mer);
-	printf ("Interrupt handler on %x line, r14\n", irqs);
+	R14(value);
+	printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
 #endif
 }
 #endif
diff --git a/cpu/microblaze/timer.c b/cpu/microblaze/timer.c
index be4fd57cc4..ab1cb12749 100644
--- a/cpu/microblaze/timer.c
+++ b/cpu/microblaze/timer.c
@@ -24,6 +24,7 @@
 
 #include <common.h>
 #include <asm/microblaze_timer.h>
+#include <asm/microblaze_intc.h>
 
 volatile int timestamp = 0;
 
@@ -44,9 +45,6 @@ void set_timer (ulong t)
 
 #ifdef CFG_INTC_0
 #ifdef CFG_TIMER_0
-extern void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
-				       void *arg);
-
 microblaze_timer_t *tmr = (microblaze_timer_t *) (CFG_TIMER_0_ADDR);
 
 void timer_isr (void *arg)
diff --git a/include/asm-microblaze/microblaze_intc.h b/include/asm-microblaze/microblaze_intc.h
index 73f732c566..4c385aa24f 100644
--- a/include/asm-microblaze/microblaze_intc.h
+++ b/include/asm-microblaze/microblaze_intc.h
@@ -39,3 +39,5 @@ struct irq_action {
 	int count; /* number of interrupt */
 };
 
+void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
+				       void *arg);

From fb7c2dbef02c9f6f8d7b04ec4c2bfb91418b9c01 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 19:12:43 +0200
Subject: [PATCH 09/17] fix: clean interrupt

---
 cpu/microblaze/Makefile     |  3 ++-
 cpu/microblaze/interrupts.c | 13 +++++++++++--
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/cpu/microblaze/Makefile b/cpu/microblaze/Makefile
index db1afa553d..b7be5e146c 100644
--- a/cpu/microblaze/Makefile
+++ b/cpu/microblaze/Makefile
@@ -26,7 +26,8 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-SOBJS	= dcache.o icache.o irq.o disable_int.o enable_int.o
+#SOBJS	= dcache.o icache.o irq.o disable_int.o enable_int.o
+SOBJS	= dcache.o icache.o irq.o
 COBJS	= cpu.o interrupts.o cache.o exception.o timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c
index 115e58d7f0..c0c92ec559 100644
--- a/cpu/microblaze/interrupts.c
+++ b/cpu/microblaze/interrupts.c
@@ -36,12 +36,14 @@ extern void microblaze_enable_interrupts (void);
 
 void enable_interrupts (void)
 {
-	microblaze_enable_interrupts ();
+	__asm__ __volatile__ ("msrset r0, 0x2");
+	//microblaze_enable_interrupts ();
 }
 
 int disable_interrupts (void)
 {
-	microblaze_disable_interrupts ();
+	__asm__ __volatile__ ("msrclr r0, 0x2");
+	//microblaze_disable_interrupts ();
 	return 0;
 }
 
@@ -49,6 +51,10 @@ int disable_interrupts (void)
 #ifdef CFG_TIMER_0
 extern void timer_init (void);
 #endif
+#ifdef CFG_FSL_2
+extern void fsl_init2 (void);
+#endif
+
 
 static struct irq_action vecs[CFG_INTC_0_NUM];
 
@@ -140,6 +146,9 @@ int interrupts_init (void)
 	intc_init ();
 #ifdef CFG_TIMER_0
 	timer_init ();
+#endif
+#ifdef CFG_FSL_2
+	fsl_init2 ();
 #endif
 	enable_interrupts ();
 	return 0;

From f3f001a341ef185d0f13841be5b5dc3395aacc31 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 19:25:08 +0200
Subject: [PATCH 10/17] fix: remove asm code

---
 cpu/microblaze/Makefile      |  3 +-
 cpu/microblaze/cache.c       | 16 +++++++++
 cpu/microblaze/dcache.S      | 68 -----------------------------------
 cpu/microblaze/disable_int.S | 46 ------------------------
 cpu/microblaze/enable_int.S  | 38 --------------------
 cpu/microblaze/icache.S      | 69 ------------------------------------
 6 files changed, 17 insertions(+), 223 deletions(-)
 delete mode 100644 cpu/microblaze/dcache.S
 delete mode 100644 cpu/microblaze/disable_int.S
 delete mode 100644 cpu/microblaze/enable_int.S
 delete mode 100644 cpu/microblaze/icache.S

diff --git a/cpu/microblaze/Makefile b/cpu/microblaze/Makefile
index b7be5e146c..9d542013cc 100644
--- a/cpu/microblaze/Makefile
+++ b/cpu/microblaze/Makefile
@@ -26,8 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-#SOBJS	= dcache.o icache.o irq.o disable_int.o enable_int.o
-SOBJS	= dcache.o icache.o irq.o
+SOBJS	= irq.o
 COBJS	= cpu.o interrupts.o cache.o exception.o timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c
index fc388ebb56..683044caea 100644
--- a/cpu/microblaze/cache.c
+++ b/cpu/microblaze/cache.c
@@ -45,4 +45,20 @@ int icache_status (void)
 	__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
 	return i;
 }
+
+void	icache_enable (void) {
+	__asm__ __volatile__ ("msrset r0, 0x80");
+}
+
+void	icache_disable(void) {
+	__asm__ __volatile__ ("msrclr r0, 0x80");
+}
+
+void	dcache_enable (void) {
+	__asm__ __volatile__ ("msrset r0, 0x20");
+}
+
+void	dcache_disable(void) {
+	__asm__ __volatile__ ("msrclr r0, 0x20");
+}
 #endif
diff --git a/cpu/microblaze/dcache.S b/cpu/microblaze/dcache.S
deleted file mode 100644
index eaf96717eb..0000000000
--- a/cpu/microblaze/dcache.S
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-	.text
-	.globl	dcache_enable
-	.ent	dcache_enable
-	.align	2
-dcache_enable:
-	/* Make space on stack for a temporary */
-	addi	r1, r1, -4
-	/* Save register r12 */
-	swi	r12, r1, 0
-	/* Read the MSR register */
-	mfs	r12, rmsr
-	/* Set the instruction enable bit */
-	ori	r12, r12, 0x80
-	/* Save the MSR register */
-	mts	rmsr, r12
-	/* Load register r12 */
-	lwi	r12, r1, 0
-	/* Return */
-	rtsd	r15, 8
-	/* Update stack in the delay slot */
-	addi	r1, r1, 4
-	.end	dcache_enable
-
-	.text
-	.globl	dcache_disable
-	.ent	dcache_disable
-	.align	2
-dcache_disable:
-	/* Make space on stack for a temporary */
-	addi	r1, r1, -4
-	/* Save register r12 */
-	swi	r12, r1, 0
-	/* Read the MSR register */
-	mfs	r12, rmsr
-	/* Clear the data cache enable bit */
-	andi	r12, r12, ~0x80
-	/* Save the MSR register */
-	mts	rmsr, r12
-	/* Load register r12 */
-	lwi	r12, r1, 0
-	/* Return */
-	rtsd	r15, 8
-	/* Update stack in the delay slot */
-	addi	r1, r1, 4
-	.end	dcache_disable
diff --git a/cpu/microblaze/disable_int.S b/cpu/microblaze/disable_int.S
deleted file mode 100644
index aecd79513c..0000000000
--- a/cpu/microblaze/disable_int.S
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-	.text
-	.globl	microblaze_disable_interrupts
-	.ent	microblaze_disable_interrupts
-	.align	2
-microblaze_disable_interrupts:
-	#Make space on stack for a temporary
-	addi	r1, r1, -4
-	#Save register r12
-	swi	r12, r1, 0
-	#Read the MSR register
-	mfs	r12, rmsr
-	#Clear the interrupt enable bit
-	andi	r12, r12, ~2
-	#Save the MSR register
-	mts	rmsr, r12
-	#Load register r12
-	lwi	r12, r1, 0
-	#Return
-	rtsd	r15, 8
-	#Update stack in the delay slot
-	addi	r1, r1, 4
-	.end	microblaze_disable_interrupts
diff --git a/cpu/microblaze/enable_int.S b/cpu/microblaze/enable_int.S
deleted file mode 100644
index c096c6c3c0..0000000000
--- a/cpu/microblaze/enable_int.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstrmonstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-	.text
-	.globl	microblaze_enable_interrupts
-	.ent	microblaze_enable_interrupts
-	.align	2
-microblaze_enable_interrupts:
-	addi	r1, r1, -4
-	swi	r12, r1, 0
-	mfs	r12, rmsr
-	ori	r12, r12, 2
-	mts	rmsr, r12
-	lwi	r12, r1, 0
-	rtsd	r15, 8
-	addi	r1, r1, 4
-	.end	microblaze_enable_interrupts
diff --git a/cpu/microblaze/icache.S b/cpu/microblaze/icache.S
deleted file mode 100644
index 25940d106e..0000000000
--- a/cpu/microblaze/icache.S
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * (C) Copyright 2007 Michal Simek
- *
- * Michal  SIMEK <monstr@monstr.eu>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-	.text
-	.globl	icache_enable
-	.ent	icache_enable
-	.align	2
-icache_enable:
-	/* Make space on stack for a temporary */
-	addi	r1, r1, -4
-	/* Save register r12 */
-	swi	r12, r1, 0
-	/* Read the MSR register */
-	mfs	r12, rmsr
-	/* Set the instruction enable bit */
-	ori	r12, r12, 0x20
-	/* Save the MSR register */
-	mts	rmsr, r12
-	/* Load register r12 */
-	lwi	r12, r1, 0
-	/* Return */
-	rtsd	r15, 8
-	/* Update stack in the delay slot */
-	addi	r1, r1, 4
-	.end	icache_enable
-
-	.text
-	.globl	icache_disable
-	.ent	icache_disable
-	.align	2
-icache_disable:
-	/* Make space on stack for a temporary */
-	addi	r1, r1, -4
-	/* Save register r12 */
-	swi	r12, r1, 0
-	/* Read the MSR register */
-	mfs	r12, rmsr
-	/* Clear the instruction enable bit */
-	andi	r12, r12, ~0x20
-	/* Save the MSR register */
-	mts	rmsr, r12
-	/* Load register r12 */
-	lwi	r12, r1, 0
-	/* Return */
-	rtsd	r15, 8
-	/* Update stack in the delay slot */
-	addi	r1, r1, 4
-	.end	icache_disable

From 792032baa7d625e34c981ab6df521911bd8dc861 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 19:30:12 +0200
Subject: [PATCH 11/17] fix: interrupt handler remove asm code

---
 cpu/microblaze/interrupts.c | 2 --
 cpu/microblaze/irq.S        | 9 +--------
 2 files changed, 1 insertion(+), 10 deletions(-)

diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c
index c0c92ec559..dd6a0c7776 100644
--- a/cpu/microblaze/interrupts.c
+++ b/cpu/microblaze/interrupts.c
@@ -37,13 +37,11 @@ extern void microblaze_enable_interrupts (void);
 void enable_interrupts (void)
 {
 	__asm__ __volatile__ ("msrset r0, 0x2");
-	//microblaze_enable_interrupts ();
 }
 
 int disable_interrupts (void)
 {
 	__asm__ __volatile__ ("msrclr r0, 0x2");
-	//microblaze_disable_interrupts ();
 	return 0;
 }
 
diff --git a/cpu/microblaze/irq.S b/cpu/microblaze/irq.S
index a4e3fbfad6..393d6e8dd4 100644
--- a/cpu/microblaze/irq.S
+++ b/cpu/microblaze/irq.S
@@ -151,14 +151,7 @@ _interrupt_handler:
 	addi	r1, r1, 4
 
 	/* enable_interrupt */
-	addi	r1, r1, -4
-	swi	r12, r1, 0
-	mfs	r12, rmsr
-	ori	r12, r12, 2
-	mts	rmsr, r12
-	lwi	r12, r1, 0
-	addi	r1, r1, 4
-	nop
+	msrset	r0, 2
 	bra	r14
 	nop
 	nop

From 19bf1fbad7f19d5a120be9b1daf136e052fcab39 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 19:33:51 +0200
Subject: [PATCH 12/17] new: fsl interrupt support FSL_Has_data is connected to
 INTC.

---
 board/xilinx/ml401/ml401.c | 22 +++++++++++++++++++++-
 include/configs/ml401.h    |  4 ++++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/board/xilinx/ml401/ml401.c b/board/xilinx/ml401/ml401.c
index b48103fdc0..955936d907 100644
--- a/board/xilinx/ml401/ml401.c
+++ b/board/xilinx/ml401/ml401.c
@@ -27,6 +27,8 @@
 
 #include <common.h>
 #include <config.h>
+#include <asm/microblaze_intc.h>
+#include <asm/asm.h>
 
 void do_reset (void)
 {
@@ -43,7 +45,25 @@ void do_reset (void)
 int gpio_init (void)
 {
 #ifdef CFG_GPIO_0
-	*((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0;
+	*((unsigned long *)(CFG_GPIO_0_ADDR)) = 0xFFFFFFFF;
 #endif
 	return 0;
 }
+
+#ifdef CFG_FSL_2
+void fsl_isr2 (void *arg) {
+	volatile int num;
+	*((unsigned int *)(CFG_GPIO_0_ADDR + 0x4)) =
+	    ++(*((unsigned int *)(CFG_GPIO_0_ADDR + 0x4)));
+	GET (num, 2);
+	NGET (num, 2);
+	puts("*");
+}
+
+void fsl_init2 (void) {
+	puts("fsl_init2\n");
+	install_interrupt_handler (FSL_INTR_2,\
+ fsl_isr2,\
+ NULL);
+}
+#endif
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index f3ef962a78..327d31c103 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -58,6 +58,10 @@
 #define	FREQUENCE		XILINX_CLOCK_FREQ
 #define	CFG_TIMER_0_PRELOAD	( FREQUENCE/1000 )
 
+/* FSL */
+#define	CFG_FSL_2
+#define	FSL_INTR_2	1
+
 /*
  * memory layout - Example
  * TEXT_BASE = 0x1200_0000;

From a7bac7e9b57ba948051beb19ec5be3a75ce75383 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 19:43:10 +0200
Subject: [PATCH 13/17] fix: read and write MSR - repair number of parameters

---
 common/cmd_mfsl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c
index ca8a8897d5..7aa37afd3f 100644
--- a/common/cmd_mfsl.c
+++ b/common/cmd_mfsl.c
@@ -265,7 +265,7 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr,
 	    "fwr     - write data to FSL\n",
 	    "- [fslnum data [0|x]],  (0 - non blocking|x - blocking).\n");
 
-U_BOOT_CMD (rmsr, 3, 1, do_rmsr,
+U_BOOT_CMD (rmsr, 2, 1, do_rmsr,
 	    "rmsr    - read MSR register\n", "- read MSR register.\n");
 
 #endif				/* CONFIG_MICROBLAZE & CFG_CMD_MFSL */

From fb05f6da35ea1c15c553abe6f23f656bf18dc5db Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Mon, 7 May 2007 23:58:31 +0200
Subject: [PATCH 14/17] new: USE_MSR_INTR support

---
 board/xilinx/ml401/xparameters.h |  3 ++-
 cpu/microblaze/cache.c           |  9 ++++----
 cpu/microblaze/interrupts.c      |  4 ++--
 cpu/microblaze/irq.S             | 14 ++++++++++++
 include/asm-microblaze/asm.h     | 37 ++++++++++++++++++++++++++++++++
 5 files changed, 60 insertions(+), 7 deletions(-)
 mode change 100644 => 100755 cpu/microblaze/cache.c
 mode change 100644 => 100755 cpu/microblaze/interrupts.c
 mode change 100644 => 100755 cpu/microblaze/irq.S
 mode change 100644 => 100755 include/asm-microblaze/asm.h

diff --git a/board/xilinx/ml401/xparameters.h b/board/xilinx/ml401/xparameters.h
index 2b0c045b9f..1a116ead1b 100755
--- a/board/xilinx/ml401/xparameters.h
+++ b/board/xilinx/ml401/xparameters.h
@@ -29,11 +29,12 @@
 #define XILINX_CLOCK_FREQ	100000000
 
 /* Microblaze is microblaze_0 */
+#define XILINX_USE_MSR_INSTR	1
 #define XILINX_FSL_NUMBER	3
 
 /* Interrupt controller is opb_intc_0 */
 #define XILINX_INTC_BASEADDR	0x41200000
-#define XILINX_INTC_NUM_INTR_INPUTS	5
+#define XILINX_INTC_NUM_INTR_INPUTS	6
 
 /* Timer pheriphery is opb_timer_1 */
 #define XILINX_TIMER_BASEADDR	0x41c00000
diff --git a/cpu/microblaze/cache.c b/cpu/microblaze/cache.c
old mode 100644
new mode 100755
index 683044caea..4f36a84ec4
--- a/cpu/microblaze/cache.c
+++ b/cpu/microblaze/cache.c
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <asm/asm.h>
 
 #if (CONFIG_COMMANDS & CFG_CMD_CACHE)
 
@@ -47,18 +48,18 @@ int icache_status (void)
 }
 
 void	icache_enable (void) {
-	__asm__ __volatile__ ("msrset r0, 0x80");
+	MSRSET(0x20);
 }
 
 void	icache_disable(void) {
-	__asm__ __volatile__ ("msrclr r0, 0x80");
+	MSRCLR(0x20);
 }
 
 void	dcache_enable (void) {
-	__asm__ __volatile__ ("msrset r0, 0x20");
+	MSRSET(0x80);
 }
 
 void	dcache_disable(void) {
-	__asm__ __volatile__ ("msrclr r0, 0x20");
+	MSRCLR(0x80);
 }
 #endif
diff --git a/cpu/microblaze/interrupts.c b/cpu/microblaze/interrupts.c
old mode 100644
new mode 100755
index dd6a0c7776..b61153f8e6
--- a/cpu/microblaze/interrupts.c
+++ b/cpu/microblaze/interrupts.c
@@ -36,12 +36,12 @@ extern void microblaze_enable_interrupts (void);
 
 void enable_interrupts (void)
 {
-	__asm__ __volatile__ ("msrset r0, 0x2");
+	MSRSET(0x2);
 }
 
 int disable_interrupts (void)
 {
-	__asm__ __volatile__ ("msrclr r0, 0x2");
+	MSRCLR(0x2);
 	return 0;
 }
 
diff --git a/cpu/microblaze/irq.S b/cpu/microblaze/irq.S
old mode 100644
new mode 100755
index 393d6e8dd4..e1fc19046c
--- a/cpu/microblaze/irq.S
+++ b/cpu/microblaze/irq.S
@@ -23,6 +23,7 @@
  */
 
 #include <config.h>
+#include <asm/asm.h>
 	.text
 	.global _interrupt_handler
 _interrupt_handler:
@@ -151,7 +152,20 @@ _interrupt_handler:
 	addi	r1, r1, 4
 
 	/* enable_interrupt */
+#ifdef XILINX_USE_MSR_INSTR
 	msrset	r0, 2
+#else
+	/* FIXME unstable in stressed mode - two irqs */
+	nop
+	addi	r1, r1, -4
+	swi	r12, r1, 0
+	mfs	r12, rmsr
+	ori	r12, r12, 2
+	mts	rmsr, r12
+	lwi	r12, r1, 0
+	addi	r1, r1, 4
+	nop
+#endif
 	bra	r14
 	nop
 	nop
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
old mode 100644
new mode 100755
index fcda31f4a8..c59854a860
--- a/include/asm-microblaze/asm.h
+++ b/include/asm-microblaze/asm.h
@@ -39,5 +39,42 @@
 #define MTS(val) \
 	__asm__ __volatile__ ("mts rmsr, %0"::"r" (val));
 
+/* get return address from interrupt */
 #define R14(val) \
 	__asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));
+
+/* use machine status registe USE_MSR_REG */
+#ifdef XILINX_USE_MSR_INSTR
+#define MSRSET(val) \
+	__asm__ __volatile__ ("msrset r0," #val );
+
+#define MSRCLR(val) \
+	__asm__ __volatile__ ("msrclr r0," #val );
+
+#else
+#define MSRSET(val)						\
+{								\
+	register unsigned tmp;					\
+	__asm__ __volatile__ ("					\
+			mfs 	%0, rmsr;			\
+			ori	%0, %0, "#val";			\
+			mts	rmsr, %0;			\
+			nop;"					\
+			: "=r" (tmp)				\
+			: "d" (val)				\
+			: "memory");				\
+}
+
+#define MSRCLR(val)						\
+{								\
+	register unsigned tmp;					\
+	__asm__ __volatile__ ("					\
+			mfs 	%0, rmsr;			\
+			andi	%0, %0, ~"#val";		\
+			mts	rmsr, %0;			\
+			nop;"					\
+			: "=r" (tmp)				\
+			: "d" (val)				\
+			: "memory");				\
+}
+#endif

From ab874d5047e5d30dbc1e517ff26083efffa98ecb Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Tue, 8 May 2007 14:39:11 +0200
Subject: [PATCH 15/17] add: FSL control read and write

---
 common/cmd_mfsl.c            | 267 +++++++++++++++++++++++++----------
 include/asm-microblaze/asm.h |  15 ++
 2 files changed, 210 insertions(+), 72 deletions(-)

diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c
index 7aa37afd3f..3032489f08 100644
--- a/common/cmd_mfsl.c
+++ b/common/cmd_mfsl.c
@@ -55,73 +55,129 @@ int do_frd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	switch (fslnum) {
 #if (XILINX_FSL_NUMBER > 0)
 	case 0:
-		if (blocking) {
-			GET (num, 0);
-		} else {
-			NGET (num, 0);
+		switch (blocking) {
+		case 0:	NGET (num, 0);
+			break;
+		case 1:	NCGET (num, 0);
+			break;
+		case 2:	GET (num, 0);
+			break;
+		case 3:	CGET (num, 0);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 1)
 	case 1:
-		if (blocking) {
-			GET (num, 1);
-		} else {
-			NGET (num, 1);
+		switch (blocking) {
+		case 0:	NGET (num, 1);
+			break;
+		case 1:	NCGET (num, 1);
+			break;
+		case 2:	GET (num, 1);
+			break;
+		case 3:	CGET (num, 1);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 2)
 	case 2:
-		if (blocking) {
-			GET (num, 2);
-		} else {
-			NGET (num, 2);
+		switch (blocking) {
+		case 0:	NGET (num, 2);
+			break;
+		case 1:	NCGET (num, 2);
+			break;
+		case 2:	GET (num, 2);
+			break;
+		case 3:	CGET (num, 2);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 3)
 	case 3:
-		if (blocking) {
-			GET (num, 3);
-		} else {
-			NGET (num, 3);
+		switch (blocking) {
+		case 0:	NGET (num, 3);
+			break;
+		case 1:	NCGET (num, 3);
+			break;
+		case 2:	GET (num, 3);
+			break;
+		case 3:	CGET (num, 3);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 4)
 	case 4:
-		if (blocking) {
-			GET (num, 4);
-		} else {
-			NGET (num, 4);
+		switch (blocking) {
+		case 0:	NGET (num, 4);
+			break;
+		case 1:	NCGET (num, 4);
+			break;
+		case 2:	GET (num, 4);
+			break;
+		case 3:	CGET (num, 4);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 5)
 	case 5:
-		if (blocking) {
-			GET (num, 5);
-		} else {
-			NGET (num, 5);
+		switch (blocking) {
+		case 0:	NGET (num, 5);
+			break;
+		case 1:	NCGET (num, 5);
+			break;
+		case 2:	GET (num, 5);
+			break;
+		case 3:	CGET (num, 5);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 6)
 	case 6:
-		if (blocking) {
-			GET (num, 6);
-		} else {
-			NGET (num, 6);
+		switch (blocking) {
+		case 0:	NGET (num, 6);
+			break;
+		case 1:	NCGET (num, 6);
+			break;
+		case 2:	GET (num, 6);
+			break;
+		case 3:	CGET (num, 6);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 7)
 	case 7:
-		if (blocking) {
-			GET (num, 7);
-		} else {
-			NGET (num, 7);
+		switch (blocking) {
+		case 0:	NGET (num, 7);
+			break;
+		case 1:	NCGET (num, 7);
+			break;
+		case 2:	GET (num, 7);
+			break;
+		case 3:	CGET (num, 7);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
@@ -129,8 +185,9 @@ int do_frd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 		return 1;
 	}
 
-	printf ("%01x: 0x%08lx - %s read\n", fslnum, num,
-		blocking ? "blocking" : "non blocking");
+	printf ("%01x: 0x%08lx - %s %s read\n", fslnum, num,
+		blocking < 2  ? "non blocking" : "blocking",
+		((blocking == 1) || (blocking == 3)) ? "control" : "data" );
 	return 0;
 }
 
@@ -156,73 +213,129 @@ int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	switch (fslnum) {
 #if (XILINX_FSL_NUMBER > 0)
 	case 0:
-		if (blocking) {
-			PUT (num, 0);
-		} else {
-			NPUT (num, 0);
+		switch (blocking) {
+		case 0:	NPUT (num, 0);
+			break;
+		case 1:	NCPUT (num, 0);
+			break;
+		case 2:	PUT (num, 0);
+			break;
+		case 3:	CPUT (num, 0);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 1)
 	case 1:
-		if (blocking) {
-			PUT (num, 1);
-		} else {
-			NPUT (num, 1);
+		switch (blocking) {
+		case 0:	NPUT (num, 1);
+			break;
+		case 1:	NCPUT (num, 1);
+			break;
+		case 2:	PUT (num, 1);
+			break;
+		case 3:	CPUT (num, 1);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 2)
 	case 2:
-		if (blocking) {
-			PUT (num, 2);
-		} else {
-			NPUT (num, 2);
+		switch (blocking) {
+		case 0:	NPUT (num, 2);
+			break;
+		case 1:	NCPUT (num, 2);
+			break;
+		case 2:	PUT (num, 2);
+			break;
+		case 3:	CPUT (num, 2);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 3)
 	case 3:
-		if (blocking) {
-			PUT (num, 3);
-		} else {
-			NPUT (num, 3);
+		switch (blocking) {
+		case 0:	NPUT (num, 3);
+			break;
+		case 1:	NCPUT (num, 3);
+			break;
+		case 2:	PUT (num, 3);
+			break;
+		case 3:	CPUT (num, 3);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 4)
 	case 4:
-		if (blocking) {
-			PUT (num, 4);
-		} else {
-			NPUT (num, 4);
+		switch (blocking) {
+		case 0:	NPUT (num, 4);
+			break;
+		case 1:	NCPUT (num, 4);
+			break;
+		case 2:	PUT (num, 4);
+			break;
+		case 3:	CPUT (num, 4);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 5)
 	case 5:
-		if (blocking) {
-			PUT (num, 5);
-		} else {
-			NPUT (num, 5);
+		switch (blocking) {
+		case 0:	NPUT (num, 5);
+			break;
+		case 1:	NCPUT (num, 5);
+			break;
+		case 2:	PUT (num, 5);
+			break;
+		case 3:	CPUT (num, 5);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 6)
 	case 6:
-		if (blocking) {
-			PUT (num, 6);
-		} else {
-			NPUT (num, 6);
+		switch (blocking) {
+		case 0:	NPUT (num, 6);
+			break;
+		case 1:	NCPUT (num, 6);
+			break;
+		case 2:	PUT (num, 6);
+			break;
+		case 3:	CPUT (num, 6);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
 #if (XILINX_FSL_NUMBER > 7)
 	case 7:
-		if (blocking) {
-			PUT (num, 7);
-		} else {
-			NPUT (num, 7);
+		switch (blocking) {
+		case 0:	NPUT (num, 7);
+			break;
+		case 1:	NCPUT (num, 7);
+			break;
+		case 2:	PUT (num, 7);
+			break;
+		case 3:	CPUT (num, 7);
+			break;
+		default:
+			return 2;
 		}
 		break;
 #endif
@@ -230,8 +343,9 @@ int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 		return 1;
 	}
 
-	printf ("%01x: 0x%08lx - %s write\n", fslnum, num,
-		blocking ? "blocking" : "non blocking");
+	printf ("%01x: 0x%08lx - %s %s write\n", fslnum, num,
+		blocking < 2  ? "non blocking" : "blocking",
+		((blocking == 1) || (blocking == 3)) ? "control" : "data" );
 	return 0;
 
 }
@@ -258,12 +372,21 @@ int do_rmsr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 /***************************************************/
 
 U_BOOT_CMD (frd, 3, 1, do_frd,
-	    "frd     - read data from FSL\n",
-	    "- [fslnum [0|x]],  (0 - non blocking|x - blocking).\n");
+		"frd     - read data from FSL\n",
+		"- [fslnum [0|1|2|3]]\n"
+		" 0 - non blocking data read\n"
+		" 1 - non blocking control read\n"
+		" 2 - blocking data read\n"
+		" 3 - blocking control read\n");
+
 
 U_BOOT_CMD (fwr, 4, 1, do_fwr,
-	    "fwr     - write data to FSL\n",
-	    "- [fslnum data [0|x]],  (0 - non blocking|x - blocking).\n");
+		"fwr     - write data to FSL\n",
+		"- [fslnum [0|1|2|3]]\n"
+		" 0 - non blocking data write\n"
+		" 1 - non blocking control write\n"
+		" 2 - blocking data write\n"
+		" 3 - blocking control write\n");
 
 U_BOOT_CMD (rmsr, 2, 1, do_rmsr,
 	    "rmsr    - read MSR register\n", "- read MSR register.\n");
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
index c59854a860..26e369119e 100755
--- a/include/asm-microblaze/asm.h
+++ b/include/asm-microblaze/asm.h
@@ -25,13 +25,28 @@
 /* FSL macros */
 #define NGET(val, fslnum) \
 	__asm__ __volatile__ ("nget %0, rfsl" #fslnum :"=r" (val));
+
 #define GET(val, fslnum) \
 	__asm__ __volatile__ ("get %0, rfsl" #fslnum :"=r" (val));
+
+#define NCGET(val, fslnum) \
+	__asm__ __volatile__ ("ncget %0, rfsl" #fslnum :"=r" (val));
+
+#define CGET(val, fslnum) \
+	__asm__ __volatile__ ("cget %0, rfsl" #fslnum :"=r" (val));
+
 #define NPUT(val, fslnum) \
 	__asm__ __volatile__ ("nput %0, rfsl" #fslnum ::"r" (val));
+
 #define PUT(val, fslnum) \
 	__asm__ __volatile__ ("put %0, rfsl" #fslnum ::"r" (val));
 
+#define NCPUT(val, fslnum) \
+	__asm__ __volatile__ ("ncput %0, rfsl" #fslnum ::"r" (val));
+
+#define CPUT(val, fslnum) \
+	__asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val));
+
 /* CPU dependent */
 #define MFS(val) \
 	__asm__ __volatile__ ("mfs %0, rmsr":"=r" (val));

From 1a50f164beb065f360fbddb76029607d6b099698 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Tue, 8 May 2007 14:52:52 +0200
Subject: [PATCH 16/17] add: Microblaze V5 exception handling

---
 cpu/microblaze/exception.c   | 10 ++++++++--
 include/asm-microblaze/asm.h |  8 ++++++++
 include/configs/ml401.h      |  1 +
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/cpu/microblaze/exception.c b/cpu/microblaze/exception.c
index b135acbad9..87ecbeaa49 100644
--- a/cpu/microblaze/exception.c
+++ b/cpu/microblaze/exception.c
@@ -23,15 +23,16 @@
  */
 
 #include <common.h>
+#include <asm/asm.h>
 
 void _hw_exception_handler (void)
 {
 	int address = 0;
 	int state = 0;
 	/* loading address of exception EAR */
-	__asm__ __volatile ("mfs %0,rear"::"r" (address):"memory");
+	MFSEAR(address);
 	/* loading excetpion state register ESR */
-	__asm__ __volatile ("mfs %0,resr"::"r" (state):"memory");
+	MFSESR(state);
 	printf ("Hardware exception at 0x%x address\n", address);
 	switch (state & 0x1f) {	/* mask on exception cause */
 	case 0x1:
@@ -49,6 +50,11 @@ void _hw_exception_handler (void)
 	case 0x5:
 		puts ("Divide by zero exception\n");
 		break;
+#ifdef MICROBLAZE_V5
+	case 0x1000:
+		puts ("Exception in delay slot\n");
+		break;
+#endif
 	default:
 		puts ("Undefined cause\n");
 		break;
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
index 26e369119e..8302ed8850 100755
--- a/include/asm-microblaze/asm.h
+++ b/include/asm-microblaze/asm.h
@@ -48,12 +48,20 @@
 	__asm__ __volatile__ ("cput %0, rfsl" #fslnum ::"r" (val));
 
 /* CPU dependent */
+/* machine status register */
 #define MFS(val) \
 	__asm__ __volatile__ ("mfs %0, rmsr":"=r" (val));
 
 #define MTS(val) \
 	__asm__ __volatile__ ("mts rmsr, %0"::"r" (val));
 
+/* exception status register */
+#define MFSEAR(val) \
+	__asm__ __volatile ("mfs %0,rear":"=r" (val));
+
+#define MFSESR(val) \
+	__asm__ __volatile ("mfs %0,resr":"=r" (val));
+
 /* get return address from interrupt */
 #define R14(val) \
 	__asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));
diff --git a/include/configs/ml401.h b/include/configs/ml401.h
index 327d31c103..4cfe802c36 100644
--- a/include/configs/ml401.h
+++ b/include/configs/ml401.h
@@ -28,6 +28,7 @@
 #include "../board/xilinx/ml401/xparameters.h"
 
 #define	CONFIG_MICROBLAZE	1	/* MicroBlaze CPU */
+#define	MICROBLAZE_V5		1
 #define	CONFIG_ML401		1	/* ML401 Board */
 
 /* uart */

From e69f66c6ebe82bbbd1da766bc4eda40ec7ee5af1 Mon Sep 17 00:00:00 2001
From: Michal Simek <monstr@monstr.eu>
Date: Tue, 8 May 2007 15:57:43 +0200
Subject: [PATCH 17/17] add: reading special purpose registers

---
 common/cmd_mfsl.c            | 43 +++++++++++++++++++++++++++---------
 cpu/microblaze/exception.c   |  4 ++--
 include/asm-microblaze/asm.h | 17 +++++---------
 3 files changed, 41 insertions(+), 23 deletions(-)

diff --git a/common/cmd_mfsl.c b/common/cmd_mfsl.c
index 3032489f08..26786aa8cd 100644
--- a/common/cmd_mfsl.c
+++ b/common/cmd_mfsl.c
@@ -350,22 +350,41 @@ int do_fwr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 
 }
 
-int do_rmsr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+int do_rspr (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
+	unsigned int reg = 0;
 	unsigned int val = 0;
 
-	val = (unsigned int)simple_strtoul (argv[1], NULL, 16);
+	reg = (unsigned int)simple_strtoul (argv[1], NULL, 16);
+	val = (unsigned int)simple_strtoul (argv[2], NULL, 16);
 	if (argc < 1) {
 		printf ("Usage:\n%s\n", cmdtp->usage);
 		return 1;
 	}
-	if (argc > 1) {
-		MTS (val);
-		MFS (val);
-	} else {
-		MFS (val);
+	switch (reg) {
+	case 0x1:
+		if (argc > 2) {
+			MTS (val, rmsr);
+			NOP;
+			MFS (val, rmsr);
+
+		} else {
+			MFS (val, rmsr);
+		}
+		puts ("MSR");
+		break;
+	case 0x3:
+		MFS (val, rear);
+		puts ("EAR");
+		break;
+	case 0x5:
+		MFS (val, resr);
+		puts ("ESR");
+		break;
+	default:
+		return 1;
 	}
-	printf ("rmsr: 0x%08lx\n", val);
+	printf (": 0x%08lx\n", val);
 	return 0;
 }
 
@@ -388,7 +407,11 @@ U_BOOT_CMD (fwr, 4, 1, do_fwr,
 		" 2 - blocking data write\n"
 		" 3 - blocking control write\n");
 
-U_BOOT_CMD (rmsr, 2, 1, do_rmsr,
-	    "rmsr    - read MSR register\n", "- read MSR register.\n");
+U_BOOT_CMD (rspr, 3, 1, do_rspr,
+		"rmsr    - read/write special purpose register\n",
+		"- reg_num [write value] read/write special purpose register\n"
+		" 0 - MSR - Machine status register\n"
+		" 1 - EAR - Exception address register\n"
+		" 2 - ESR - Exception status register\n");
 
 #endif				/* CONFIG_MICROBLAZE & CFG_CMD_MFSL */
diff --git a/cpu/microblaze/exception.c b/cpu/microblaze/exception.c
index 87ecbeaa49..d76b05a526 100644
--- a/cpu/microblaze/exception.c
+++ b/cpu/microblaze/exception.c
@@ -30,9 +30,9 @@ void _hw_exception_handler (void)
 	int address = 0;
 	int state = 0;
 	/* loading address of exception EAR */
-	MFSEAR(address);
+	MFS (address, rear);
 	/* loading excetpion state register ESR */
-	MFSESR(state);
+	MFS (state, resr);
 	printf ("Hardware exception at 0x%x address\n", address);
 	switch (state & 0x1f) {	/* mask on exception cause */
 	case 0x1:
diff --git a/include/asm-microblaze/asm.h b/include/asm-microblaze/asm.h
index 8302ed8850..f10f89c941 100755
--- a/include/asm-microblaze/asm.h
+++ b/include/asm-microblaze/asm.h
@@ -49,23 +49,18 @@
 
 /* CPU dependent */
 /* machine status register */
-#define MFS(val) \
-	__asm__ __volatile__ ("mfs %0, rmsr":"=r" (val));
+#define MFS(val, reg) \
+	__asm__ __volatile__ ("mfs %0," #reg :"=r" (val));
 
-#define MTS(val) \
-	__asm__ __volatile__ ("mts rmsr, %0"::"r" (val));
-
-/* exception status register */
-#define MFSEAR(val) \
-	__asm__ __volatile ("mfs %0,rear":"=r" (val));
-
-#define MFSESR(val) \
-	__asm__ __volatile ("mfs %0,resr":"=r" (val));
+#define MTS(val, reg) \
+	__asm__ __volatile__ ("mts " #reg ", %0"::"r" (val));
 
 /* get return address from interrupt */
 #define R14(val) \
 	__asm__ __volatile__ ("addi %0, r14, 0":"=r" (val));
 
+#define NOP	__asm__ __volatile__ ("nop");
+
 /* use machine status registe USE_MSR_REG */
 #ifdef XILINX_USE_MSR_INSTR
 #define MSRSET(val) \