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MIPS: Clear hazard between TagLo writes & cache ops 

Writing to the coprocessor 0 TagLo registers introduces an execution
hazard in that we need that write to complete before any cache
instructions execute. Ensure that hazard is cleared by inserting an ehb
instruction between the TagLo writes & cache op loop.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
This commit is contained in:
Paul Burton 2016-09-21 11:18:58 +01:00 committed by Daniel Schwierzeck
parent c5b8412d60
commit d608254b0a
1 changed files with 1 additions and 0 deletions
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1
arch/mips/lib/cache_init.S
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@ -293,6 +293,7 @@ l2_init:
l1_init:
mtc0 zero, CP0_TAGLO
mtc0 zero, CP0_TAGLO, 2
ehb
/*
* The caches are probably in an indeterminate state, so we force good