sysmo-bts
/
u-boot
9
0
Fork 0
Code Pull Requests Releases Activity

spi: spi-mxc: add defines for clk inactive state for ECSPI 

Provide define for the SCLK_CTL field of the config reg of ECSPI.
While at it, oder the defines to improve readability and make
adding more defines easier.

Signed-off-by: Markus Niebel <Markus.Niebel@tqs.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
This commit is contained in:
Markus Niebel 2014-02-17 17:33:16 +01:00 committed by Jagannadha Sutradharudu Teki
parent 999c39a45f
commit d7cbcc762e
2 changed files with 8 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
arch/arm/include/asm/arch-mx5/imx-regs.h
View File

@ -230,9 +230,10 @@
#define MXC_CSPICTRL_CHAN 18 #define MXC_CSPICTRL_CHAN 18
/* Bit position inside CON register to be associated with SS */ /* Bit position inside CON register to be associated with SS */
#define MXC_CSPICON_POL 4 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
#define MXC_CSPICON_PHA 0 #define MXC_CSPICON_POL 4 /* SCLK polarity */
#define MXC_CSPICON_SSPOL 12 #define MXC_CSPICON_SSPOL 12 /* SS polarity */
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#define MXC_SPI_BASE_ADDRESSES \ #define MXC_SPI_BASE_ADDRESSES \
CSPI1_BASE_ADDR, \ CSPI1_BASE_ADDR, \
CSPI2_BASE_ADDR, \ CSPI2_BASE_ADDR, \

7
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -405,9 +405,10 @@ struct cspi_regs {
#define MXC_CSPICTRL_CHAN 18 #define MXC_CSPICTRL_CHAN 18
/* Bit position inside CON register to be associated with SS */ /* Bit position inside CON register to be associated with SS */
#define MXC_CSPICON_POL 4 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
#define MXC_CSPICON_PHA 0 #define MXC_CSPICON_POL 4 /* SCLK polarity */
#define MXC_CSPICON_SSPOL 12 #define MXC_CSPICON_SSPOL 12 /* SS polarity */
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#ifdef CONFIG_MX6SL #ifdef CONFIG_MX6SL
#define MXC_SPI_BASE_ADDRESSES \ #define MXC_SPI_BASE_ADDRESSES \
ECSPI1_BASE_ADDR, \ ECSPI1_BASE_ADDR, \