arm: Remove qong board

This board has not been converted to generic board by the deadline.
Remove it.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2015-08-30 19:19:25 -06:00 committed by Tom Rini
parent 49d8899ba9
commit daf770864d
10 changed files with 0 additions and 904 deletions

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@ -239,10 +239,6 @@ config TARGET_IMX31_PHYCORE
bool "Support imx31_phycore"
select CPU_ARM1136
config TARGET_QONG
bool "Support qong"
select CPU_ARM1136
config TARGET_MX31ADS
bool "Support mx31ads"
select CPU_ARM1136
@ -751,7 +747,6 @@ source "board/cirrus/edb93xx/Kconfig"
source "board/compulab/cm_t335/Kconfig"
source "board/compulab/cm_t43/Kconfig"
source "board/creative/xfi3/Kconfig"
source "board/davedenx/qong/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/freescale/ls2085a/Kconfig"

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@ -1,15 +0,0 @@
if TARGET_QONG
config SYS_BOARD
default "qong"
config SYS_VENDOR
default "davedenx"
config SYS_SOC
default "mx31"
config SYS_CONFIG_NAME
default "qong"
endif

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@ -1,6 +0,0 @@
QONG BOARD
M: Wolfgang Denk <wd@denx.de>
S: Maintained
F: board/davedenx/qong/
F: include/configs/qong.h
F: configs/qong_defconfig

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@ -1,11 +0,0 @@
#
# (C) Copyright 2009
# Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := qong.o fpga.o
obj-y += lowlevel_init.o

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@ -1,77 +0,0 @@
/*
* (C) Copyright 2010
* Stefano Babic, DENX Software Engineering, sbabic@denx.de
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/gpio.h>
#include <fpga.h>
#include <lattice.h>
#include "qong_fpga.h"
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_FPGA)
static void qong_jtag_init(void)
{
return;
}
static void qong_fpga_jtag_set_tdi(int value)
{
gpio_set_value(QONG_FPGA_TDI_PIN, value);
}
static void qong_fpga_jtag_set_tms(int value)
{
gpio_set_value(QONG_FPGA_TMS_PIN, value);
}
static void qong_fpga_jtag_set_tck(int value)
{
gpio_set_value(QONG_FPGA_TCK_PIN, value);
}
static int qong_fpga_jtag_get_tdo(void)
{
return gpio_get_value(QONG_FPGA_TDO_PIN);
}
lattice_board_specific_func qong_fpga_fns = {
qong_jtag_init,
qong_fpga_jtag_set_tdi,
qong_fpga_jtag_set_tms,
qong_fpga_jtag_set_tck,
qong_fpga_jtag_get_tdo
};
Lattice_desc qong_fpga[CONFIG_FPGA_COUNT] = {
{
Lattice_XP2,
lattice_jtag_mode,
356519,
(void *) &qong_fpga_fns,
NULL,
0,
"lfxp2_5e_ftbga256"
},
};
int qong_fpga_init(void)
{
int i;
fpga_init();
for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
fpga_add(fpga_lattice, &qong_fpga[i]);
}
return 0;
}
#endif

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@ -1,223 +0,0 @@
/*
* Copyright (C) 2009, Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
*
* Based on board/freescale/mx31ads/lowlevel_init.S
* by Guennadi Liakhovetski.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm/arch/imx-regs.h>
.macro REG reg, val
ldr r2, =\reg
ldr r3, =\val
str r3, [r2]
.endm
.macro REG8 reg, val
ldr r2, =\reg
ldr r3, =\val
strb r3, [r2]
.endm
.macro DELAY loops
ldr r2, =\loops
1:
subs r2, r2, #1
nop
bcs 1b
.endm
.macro SETUP_RAM cfg, ctl
/* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
REG 0xB8001010, 0x00000004
ldr r3, =\cfg
ldr r2, =WEIM_ESDCFG0
str r3, [r2]
REG 0xB8001000, 0x92100000
REG 0x80000f00, 0x12344321
REG 0xB8001000, 0xa2100000
REG 0x80000000, 0x12344321
REG 0x80000000, 0x12344321
REG 0xB8001000, 0xb2100000
REG8 0x80000033, 0xda
REG8 0x81000000, 0xff
ldr r3, =\ctl
ldr r2, =WEIM_ESDCTL0
str r3, [r2]
REG 0x80000000, 0xDEADBEEF
REG 0xB8001010, 0x0000000c
.endm
/* RedBoot: To support 133MHz DDR */
.macro init_drive_strength
/*
* Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
* in SW_PAD_CTL registers
*/
/* SDCLK */
ldr r1, =IOMUXC_SW_PAD_CTL(0x2b)
ldr r0, [r1, #0x6C]
bic r0, r0, #(1 << 12)
str r0, [r1, #0x6C]
/* CAS */
ldr r0, [r1, #0x70]
bic r0, r0, #(1 << 22)
str r0, [r1, #0x70]
/* RAS */
ldr r0, [r1, #0x74]
bic r0, r0, #(1 << 2)
str r0, [r1, #0x74]
/* CS2 (CSD0) */
ldr r0, [r1, #0x7C]
bic r0, r0, #(1 << 22)
str r0, [r1, #0x7C]
/* DQM3 */
ldr r0, [r1, #0x84]
bic r0, r0, #(1 << 22)
str r0, [r1, #0x84]
/* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */
pad_loop:
ldr r0, [r1, #0x88]
bic r0, r0, #(1 << 22)
bic r0, r0, #(1 << 12)
bic r0, r0, #(1 << 2)
str r0, [r1, #0x88]
add r1, r1, #4
subs r2, r2, #0x1
bne pad_loop
.endm /* init_drive_strength */
.globl lowlevel_init
lowlevel_init:
init_drive_strength
/* Image Processing Unit: */
/* Too early to switch display on? */
/* Switch on Display Interface */
REG IPU_CONF, IPU_CONF_DI_EN
/* Clock Control Module: */
REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */
DELAY 0x40000
REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */
/* Switch to MCU PLL */
REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
/* 399-133-66.5 */
ldr r0, =CCM_BASE
ldr r1, =0xFF871650
/* PDR0 */
str r1, [r0, #0x4]
ldr r1, MPCTL_PARAM_399
/* MPCTL */
str r1, [r0, #0x10]
/* Set UPLL=240MHz, USB=60MHz */
ldr r1, =0x49FCFE7F
/* PDR1 */
str r1, [r0, #0x8]
ldr r1, UPCTL_PARAM_240
/* UPCTL */
str r1, [r0, #0x14]
/* default CLKO to 1/8 of the ARM core */
mov r1, #0x00000208
/* COSR */
str r1, [r0, #0x1c]
/* Default: 1, 4, 12, 1 */
REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
check_ddr_module:
/* Set stackpointer in internal RAM to call get_ram_size */
ldr sp, =(IRAM_BASE_ADDR + IRAM_SIZE - 16)
stmfd sp!, {r0-r11, ip, lr}
mov ip, lr /* save link reg across call */
ldr r0,=0x08000000
SETUP_RAM ESDCFG0_256MB, ESDCTL0_256MB
ldr r0,=0x80000000
ldr r1,=0x10000000
bl get_ram_size
ldr r1,=0x10000000
cmp r0,r1
beq restore_regs
SETUP_RAM ESDCFG0_128MB, ESDCTL0_128MB
ldr r0,=0x80000000
ldr r1,=0x08000000
bl get_ram_size
ldr r1,=0x08000000
cmp r0,r1
beq restore_regs
restore_regs:
ldmfd sp!, {r0-r11, ip, lr}
mov lr, ip /* restore link reg */
mov pc, lr
MPCTL_PARAM_399:
.word (((1 - 1) << 26) + ((52 - 1) << 16) + (7 << 10) + (35 << 0))
UPCTL_PARAM_240:
.word (((2 - 1) << 26) + ((13 - 1) << 16) + (9 << 10) + (3 << 0))
.equ ESDCFG0_128MB, \
(0 << 21) + /* tXP */ \
(1 << 20) + /* tWTR */ \
(2 << 18) + /* tRP */ \
(1 << 16) + /* tMRD */ \
(0 << 15) + /* tWR */ \
(5 << 12) + /* tRAS */ \
(1 << 10) + /* tRRD */ \
(3 << 8) + /* tCAS */ \
(2 << 4) + /* tRCD */ \
(0x0F << 0) /* tRC */
.equ ESDCTL0_128MB, \
(1 << 31) + /* enable */ \
(0 << 28) + /* mode */ \
(0 << 27) + /* supervisor protect */ \
(2 << 24) + /* 13 rows */ \
(2 << 20) + /* 10 cols */ \
(2 << 16) + /* 32 bit */ \
(3 << 13) + /* 7.81us (64ms/8192) */ \
(0 << 10) + /* power down timer */ \
(0 << 8) + /* full page */ \
(1 << 7) + /* burst length */ \
(0 << 0) /* precharge timer */
.equ ESDCFG0_256MB, \
(3 << 21) + /* tXP */ \
(0 << 20) + /* tWTR */ \
(2 << 18) + /* tRP */ \
(1 << 16) + /* tMRD */ \
(0 << 15) + /* tWR */ \
(5 << 12) + /* tRAS */ \
(1 << 10) + /* tRRD */ \
(3 << 8) + /* tCAS */ \
(2 << 4) + /* tRCD */ \
(7 << 0) /* tRC */
.equ ESDCTL0_256MB, \
(1 << 31) + \
(0 << 28) + \
(0 << 27) + \
(3 << 24) + /* 14 rows */ \
(2 << 20) + /* 10 cols */ \
(2 << 16) + \
(4 << 13) + /* 3.91us (64ms/16384) */ \
(0 << 10) + \
(0 << 8) + \
(1 << 7) + \
(0 << 0)

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@ -1,259 +0,0 @@
/*
*
* (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include <nand.h>
#include <power/pmic.h>
#include <fsl_pmic.h>
#include <asm/gpio.h>
#include "qong_fpga.h"
#include <watchdog.h>
#include <errno.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
return 0;
}
static void qong_fpga_reset(void)
{
gpio_set_value(QONG_FPGA_RST_PIN, 0);
udelay(30);
gpio_set_value(QONG_FPGA_RST_PIN, 1);
udelay(300);
}
int board_early_init_f(void)
{
#ifdef CONFIG_QONG_FPGA
/* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */
static const struct mxc_weimcs cs1 = {
/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1),
/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1),
/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0)
};
mxc_setup_weimcs(1, &cs1);
/* setup pins for FPGA */
mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO));
mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO));
mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO));
mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO));
mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO));
/* FPGA reset Pin */
/* rstn = 0 */
gpio_direction_output(QONG_FPGA_RST_PIN, 0);
/* set interrupt pin as input */
gpio_direction_input(QONG_FPGA_IRQ_PIN);
/* FPGA JTAG Interface */
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
gpio_direction_output(QONG_FPGA_TCK_PIN, 0);
gpio_direction_output(QONG_FPGA_TMS_PIN, 0);
gpio_direction_output(QONG_FPGA_TDI_PIN, 0);
gpio_direction_input(QONG_FPGA_TDO_PIN);
#endif
/* setup pins for UART1 */
mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
/* setup pins for SPI (pmic) */
mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
/* Setup pins for USB2 Host */
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
mx31_set_gpr(MUX_PGP_UH2, 1);
return 0;
}
int board_init(void)
{
/* Chip selects */
/* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */
/* Assumptions: HCLK = 133 MHz, tACC = 130ns */
static const struct mxc_weimcs cs0 = {
/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 3, 21, 0, 0, 6),
/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
CSCR_L(0, 1, 3, 3, 1, 1, 5, 1, 0, 0, 0, 1),
/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
CSCR_A(0, 1, 2, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
};
mxc_setup_weimcs(0, &cs0);
/* board id for linux */
gd->bd->bi_arch_number = MACH_TYPE_QONG;
gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
qong_fpga_init();
return 0;
}
int board_late_init(void)
{
u32 val;
struct pmic *p;
int ret;
ret = pmic_init(I2C_PMIC);
if (ret)
return ret;
p = pmic_get("FSL_PMIC");
if (!p)
return -ENODEV;
/* Enable RTC battery */
pmic_reg_read(p, REG_POWER_CTL0, &val);
pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN);
pmic_reg_write(p, REG_INT_STATUS1, RTCRSTI);
#ifdef CONFIG_HW_WATCHDOG
hw_watchdog_init();
#endif
return 0;
}
int checkboard(void)
{
printf("Board: DAVE/DENX Qong\n");
return 0;
}
int misc_init_r(void)
{
#ifdef CONFIG_QONG_FPGA
u32 tmp;
tmp = *(volatile u32*)QONG_FPGA_CTRL_VERSION;
printf("FPGA: ");
printf("version register = %u.%u.%u\n",
(tmp & 0xF000) >> 12, (tmp & 0x0F00) >> 8, tmp & 0x00FF);
#endif
return 0;
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_DNET)
return dnet_eth_initialize(0, (void *)CONFIG_DNET_BASE, -1);
#else
return 0;
#endif
}
#if defined(CONFIG_QONG_FPGA) && defined(CONFIG_NAND_PLAT)
static void board_nand_setup(void)
{
/* CS3: NAND 8-bit */
static const struct mxc_weimcs cs3 = {
/* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 1, 15, 0, 0, 0),
/* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
CSCR_L(2, 0, 0, 1, 3, 1, 3, 3, 0, 0, 0, 1),
/* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
CSCR_A(0, 0, 0, 2, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0)
};
mxc_setup_weimcs(3, &cs3);
mx31_set_gpr(MUX_SDCTL_CSD1_SEL, 1);
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_WP, MUX_CTL_IN_GPIO));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_CE, MUX_CTL_IN_GPIO));
mx31_gpio_mux(IOMUX_MODE(MUX_CTL_NFC_RB, MUX_CTL_IN_GPIO));
/* Make sure to reset the fpga else you cannot access NAND */
qong_fpga_reset();
/* Enable NAND flash */
gpio_set_value(15, 1);
gpio_set_value(14, 1);
gpio_direction_output(15, 0);
gpio_direction_input(16);
gpio_direction_input(14);
}
int qong_nand_rdy(void *chip)
{
udelay(1);
return gpio_get_value(16);
}
void qong_nand_select_chip(struct mtd_info *mtd, int chip)
{
if (chip >= 0)
gpio_set_value(15, 0);
else
gpio_set_value(15, 1);
}
void qong_nand_plat_init(void *chip)
{
struct nand_chip *nand = (struct nand_chip *)chip;
nand->chip_delay = 20;
nand->select_chip = qong_nand_select_chip;
nand->options &= ~NAND_BUSWIDTH_16;
board_nand_setup();
}
#endif

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@ -1,23 +0,0 @@
/*
*
* (c) 2009 Emcraft Systems, Ilya Yanok <yanok@emcraft.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef QONG_FPGA_H
#define QONG_FPGA_H
#define QONG_FPGA_CTRL_BASE CONFIG_FPGA_BASE
#define QONG_FPGA_CTRL_VERSION (QONG_FPGA_CTRL_BASE + 0x00000000)
#define QONG_FPGA_PERIPH_SIZE (1 << 24)
#define QONG_FPGA_TCK_PIN 26
#define QONG_FPGA_TMS_PIN 25
#define QONG_FPGA_TDI_PIN 8
#define QONG_FPGA_TDO_PIN 7
#define QONG_FPGA_RST_PIN 48
#define QONG_FPGA_IRQ_PIN 40
int qong_fpga_init(void);
#endif /* QONG_FPGA_H */

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@ -1,2 +0,0 @@
CONFIG_ARM=y
CONFIG_TARGET_QONG=y

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@ -1,283 +0,0 @@
/*
* Copyright (C) 2009, Ilya Yanok, Emcraft Systems, <yanok@emcraft.com>
*
* Configuration settings for the Dave/DENX QongEVB-LITE board.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <asm/arch/imx-regs.h>
/* High Level Configuration Options */
#define CONFIG_MX31 /* This is a mx31 */
#define CONFIG_QONG
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_SYS_TEXT_BASE 0xa0000000
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1536 * 1024)
/*
* Hardware drivers
*/
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART1_BASE
#define CONFIG_MXC_GPIO
#define CONFIG_HW_WATCHDOG
#define CONFIG_IMX_WATCHDOG
#define CONFIG_MXC_SPI
#define CONFIG_DEFAULT_SPI_BUS 1
#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_RTC_MC13XXX
#define CONFIG_POWER
#define CONFIG_POWER_SPI
#define CONFIG_POWER_FSL
#define CONFIG_FSL_PMIC_BUS 1
#define CONFIG_FSL_PMIC_CS 0
#define CONFIG_FSL_PMIC_CLK 100000
#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH)
#define CONFIG_FSL_PMIC_BITLEN 32
/* FPGA */
#define CONFIG_FPGA
#define CONFIG_QONG_FPGA
#define CONFIG_FPGA_BASE (CS1_BASE)
#define CONFIG_FPGA_LATTICE
#define CONFIG_FPGA_COUNT 1
#ifdef CONFIG_QONG_FPGA
/* Ethernet */
#define CONFIG_DNET
#define CONFIG_DNET_BASE (CS1_BASE + QONG_FPGA_PERIPH_SIZE)
/* Framebuffer and LCD */
#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_MX3
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_SW_CURSOR
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
#define CONFIG_SPLASH_SCREEN
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10)
/* USB */
#define CONFIG_CMD_USB
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_USB_EHCI_MXC
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORT 2
#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_SUPPORT_VFAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#endif /* CONFIG_CMD_USB */
/*
* Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
* initial TFTP transfer, should the user wish one, significantly.
*/
#define CONFIG_ARP_TIMEOUT 200UL
#endif /* CONFIG_QONG_FPGA */
#define CONFIG_CONS_INDEX 1
#define CONFIG_BAUDRATE 115200
/***********************************************************
* Command definition
***********************************************************/
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_SPI
#define CONFIG_CMD_UNZIP
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_BOOTDELAY 5
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs}" \
" console=ttymxc0,${baudrate}\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addmisc=setenv bootargs ${bootargs}\0" \
"uboot_addr=A0000000\0" \
"kernel_addr=A00C0000\0" \
"ramdisk_addr=A0300000\0" \
"u-boot=qong/u-boot.bin\0" \
"kernel_addr_r=80800000\0" \
"hostname=qong\0" \
"bootfile=qong/uImage\0" \
"rootpath=/opt/eldk-4.2-arm/armVFP\0" \
"flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr}\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
"run nfsargs addip addtty addmtd addmisc;" \
"bootm\0" \
"bootcmd=run flash_self\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
" +${filesize};cp.b ${fileaddr} " \
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
"videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \
"le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \
"vmode:0\0" \
/*
* Miscellaneous configurable options
*/
#define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* memtest works on first 255MB of RAM */
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0xff000000)
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
#define CONFIG_MISC_INIT_R
/*-----------------------------------------------------------------------
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_BASE
#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */
/*
* NAND driver
*/
#ifndef __ASSEMBLY__
extern void qong_nand_plat_init(void *chip);
extern int qong_nand_rdy(void *chip);
#endif
#define CONFIG_NAND_PLAT
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE CS3_BASE
#define NAND_PLAT_INIT() qong_nand_plat_init(nand)
#define QONG_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 24))
#define QONG_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 23))
#define QONG_NAND_WRITE(addr, cmd) \
do { \
__REG8(addr) = cmd; \
} while (0)
#define NAND_PLAT_WRITE_CMD(chip, cmd) QONG_NAND_WRITE(QONG_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) QONG_NAND_WRITE(QONG_NAND_ALE(chip), cmd)
#define NAND_PLAT_DEV_READY(chip) (qong_nand_rdy(chip))
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
#define CONFIG_SYS_FLASH_BASE CS0_BASE
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_SECT 1024
/* Monitor at beginning of flash */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x80000)
/* Address and size of Redundant Environment Sector */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
/*-----------------------------------------------------------------------
* CFI FLASH driver setup
*/
/* Flash memory is CFI compliant */
#define CONFIG_SYS_FLASH_CFI
/* Use drivers/cfi_flash.c */
#define CONFIG_FLASH_CFI_DRIVER
/* Use buffered writes (~10x faster) */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
/* Use hardware sector protection */
#define CONFIG_SYS_FLASH_PROTECTION
/*
* Filesystem
*/
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_LZO
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \
"nand0=gen_nand"
#define MTDPARTS_DEFAULT \
"mtdparts=physmap-flash.0:" \
"512k(U-Boot),128k(env1),128k(env2)," \
"2304k(kernel),13m(ramdisk),-(user);" \
"gen_nand:" \
"128m(nand)"
/* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)
#define CONFIG_BOARD_EARLY_INIT_F
#endif /* __CONFIG_H */