at91sam9/at91cap: improve clock framework
calculate dynamically the clock rate and pllb setting for usb Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
parent
f75a729b5c
commit
dc39ae9513
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@ -29,6 +29,7 @@
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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@ -283,7 +284,7 @@ void lcd_show_board_info(void)
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lcd_printf ("at91support@atmel.com\n");
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lcd_printf ("%s CPU at %s MHz\n",
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AT91_CPU_NAME,
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strmhz(temp, AT91_CPU_CLOCK));
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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@ -29,6 +29,7 @@
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <lcd.h>
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@ -185,7 +186,7 @@ void lcd_show_board_info(void)
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lcd_printf ("at91support@atmel.com\n");
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lcd_printf ("%s CPU at %s MHz\n",
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AT91_CPU_NAME,
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strmhz(temp, AT91_CPU_CLOCK));
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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@ -30,6 +30,7 @@
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/hardware.h>
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@ -206,7 +207,7 @@ void lcd_show_board_info(void)
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lcd_printf ("at91support@atmel.com\n");
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lcd_printf ("%s CPU at %s MHz\n",
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AT91_CPU_NAME,
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strmhz(temp, AT91_CPU_CLOCK));
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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@ -29,6 +29,7 @@
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#include <asm/arch/at91_common.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/at91_rstc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <lcd.h>
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@ -157,7 +158,7 @@ void lcd_show_board_info(void)
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lcd_printf ("at91support@atmel.com\n");
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lcd_printf ("%s CPU at %s MHz\n",
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AT91_CPU_NAME,
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strmhz(temp, AT91_CPU_CLOCK));
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strmhz(temp, get_cpu_clk_rate()));
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dram_size = 0;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
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@ -55,6 +55,8 @@ COBJS-y += at91sam9rl_serial.o
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COBJS-$(CONFIG_HAS_DATAFLASH) += at91sam9rl_spi.o
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endif
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COBJS-$(CONFIG_AT91_LED) += led.o
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COBJS-y += clock.o
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COBJS-y += cpu.o
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COBJS-y += timer.o
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SOBJS = lowlevel_init.o
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@ -0,0 +1,202 @@
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/*
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* [origin: Linux kernel linux/arch/arm/mach-at91/clock.c]
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*
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* Copyright (C) 2005 David Brownell
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <config.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/io.h>
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static unsigned long cpu_clk_rate_hz;
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static unsigned long main_clk_rate_hz;
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static unsigned long mck_rate_hz;
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static unsigned long plla_rate_hz;
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static unsigned long pllb_rate_hz;
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static u32 at91_pllb_usb_init;
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unsigned long get_cpu_clk_rate(void)
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{
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return cpu_clk_rate_hz;
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}
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unsigned long get_main_clk_rate(void)
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{
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return main_clk_rate_hz;
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}
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unsigned long get_mck_clk_rate(void)
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{
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return mck_rate_hz;
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}
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unsigned long get_plla_clk_rate(void)
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{
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return plla_rate_hz;
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}
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unsigned long get_pllb_clk_rate(void)
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{
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return pllb_rate_hz;
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}
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u32 get_pllb_init(void)
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{
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return at91_pllb_usb_init;
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}
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static unsigned long at91_css_to_rate(unsigned long css)
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{
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switch (css) {
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case AT91_PMC_CSS_SLOW:
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return AT91_SLOW_CLOCK;
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case AT91_PMC_CSS_MAIN:
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return main_clk_rate_hz;
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case AT91_PMC_CSS_PLLA:
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return plla_rate_hz;
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case AT91_PMC_CSS_PLLB:
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return pllb_rate_hz;
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}
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return 0;
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}
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#ifdef CONFIG_USB_ATMEL
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static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
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{
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unsigned i, div = 0, mul = 0, diff = 1 << 30;
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unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
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/* PLL output max 240 MHz (or 180 MHz per errata) */
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if (out_freq > 240000000)
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goto fail;
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for (i = 1; i < 256; i++) {
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int diff1;
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unsigned input, mul1;
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/*
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* PLL input between 1MHz and 32MHz per spec, but lower
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* frequences seem necessary in some cases so allow 100K.
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* Warning: some newer products need 2MHz min.
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*/
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input = main_freq / i;
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#if defined(CONFIG_AT91SAM9G20)
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if (input < 2000000)
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continue;
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#endif
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if (input < 100000)
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continue;
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if (input > 32000000)
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continue;
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mul1 = out_freq / input;
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#if defined(CONFIG_AT91SAM9G20)
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if (mul > 63)
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continue;
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#endif
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if (mul1 > 2048)
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continue;
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if (mul1 < 2)
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goto fail;
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diff1 = out_freq - input * mul1;
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if (diff1 < 0)
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diff1 = -diff1;
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if (diff > diff1) {
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diff = diff1;
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div = i;
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mul = mul1;
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if (diff == 0)
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break;
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}
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}
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if (i == 256 && diff > (out_freq >> 5))
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goto fail;
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return ret | ((mul - 1) << 16) | div;
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fail:
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return 0;
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}
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static u32 at91_pll_rate(u32 freq, u32 reg)
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{
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unsigned mul, div;
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div = reg & 0xff;
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mul = (reg >> 16) & 0x7ff;
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if (div && mul) {
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freq /= div;
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freq *= mul + 1;
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} else
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freq = 0;
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return freq;
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}
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#endif
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int at91_clock_init(unsigned long main_clock)
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{
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unsigned freq, mckr;
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#ifndef AT91_MAIN_CLOCK
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unsigned tmp;
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/*
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* When the bootloader initialized the main oscillator correctly,
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* there's no problem using the cycle counter. But if it didn't,
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* or when using oscillator bypass mode, we must be told the speed
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* of the main clock.
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*/
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if (!main_clock) {
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do {
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tmp = at91_sys_read(AT91_CKGR_MCFR);
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} while (!(tmp & AT91_PMC_MAINRDY));
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main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
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}
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#endif
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main_clk_rate_hz = main_clock;
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/* report if PLLA is more than mildly overclocked */
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plla_rate_hz = at91_pll_rate(main_clock, at91_sys_read(AT91_CKGR_PLLAR));
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#ifdef CONFIG_USB_ATMEL
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/*
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* USB clock init: choose 48 MHz PLLB value,
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* disable 48MHz clock during usb peripheral suspend.
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*
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* REVISIT: assumes MCK doesn't derive from PLLB!
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*/
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at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
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AT91_PMC_USB96M;
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pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
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#endif
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/*
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* MCK and CPU derive from one of those primary clocks.
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* For now, assume this parentage won't change.
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*/
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mckr = at91_sys_read(AT91_PMC_MCKR);
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freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS);
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freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
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#if defined(CONFIG_AT91RM9200)
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mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
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#elif defined(CONFIG_AT91SAM9G20)
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mck_rate_hz = (mckr & AT91_PMC_MDIV) ?
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freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
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if (mckr & AT91_PMC_PDIV)
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freq /= 2; /* processor clock division */
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#else
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mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
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#endif
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cpu_clk_rate_hz = freq;
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return 0;
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}
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@ -0,0 +1,14 @@
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#include <config.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/io.h>
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int arch_cpu_init(void)
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{
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#ifdef AT91_MAIN_CLOCK
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return at91_clock_init(AT91_MAIN_CLOCK);
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#else
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return at91_clock_init(0);
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#endif
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}
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@ -21,6 +21,7 @@
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/io.h>
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#include <asm/arch/at91_pio.h>
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@ -45,7 +46,7 @@ void AT91F_SpiInit(void)
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writel(AT91_SPI_NCPHA |
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(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
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(AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
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((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
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((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
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AT91_BASE_SPI + AT91_SPI_CSR(0));
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#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
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@ -53,7 +54,7 @@ void AT91F_SpiInit(void)
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writel(AT91_SPI_NCPHA |
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(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
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(AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
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((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
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((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
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AT91_BASE_SPI + AT91_SPI_CSR(1));
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#endif
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@ -62,7 +63,7 @@ void AT91F_SpiInit(void)
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writel(AT91_SPI_NCPHA |
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(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
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(AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
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((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
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((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
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AT91_BASE_SPI + AT91_SPI_CSR(3));
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#endif
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@ -28,6 +28,7 @@
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#include <asm/arch/hardware.h>
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#include <asm/arch/io.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/clk.h>
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int usb_cpu_init(void)
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{
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@ -35,7 +36,7 @@ int usb_cpu_init(void)
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#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
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defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20)
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/* Enable PLLB */
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at91_sys_write(AT91_CKGR_PLLBR, CONFIG_SYS_AT91_PLLB);
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at91_sys_write(AT91_CKGR_PLLBR, get_pllb_init());
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while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
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;
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#endif
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@ -1,5 +1,5 @@
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/*
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* [origin: Linux kernel include/asm-arm/arch-at91/at91_pmc.h]
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* [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_pmc.h]
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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@ -23,6 +23,7 @@
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#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
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#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
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#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
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#define AT91CAP9_PMC_DDR (1 << 2) /* DDR Clock [AT91CAP9 revC only] */
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#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
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#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
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#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
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@ -39,10 +40,14 @@
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#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
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#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
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#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
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#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
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#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
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#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
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#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
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#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
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#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
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#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
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#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
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#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
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@ -76,10 +81,17 @@
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#define AT91_PMC_PRES_32 (5 << 2)
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#define AT91_PMC_PRES_64 (6 << 2)
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#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
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#define AT91_PMC_MDIV_1 (0 << 8)
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#define AT91_PMC_MDIV_2 (1 << 8)
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#define AT91_PMC_MDIV_3 (2 << 8)
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#define AT91_PMC_MDIV_4 (3 << 8)
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#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
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#define AT91RM9200_PMC_MDIV_2 (1 << 8)
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#define AT91RM9200_PMC_MDIV_3 (2 << 8)
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#define AT91RM9200_PMC_MDIV_4 (3 << 8)
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#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
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#define AT91SAM9_PMC_MDIV_2 (1 << 8)
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#define AT91SAM9_PMC_MDIV_4 (2 << 8)
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#define AT91SAM9_PMC_MDIV_6 (3 << 8)
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#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
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||||
#define AT91_PMC_PDIV_1 (0 << 12)
|
||||
#define AT91_PMC_PDIV_2 (1 << 12)
|
||||
|
||||
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
|
||||
|
||||
|
|
@ -90,6 +102,8 @@
|
|||
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
|
||||
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
|
||||
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
|
||||
#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */
|
||||
#define AT91_PMC_OSCSEL (1 << 7) /* Slow Clock Oscillator [AT91CAP9 revC only] */
|
||||
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
|
||||
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
|
||||
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
|
||||
|
|
@ -97,8 +111,8 @@
|
|||
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
|
||||
|
||||
#define AT91_PMC_PROT (AT91_PMC + 0xe4) /* Protect Register [AT91CAP9 revC only] */
|
||||
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
|
||||
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
|
||||
|
||||
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
|
||||
#define AT91_PMC_VER (AT91_PMC + 0xfc) /* PMC Module Version [AT91CAP9 only] */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* (C) Copyright 2007
|
||||
* Stelian Pop <stelian.pop@leadtechdesign.com>
|
||||
* Lead Tech Design <www.leadtechdesign.com>
|
||||
* Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
|
|
@ -26,20 +27,32 @@
|
|||
|
||||
#include <asm/arch/hardware.h>
|
||||
|
||||
unsigned long get_cpu_clk_rate(void);
|
||||
unsigned long get_main_clk_rate(void);
|
||||
unsigned long get_mck_clk_rate(void);
|
||||
unsigned long get_plla_clk_rate(void);
|
||||
unsigned long get_pllb_clk_rate(void);
|
||||
unsigned int get_pllb_init(void);
|
||||
|
||||
static inline unsigned long get_macb_pclk_rate(unsigned int dev_id)
|
||||
{
|
||||
return AT91_MASTER_CLOCK;
|
||||
return get_mck_clk_rate();
|
||||
}
|
||||
|
||||
static inline unsigned long get_usart_clk_rate(unsigned int dev_id)
|
||||
{
|
||||
return AT91_MASTER_CLOCK;
|
||||
return get_mck_clk_rate();
|
||||
}
|
||||
|
||||
static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id)
|
||||
{
|
||||
return AT91_MASTER_CLOCK;
|
||||
return get_mck_clk_rate();
|
||||
}
|
||||
|
||||
static inline unsigned long get_twi_clk_rate(unsigned int dev_id)
|
||||
{
|
||||
return get_mck_clk_rate();
|
||||
}
|
||||
|
||||
int at91_clock_init(unsigned long main_clock);
|
||||
#endif /* __ASM_ARM_ARCH_CLK_H__ */
|
||||
|
|
|
|||
|
|
@ -48,4 +48,7 @@
|
|||
#error "Unsupported AT91 processor"
|
||||
#endif
|
||||
|
||||
/* Clocks */
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -40,6 +40,9 @@ extern ulong FIQ_STACK_START; /* top of FIQ stack */
|
|||
int cpu_init(void);
|
||||
int cleanup_before_linux(void);
|
||||
|
||||
/* cpu/.../arch/cpu.c */
|
||||
int arch_cpu_init(void);
|
||||
|
||||
/* board/.../... */
|
||||
int board_init(void);
|
||||
int dram_init (void);
|
||||
|
|
|
|||
|
|
@ -28,14 +28,11 @@
|
|||
|
||||
/* ARM asynchronous clock */
|
||||
#define AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */
|
||||
#define AT91_MASTER_CLOCK 89999598 /* peripheral = main / 2 */
|
||||
#define CONFIG_SYS_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */
|
||||
#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
|
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/
|
||||
#define CONFIG_AFEB9260 1 /* on an AFEB9260 Board */
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
|
|
|
|||
|
|
@ -30,16 +30,12 @@
|
|||
/* ARM asynchronous clock */
|
||||
#define AT91_CPU_NAME "AT91CAP9"
|
||||
#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
|
||||
#define AT91_MASTER_CLOCK 100000000 /* peripheral */
|
||||
#define AT91_CPU_CLOCK 200000000 /* cpu */
|
||||
#define CONFIG_SYS_AT91_PLLB 0x10073e01 /* PLLB settings for USB */
|
||||
#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
|
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
|
||||
#define CONFIG_AT91CAP9 1 /* It's an Atmel AT91CAP9 SoC */
|
||||
#define CONFIG_AT91CAP9ADK 1 /* on an AT91CAP9ADK Board */
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
|
|
|
|||
|
|
@ -29,25 +29,19 @@
|
|||
|
||||
/* ARM asynchronous clock */
|
||||
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
|
||||
#define CONFIG_SYS_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */
|
||||
#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
|
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
|
||||
|
||||
#ifdef CONFIG_AT91SAM9G20EK
|
||||
#define AT91_CPU_NAME "AT91SAM9G20"
|
||||
#define AT91_MASTER_CLOCK 132000000 /* peripheral */
|
||||
#define AT91_CPU_CLOCK 396000000 /* cpu */
|
||||
#define CONFIG_AT91SAM9G20 1 /* It's an Atmel AT91SAM9G20 SoC*/
|
||||
#else
|
||||
#define AT91_CPU_NAME "AT91SAM9260"
|
||||
#define AT91_MASTER_CLOCK 100000000 /* peripheral */
|
||||
#define AT91_CPU_CLOCK 200000000 /* cpu */
|
||||
#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/
|
||||
#endif
|
||||
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
|
|
|
|||
|
|
@ -30,15 +30,12 @@
|
|||
/* ARM asynchronous clock */
|
||||
#define AT91_CPU_NAME "AT91SAM9261"
|
||||
#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
|
||||
#define AT91_MASTER_CLOCK 100000000 /* peripheral */
|
||||
#define AT91_CPU_CLOCK 200000000 /* cpu */
|
||||
#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
|
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
|
||||
#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/
|
||||
#define CONFIG_AT91SAM9261EK 1 /* on an AT91SAM9261EK Board */
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
|
|
|
|||
|
|
@ -30,16 +30,12 @@
|
|||
/* ARM asynchronous clock */
|
||||
#define AT91_CPU_NAME "AT91SAM9263"
|
||||
#define AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
|
||||
#define AT91_MASTER_CLOCK 100000000 /* peripheral */
|
||||
#define AT91_CPU_CLOCK 200000000 /* cpu */
|
||||
#define CONFIG_SYS_AT91_PLLB 0x133a3e8d /* PLLB settings for USB */
|
||||
#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
|
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
|
||||
#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/
|
||||
#define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
|
|
|
|||
|
|
@ -30,15 +30,12 @@
|
|||
/* ARM asynchronous clock */
|
||||
#define AT91_CPU_NAME "AT91SAM9RL"
|
||||
#define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */
|
||||
#define AT91_MASTER_CLOCK 100000000 /* peripheral */
|
||||
#define AT91_CPU_CLOCK 200000000 /* cpu */
|
||||
#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
|
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
|
||||
#define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/
|
||||
#define CONFIG_AT91SAM9RLEK 1 /* on an AT91SAM9RLEK Board */
|
||||
#define CONFIG_ARCH_CPU_INIT
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
|
|
|
|||
|
|
@ -262,6 +262,9 @@ int print_cpuinfo (void); /* test-only */
|
|||
|
||||
init_fnc_t *init_sequence[] = {
|
||||
cpu_init, /* basic cpu dependent setup */
|
||||
#if defined(CONFIG_ARCH_CPU_INIT)
|
||||
arch_cpu_init, /* basic arch cpu dependent setup */
|
||||
#endif
|
||||
board_init, /* basic board dependent setup */
|
||||
interrupt_init, /* set up exceptions */
|
||||
env_init, /* initialize environment */
|
||||
|
|
|
|||
Loading…
Reference in New Issue