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Fix style issues primarily in 85xx and 83xx boards. 

- C++ comments
    - Trailing white space
    - Indentation not by TAB
    - Excessive amount of empty lines
    - Trailing empty lines
This commit is contained in:
Jon Loeliger 2005-08-01 13:20:47 -05:00
parent b0e3294923
commit de1d0a6995
25 changed files with 544 additions and 567 deletions
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8
CHANGELOG
View File

@ -1,6 +1,14 @@
====================================================================== ======================================================================
Changes for U-Boot 1.1.3: Changes for U-Boot 1.1.3:
====================================================================== ======================================================================
* Patch by Jon Loeliger
Fix style issues primarily in 85xx and 83xx boards.
- C++ comments
- Trailing white space
- Indentation not by TAB
- Excessive amount of empty lines
- Trailing empty lines
* Patch by Ron Alder, 11 July 2005 * Patch by Ron Alder, 11 July 2005
Add Xianghua Xiao and Lunsheng Wang's support for the Add Xianghua Xiao and Lunsheng Wang's support for the
GDA MPC8540 EVAL board. GDA MPC8540 EVAL board.

28
board/mpc8349ads/mpc8349ads.c
View File

@ -53,7 +53,6 @@ int board_early_init_f (void)
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1) #define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
long int initdram (int board_type) long int initdram (int board_type)
{ {
volatile immap_t *im = (immap_t *)CFG_IMMRBAR; volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
@ -148,7 +147,7 @@ int checkboard (void)
return 0; return 0;
} }
#if defined(CONFIG_PCI) //copy from mpc85xx #if defined(CONFIG_PCI)
/* /*
* Initialize PCI Devices, report devices found * Initialize PCI Devices, report devices found
*/ */
@ -190,8 +189,8 @@ pci_init_board(void)
} }
/* /*
if MPC8349ADS is soldered with SDRAM * if MPC8349ADS is soldered with SDRAM
*/ */
#if defined(CFG_BR2_PRELIM) \ #if defined(CFG_BR2_PRELIM) \
&& defined(CFG_OR2_PRELIM) \ && defined(CFG_OR2_PRELIM) \
&& defined(CFG_LBLAWBAR2_PRELIM) \ && defined(CFG_LBLAWBAR2_PRELIM) \
@ -207,7 +206,6 @@ sdram_init(void)
volatile lbus8349_t *lbc= &immap->lbus; volatile lbus8349_t *lbc= &immap->lbus;
uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
puts("\n SDRAM on Local Bus: "); puts("\n SDRAM on Local Bus: ");
print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
@ -233,32 +231,33 @@ sdram_init(void)
lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/ lbc->lsdmr = CFG_LBC_LSDMR_2;/*0x48636733;auto refresh*/
asm("sync"); asm("sync");
/*1 times*/ /*1 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
/*2 times*/ /*2 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
/*3 times*/ /*3 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
/*4 times*/ /*4 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
/*5 times*/ /*5 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
/*6 times*/ /*6 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
/*7 times*/ /*7 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
/*8 times*/ /*8 times*/
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
lbc->lsdmr = CFG_LBC_LSDMR_4; /*0x58636733;mode register write operation*/ /* 0x58636733;mode register write operation */
lbc->lsdmr = CFG_LBC_LSDMR_4;
asm("sync"); asm("sync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
udelay(100); udelay(100);
@ -275,4 +274,3 @@ sdram_init(void)
put("SDRAM on Local Bus is NOT available!\n"); put("SDRAM on Local Bus is NOT available!\n");
} }
#endif #endif

40
board/mpc8540eval/mpc8540eval.c
View File

@ -23,34 +23,15 @@
* MA 02111-1307 USA * MA 02111-1307 USA
*/ */
extern long int spd_sdram (void);
#include <common.h> #include <common.h>
#include <asm/processor.h> #include <asm/processor.h>
#include <asm/immap_85xx.h> #include <asm/immap_85xx.h>
#include <spd.h> #include <spd.h>
extern long int spd_sdram (void);
long int fixed_sdram (void); long int fixed_sdram (void);
/* MPC8540ADS Board Status & Control Registers */
#if 0
typedef struct bscr_ {
unsigned long bcsr0;
unsigned long bcsr1;
unsigned long bcsr2;
unsigned long bcsr3;
unsigned long bcsr4;
unsigned long bcsr5;
unsigned long bcsr6;
unsigned long bcsr7;
} bcsr_t;
#endif
int board_pre_init (void) int board_pre_init (void)
{ {
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
@ -74,7 +55,8 @@ int checkboard (void)
printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000); printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \ if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
|| (CFG_LBC_LCRR & 0x0f) == 8) { || (CFG_LBC_LCRR & 0x0f) == 8) {
printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f)); printf ("\tLBC: %lu MHz\n",
sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f));
} else { } else {
printf("\tLBC: unknown\n"); printf("\tLBC: unknown\n");
} }
@ -199,7 +181,6 @@ long int initdram (int board_type)
return dram_size; return dram_size;
} }
#if defined(CFG_DRAM_TEST) #if defined(CFG_DRAM_TEST)
int testdram (void) int testdram (void)
{ {
@ -234,14 +215,13 @@ int testdram (void)
} }
#endif #endif
#if !defined(CONFIG_SPD_EEPROM) #if !defined(CONFIG_SPD_EEPROM)
/************************************************************************* /*************************************************************************
* fixed sdram init -- doesn't use serial presence detect. * fixed sdram init -- doesn't use serial presence detect.
************************************************************************/ ************************************************************************/
long int fixed_sdram (void) long int fixed_sdram (void)
{ {
#ifndef CFG_RAMBOOT #ifndef CFG_RAMBOOT
volatile immap_t *immap = (immap_t *)CFG_IMMR; volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile ccsr_ddr_t *ddr= &immap->im_ddr; volatile ccsr_ddr_t *ddr= &immap->im_ddr;
@ -251,21 +231,21 @@ long int fixed_sdram (void)
ddr->timing_cfg_2 = CFG_DDR_TIMING_2; ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
ddr->sdram_mode = CFG_DDR_MODE; ddr->sdram_mode = CFG_DDR_MODE;
ddr->sdram_interval = CFG_DDR_INTERVAL; ddr->sdram_interval = CFG_DDR_INTERVAL;
#if defined (CONFIG_DDR_ECC) #if defined (CONFIG_DDR_ECC)
ddr->err_disable = 0x0000000D; ddr->err_disable = 0x0000000D;
ddr->err_sbe = 0x00ff0000; ddr->err_sbe = 0x00ff0000;
#endif #endif
asm("sync;isync;msync"); asm("sync;isync;msync");
udelay(500); udelay(500);
#if defined (CONFIG_DDR_ECC) #if defined (CONFIG_DDR_ECC)
/* Enable ECC checking */ /* Enable ECC checking */
ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000); ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
#else #else
ddr->sdram_cfg = CFG_DDR_CONTROL; ddr->sdram_cfg = CFG_DDR_CONTROL;
#endif #endif
asm("sync; isync; msync"); asm("sync; isync; msync");
udelay(500); udelay(500);
#endif #endif
return (CFG_SDRAM_SIZE * 1024 * 1024); return (CFG_SDRAM_SIZE * 1024 * 1024);
} }
#endif /* !defined(CONFIG_SPD_EEPROM) */ #endif /* !defined(CONFIG_SPD_EEPROM) */

2
common/cmd_flash.c
View File

@ -101,7 +101,7 @@ abbrev_spec (char *str, flash_info_t ** pinfo, int *psf, int *psl)
* erase and protect commands. The range of the addresses on which * erase and protect commands. The range of the addresses on which
* either of the commands is to operate can be given in two forms: * either of the commands is to operate can be given in two forms:
* 1. <cmd> start end - operate on <'start', 'end') * 1. <cmd> start end - operate on <'start', 'end')
* 2. <cmd> start +length - operate on <'start', start + length) * 2. <cmd> start +length - operate on <'start', start + length)
* If the second form is used and the end address doesn't fall on the * If the second form is used and the end address doesn't fall on the
* sector boundary, than it will be adjusted to the next sector boundary. * sector boundary, than it will be adjusted to the next sector boundary.
* If it isn't in the flash, the function will fail (return -1). * If it isn't in the flash, the function will fail (return -1).

3
common/cmd_usb.c
View File

@ -455,9 +455,8 @@ int do_usb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
i = usb_init(); i = usb_init();
#ifdef CONFIG_USB_STORAGE #ifdef CONFIG_USB_STORAGE
/* try to recognize storage devices immediately */ /* try to recognize storage devices immediately */
if (i >= 0) if (i >= 0)
usb_stor_curr_dev = usb_stor_scan(1); usb_stor_curr_dev = usb_stor_scan(1);
#endif #endif
return 0; return 0;
} }

15
common/usb.c
View File

@ -47,7 +47,7 @@
#endif #endif
#undef USB_DEBUG #undef USB_DEBUG
#ifdef USB_DEBUG #ifdef USB_DEBUG
#define USB_PRINTF(fmt,args...) printf (fmt ,##args) #define USB_PRINTF(fmt,args...) printf (fmt ,##args)
@ -342,7 +342,7 @@ int usb_clear_halt(struct usb_device *dev, int pipe)
if (result < 0) if (result < 0)
return result; return result;
/* /*
* NOTE: we do not get status and verify reset was successful * NOTE: we do not get status and verify reset was successful
* as some devices are reported to lock up upon this check.. * as some devices are reported to lock up upon this check..
*/ */
@ -517,13 +517,12 @@ int usb_get_string(struct usb_device *dev, unsigned short langid, unsigned char
/* some devices are flaky */ /* some devices are flaky */
result = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), result = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
USB_REQ_GET_DESCRIPTOR, USB_DIR_IN, USB_REQ_GET_DESCRIPTOR, USB_DIR_IN,
(USB_DT_STRING << 8) + index, langid, buf, size, (USB_DT_STRING << 8) + index, langid, buf, size,
USB_CNTL_TIMEOUT); USB_CNTL_TIMEOUT);
if (result > 0) if (result > 0)
break; break;
} }
return result; return result;
} }
@ -572,7 +571,7 @@ static int usb_string_sub(struct usb_device *dev, unsigned int langid,
} }
if (rc < 2) if (rc < 2)
rc = -1; rc = -1;
return rc; return rc;
} }
@ -721,10 +720,9 @@ int usb_new_device(struct usb_device *dev)
} }
} }
dev->descriptor.bMaxPacketSize0 = desc->bMaxPacketSize0; dev->descriptor.bMaxPacketSize0 = desc->bMaxPacketSize0;
/* find the port number we're at */ /* find the port number we're at */
if (parent) { if (parent) {
for (j = 0; j < parent->maxchild; j++) { for (j = 0; j < parent->maxchild; j++) {
if (parent->children[j] == dev) { if (parent->children[j] == dev) {
port = j; port = j;
@ -958,7 +956,6 @@ static int hub_port_reset(struct usb_device *dev, int port,
return -1; return -1;
if (portstatus & USB_PORT_STAT_ENABLE) { if (portstatus & USB_PORT_STAT_ENABLE) {
break; break;
} }

10
common/usb_storage.c
View File

@ -229,7 +229,7 @@ int usb_stor_scan(int mode)
} }
if(usb_storage_probe(dev,0,&usb_stor[usb_max_devs])) { /* ok, it is a storage devices */ if(usb_storage_probe(dev,0,&usb_stor[usb_max_devs])) { /* ok, it is a storage devices */
/* get info and fill it in */ /* get info and fill it in */
if(usb_stor_get_info(dev, &usb_stor[usb_max_devs], &usb_dev_desc[usb_max_devs])) if(usb_stor_get_info(dev, &usb_stor[usb_max_devs], &usb_dev_desc[usb_max_devs]))
usb_max_devs++; usb_max_devs++;
} /* if storage device */ } /* if storage device */
if(usb_max_devs==USB_MAX_STOR_DEV) { if(usb_max_devs==USB_MAX_STOR_DEV) {
@ -237,7 +237,7 @@ int usb_stor_scan(int mode)
break; break;
} }
} /* for */ } /* for */
usb_disable_asynch(0); /* asynch transfer allowed */ usb_disable_asynch(0); /* asynch transfer allowed */
printf("%d Storage Device(s) found\n", usb_max_devs); printf("%d Storage Device(s) found\n", usb_max_devs);
if(usb_max_devs>0) if(usb_max_devs>0)
@ -656,7 +656,7 @@ int usb_stor_BBB_transport(ccb *srb, struct us_data *us)
retry = 0; retry = 0;
again: again:
USB_STOR_PRINTF("STATUS phase\n"); USB_STOR_PRINTF("STATUS phase\n");
result = usb_bulk_msg(us->pusb_dev, pipein, &csw, UMASS_BBB_CSW_SIZE, result = usb_bulk_msg(us->pusb_dev, pipein, &csw, UMASS_BBB_CSW_SIZE,
&actlen, USB_CNTL_TIMEOUT*5); &actlen, USB_CNTL_TIMEOUT*5);
/* special handling of STALL in STATUS phase */ /* special handling of STALL in STATUS phase */
@ -1134,7 +1134,7 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t
dev->descriptor.idProduct == 0x2010) dev->descriptor.idProduct == 0x2010)
) )
USB_STOR_PRINTF("usb_stor_get_info: skipping RESET..\n"); USB_STOR_PRINTF("usb_stor_get_info: skipping RESET..\n");
else else
ss->transport_reset(ss); ss->transport_reset(ss);
pccb->pdata = usb_stor_buf; pccb->pdata = usb_stor_buf;
@ -1145,7 +1145,7 @@ int usb_stor_get_info(struct usb_device *dev,struct us_data *ss,block_dev_desc_t
if(usb_inquiry(pccb,ss)) if(usb_inquiry(pccb,ss))
return -1; return -1;
perq = usb_stor_buf[0]; perq = usb_stor_buf[0];
modi = usb_stor_buf[1]; modi = usb_stor_buf[1];
if((perq & 0x1f) == 0x1f) { if((perq & 0x1f) == 0x1f) {

6
cpu/arm920t/s3c24x0/usb_ohci.c
View File

@ -53,7 +53,6 @@
#define OHCI_USE_NPS /* force NoPowerSwitching mode */ #define OHCI_USE_NPS /* force NoPowerSwitching mode */
#undef OHCI_VERBOSE_DEBUG /* not always helpful */ #undef OHCI_VERBOSE_DEBUG /* not always helpful */
/* For initializing controller (mask in an HCFS mode too) */ /* For initializing controller (mask in an HCFS mode too) */
#define OHCI_CONTROL_INIT \ #define OHCI_CONTROL_INIT \
(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
@ -1221,7 +1220,6 @@ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
} }
/*-------------------------------------------------------------------------*/ /*-------------------------------------------------------------------------*/
/* common code for handling submit messages - used for all but root hub */ /* common code for handling submit messages - used for all but root hub */
@ -1294,7 +1292,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
wait_ms(1); wait_ms(1);
if (!urb_finished) if (!urb_finished)
dbg("\%"); dbg("\%");
} else { } else {
err("CTL:TIMEOUT "); err("CTL:TIMEOUT ");
dbg("submit_common_msg: TO status %x\n", stat); dbg("submit_common_msg: TO status %x\n", stat);
@ -1511,7 +1509,7 @@ hc_interrupt (void)
ohci->disabled++; ohci->disabled++;
err ("%s device removed!", ohci->slot_name); err ("%s device removed!", ohci->slot_name);
return -1; return -1;
} else if ((ints &= readl (&regs->intrenable)) == 0) { } else if ((ints &= readl (&regs->intrenable)) == 0) {
dbg("hc_interrupt: returning..\n"); dbg("hc_interrupt: returning..\n");
return 0xff; return 0xff;

6
cpu/mpc5xxx/usb_ohci.c
View File

@ -1261,7 +1261,7 @@ int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
stat = USB_ST_CRC_ERR; stat = USB_ST_CRC_ERR;
break; break;
} }
/* NOTE: since we are not interrupt driven in U-Boot and always /* NOTE: since we are not interrupt driven in U-Boot and always
* handle only one URB at a time, we cannot assume the * handle only one URB at a time, we cannot assume the
* transaction finished on the first successful return from * transaction finished on the first successful return from
@ -1483,7 +1483,7 @@ hc_interrupt (void)
struct ohci_regs *regs = ohci->regs; struct ohci_regs *regs = ohci->regs;
int ints; int ints;
int stat = -1; int stat = -1;
if ((ohci->hcca->done_head != 0) && if ((ohci->hcca->done_head != 0) &&
!(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) { !(ohci_cpu_to_le32(ohci->hcca->done_head) & 0x01)) {
@ -1493,7 +1493,7 @@ hc_interrupt (void)
ohci->disabled++; ohci->disabled++;
err ("%s device removed!", ohci->slot_name); err ("%s device removed!", ohci->slot_name);
return -1; return -1;
} else if ((ints &= readl (&regs->intrenable)) == 0) { } else if ((ints &= readl (&regs->intrenable)) == 0) {
dbg("hc_interrupt: returning..\n"); dbg("hc_interrupt: returning..\n");
return 0xff; return 0xff;

1
cpu/mpc83xx/cpu_init.c
View File

@ -161,4 +161,3 @@ int cpu_init_r (void)
{ {
return 0; return 0;
} }

25
cpu/mpc83xx/pci.c
View File

@ -45,12 +45,12 @@ void
pci_mpc83xx_init(volatile struct pci_controller *hose) pci_mpc83xx_init(volatile struct pci_controller *hose)
{ {
volatile immap_t * immr; volatile immap_t * immr;
volatile clk8349_t * clk; volatile clk8349_t * clk;
volatile law8349_t * pci_law; volatile law8349_t * pci_law;
volatile pot8349_t * pci_pot; volatile pot8349_t * pci_pot;
volatile pcictrl8349_t * pci_ctrl; volatile pcictrl8349_t * pci_ctrl;
volatile pciconf8349_t * pci_conf; volatile pciconf8349_t * pci_conf;
u8 val8,tmp8,ret; u8 val8,tmp8,ret;
u16 reg16,tmp16; u16 reg16,tmp16;
u32 val32,tmp32; u32 val32,tmp32;
@ -69,7 +69,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
udelay(2000); udelay(2000);
clk->occr = 0xff000000; clk->occr = 0xff000000;
udelay(2000); udelay(2000);
/* /*
* Configure PCI Local Access Windows * Configure PCI Local Access Windows
*/ */
@ -89,7 +89,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
//#if defined(CONFIG_PCI_2)
pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK); pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK);
@ -98,8 +98,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
//#endif
/* /*
* Configure PCI Inbound Translation Windows * Configure PCI Inbound Translation Windows
*/ */
@ -131,13 +130,13 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
val8 = 0x34; val8 = 0x34;
ret = i2c_write(0x26,0x7,1,&val8,1); ret = i2c_write(0x26,0x7,1,&val8,1);
#if defined(PCI_64BIT) #if defined(PCI_64BIT)
val8 = 0xf4; // PMC2<->PCI1 64bit val8 = 0xf4; /* PMC2<->PCI1 64bit */
#elif defined(PCI_ALL_PCI1) #elif defined(PCI_ALL_PCI1)
val8 = 0xf3; // PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit val8 = 0xf3; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit */
#elif defined(PCI_ONE_PCI1) #elif defined(PCI_ONE_PCI1)
val8 = 0xf9; // PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit val8 = 0xf9; /* PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit */
#elif defined(PCI_TWO_PCI1) #elif defined(PCI_TWO_PCI1)
val8 = 0xf5; // PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit val8 = 0xf5; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit */
#else #else
val8 = 0xf5; val8 = 0xf5;
#endif #endif
@ -160,7 +159,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
pci_ctrl[0].gcr = 1; pci_ctrl[0].gcr = 1;
#ifndef PCI_64BIT #ifndef PCI_64BIT
pci_ctrl[1].gcr = 1; pci_ctrl[1].gcr = 1;
#endif #endif
udelay(2000); udelay(2000);
hose[0].first_busno = 0; hose[0].first_busno = 0;
@ -186,7 +185,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
#define PCI_CLASS_BRIDGE 0x06 #define PCI_CLASS_BRIDGE 0x06
reg16 = 0xff; reg16 = 0xff;
tmp32 = 0xffff; tmp32 = 0xffff;
pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE); pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, &reg16); pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
@ -219,7 +218,7 @@ pci_mpc83xx_init(volatile struct pci_controller *hose)
(CFG_IMMRBAR+0x8380), (CFG_IMMRBAR+0x8380),
(CFG_IMMRBAR+0x8384)); (CFG_IMMRBAR+0x8384));
pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE); pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE);
pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, &reg16); pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, &reg16);
reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16); pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16);

2
cpu/mpc83xx/resetvec.S
View File

@ -2,5 +2,5 @@
#ifndef FIXME #ifndef FIXME
#if 0 #if 0
b _start_e500 b _start_e500
#endif #endif
#endif #endif

25
cpu/mpc83xx/spd_sdram.c
View File

@ -36,20 +36,16 @@
#ifdef CONFIG_SPD_EEPROM #ifdef CONFIG_SPD_EEPROM
#if defined(CONFIG_DDR_ECC) #if defined(CONFIG_DDR_ECC)
extern void dma_init(void); extern void dma_init(void);
extern uint dma_check(void); extern uint dma_check(void);
extern int dma_xfer(void *dest, uint count, void *src); extern int dma_xfer(void *dest, uint count, void *src);
#endif #endif
#ifndef CFG_READ_SPD #ifndef CFG_READ_SPD
#define CFG_READ_SPD i2c_read #define CFG_READ_SPD i2c_read
#endif #endif
/* /*
* Convert picoseconds into clock cycles (rounding up if needed). * Convert picoseconds into clock cycles (rounding up if needed).
*/ */
@ -67,14 +63,12 @@ picos_to_clk(int picos)
return clks; return clks;
} }
unsigned int unsigned int
banksize(unsigned char row_dens) banksize(unsigned char row_dens)
{ {
return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24; return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
} }
long int spd_sdram(int(read_spd)(uint addr)) long int spd_sdram(int(read_spd)(uint addr))
{ {
volatile immap_t *immap = (immap_t *)CFG_IMMRBAR; volatile immap_t *immap = (immap_t *)CFG_IMMRBAR;
@ -86,8 +80,8 @@ long int spd_sdram(int(read_spd)(uint addr))
unsigned int law_size; unsigned int law_size;
unsigned char caslat; unsigned char caslat;
unsigned int trfc, trfc_clk, trfc_low; unsigned int trfc, trfc_clk, trfc_low;
#warning Current spd_sdram does not fit its usage... adjust implementation or API... #warning Current spd_sdram does not fit its usage... adjust implementation or API...
CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
@ -111,7 +105,7 @@ long int spd_sdram(int(read_spd)(uint addr))
debug("\n"); debug("\n");
debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds); debug("cs2_bnds = 0x%08x\n",ddr->csbnds[2].csbnds);
debug("cs2_config = 0x%08x\n",ddr->cs_config[2]); debug("cs2_config = 0x%08x\n",ddr->cs_config[2]);
if (spd.nrows == 2) { if (spd.nrows == 2) {
ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8) ddr->csbnds[3].csbnds = ( (banksize(spd.row_dens) >> 8)
| ((banksize(spd.row_dens) >> 23) - 1) ); | ((banksize(spd.row_dens) >> 23) - 1) );
@ -298,9 +292,12 @@ long int spd_sdram(int(read_spd)(uint addr))
udelay(500); udelay(500);
/*
ddr->sdram_clk_cntl = 0x82000000;/*SS_EN=1, CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM clock cycle after address/command*/ * SS_EN=1,
* CLK_ADJST = 2-MCK/MCK_B, is lauched 1/2 of one SDRAM
* clock cycle after address/command
*/
ddr->sdram_clk_cntl = 0x82000000;
/* /*
* Figure out the settings for the sdram_cfg register. Build up * Figure out the settings for the sdram_cfg register. Build up
@ -339,7 +336,6 @@ long int spd_sdram(int(read_spd)(uint addr))
#endif #endif
ddr->sdram_cfg = tmp; ddr->sdram_cfg = tmp;
asm("sync;isync"); asm("sync;isync");
udelay(500); udelay(500);
@ -347,7 +343,6 @@ long int spd_sdram(int(read_spd)(uint addr))
return memsize;/*in MBytes*/ return memsize;/*in MBytes*/
} }
#endif /* CONFIG_SPD_EEPROM */ #endif /* CONFIG_SPD_EEPROM */
@ -407,7 +402,7 @@ ddr_enable_ecc(unsigned int dram_size)
*/ */
ddr->err_disable = 0x00000000; ddr->err_disable = 0x00000000;
asm("sync;isync"); asm("sync;isync");
#endif #endif
} }
#endif /* CONFIG_DDR_ECC */ #endif /* CONFIG_DDR_ECC */

39
cpu/mpc83xx/speed.c
View File

@ -101,7 +101,7 @@ int get_clocks (void)
u32 corecnf_tab_index; u32 corecnf_tab_index;
u8 corepll; u8 corepll;
u32 lcrr; u32 lcrr;
u32 csb_clk; u32 csb_clk;
u32 tsec1_clk; u32 tsec1_clk;
u32 tsec2_clk; u32 tsec2_clk;
@ -113,10 +113,10 @@ int get_clocks (void)
u32 lbiu_clk; u32 lbiu_clk;
u32 lclk_clk; u32 lclk_clk;
u32 ddr_clk; u32 ddr_clk;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1; return -1;
#ifndef CFG_HRCW_HIGH #ifndef CFG_HRCW_HIGH
# error "CFG_HRCW_HIGH must be defined in include/configs/MCP83XXADS.h" # error "CFG_HRCW_HIGH must be defined in include/configs/MCP83XXADS.h"
#endif /* CFG_HCWD_HIGH */ #endif /* CFG_HCWD_HIGH */
@ -133,7 +133,6 @@ int get_clocks (void)
/* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */ /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH the im->reset.rcwhr PCI Host Mode is disabled */
/* FIXME: findout if there is a way to issue some warning */ /* FIXME: findout if there is a way to issue some warning */
return -2; return -2;
} }
if (im->clk.spmr & SPMR_CKID) { if (im->clk.spmr & SPMR_CKID) {
pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */ pci_sync_in = CONFIG_83XX_CLKIN / 2; /* PCI Clock is half CONFIG_83XX_CLKIN */
@ -157,17 +156,16 @@ int get_clocks (void)
#endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */ #endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
/* we have up to date pci_sync_in */ /* we have up to date pci_sync_in */
spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT); spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT); clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) { if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) {
csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2; csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2;
} }
else { else {
csb_clk = pci_sync_in * spmf * (1 + clkin_div); csb_clk = pci_sync_in * spmf * (1 + clkin_div);
} }
sccr = im->clk.sccr; sccr = im->clk.sccr;
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) { switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0: case 0:
@ -186,7 +184,7 @@ int get_clocks (void)
/* unkown SCCR_TSEC1CM value */ /* unkown SCCR_TSEC1CM value */
return -4; return -4;
} }
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) { switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0: case 0:
tsec2_clk = 0; tsec2_clk = 0;
@ -205,7 +203,7 @@ int get_clocks (void)
return -5; return -5;
} }
i2c_clk = tsec2_clk; i2c_clk = tsec2_clk;
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) { switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0: case 0:
enc_clk = 0; enc_clk = 0;
@ -223,7 +221,7 @@ int get_clocks (void)
/* unkown SCCR_ENCCM value */ /* unkown SCCR_ENCCM value */
return -6; return -6;
} }
switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) { switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
case 0: case 0:
usbmph_clk = 0; usbmph_clk = 0;
@ -259,14 +257,14 @@ int get_clocks (void)
/* unkown SCCR_USBDRCM value */ /* unkown SCCR_USBDRCM value */
return -8; return -8;
} }
if (usbmph_clk != 0 if (usbmph_clk != 0
&& usbdr_clk != 0 && usbdr_clk != 0
&& usbmph_clk != usbdr_clk ) { && usbmph_clk != usbdr_clk ) {
/* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */ /* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */
return -9; return -9;
} }
lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT)); lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT; lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
switch (lcrr) { switch (lcrr) {
@ -279,9 +277,9 @@ int get_clocks (void)
/* unknown lcrr */ /* unknown lcrr */
return -10; return -10;
} }
ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT)); ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT; corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5); corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) { if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) {
@ -310,7 +308,7 @@ int get_clocks (void)
/* unkown core to csb ratio */ /* unkown core to csb ratio */
return -12; return -12;
} }
gd->csb_clk = csb_clk ; gd->csb_clk = csb_clk ;
gd->tsec1_clk = tsec1_clk ; gd->tsec1_clk = tsec1_clk ;
gd->tsec2_clk = tsec2_clk ; gd->tsec2_clk = tsec2_clk ;
@ -318,11 +316,11 @@ int get_clocks (void)
gd->usbmph_clk = usbmph_clk; gd->usbmph_clk = usbmph_clk;
gd->usbdr_clk = usbdr_clk ; gd->usbdr_clk = usbdr_clk ;
gd->i2c_clk = i2c_clk ; gd->i2c_clk = i2c_clk ;
gd->enc_clk = enc_clk ; gd->enc_clk = enc_clk ;
gd->lbiu_clk = lbiu_clk ; gd->lbiu_clk = lbiu_clk ;
gd->lclk_clk = lclk_clk ; gd->lclk_clk = lclk_clk ;
gd->ddr_clk = ddr_clk ; gd->ddr_clk = ddr_clk ;
gd->cpu_clk = gd->core_clk; gd->cpu_clk = gd->core_clk;
gd->bus_clk = gd->lbiu_clk; gd->bus_clk = gd->lbiu_clk;
return 0; return 0;
@ -341,7 +339,7 @@ ulong get_bus_freq (ulong dummy)
int print_clock_conf (void) int print_clock_conf (void)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
printf("Clock configuration:\n"); printf("Clock configuration:\n");
printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000); printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
printf(" Core: %4d MHz\n",gd->core_clk/1000000); printf(" Core: %4d MHz\n",gd->core_clk/1000000);
@ -353,7 +351,7 @@ int print_clock_conf (void)
printf(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000); printf(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
printf(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000); printf(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
printf(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000); printf(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);
#if 0 #if 0
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -419,6 +417,5 @@ int print_clock_conf (void)
} }
putc ('\n'); putc ('\n');
#endif #endif
return (0); return 0;
} }

79
cpu/mpc83xx/start.S
View File

@ -28,7 +28,7 @@
*/ */
#include <config.h> #include <config.h>
#include <mpc83xx.h> #include <mpc83xx.h>
#include <version.h> #include <version.h>
#define CONFIG_83XX 1 /* needed for Linux kernel header files*/ #define CONFIG_83XX 1 /* needed for Linux kernel header files*/
@ -89,7 +89,7 @@ version_string:
.ascii U_BOOT_VERSION .ascii U_BOOT_VERSION
.ascii " (", __DATE__, " - ", __TIME__, ")" .ascii " (", __DATE__, " - ", __TIME__, ")"
.ascii " ", CONFIG_IDENT_STRING, "\0" .ascii " ", CONFIG_IDENT_STRING, "\0"
.text .text
#define _HRCW_TABLE_ENTRY(w) \ #define _HRCW_TABLE_ENTRY(w) \
.fill 8,1,(((w)>>24)&0xff); \ .fill 8,1,(((w)>>24)&0xff); \
@ -101,7 +101,6 @@ version_string:
_HRCW_TABLE_ENTRY(CFG_HRCW_HIGH) _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
#ifndef CONFIG_DEFAULT_IMMR #ifndef CONFIG_DEFAULT_IMMR
#error CONFIG_DEFAULT_IMMR must be defined #error CONFIG_DEFAULT_IMMR must be defined
#endif /* CFG_DEFAULT_IMMR */ #endif /* CFG_DEFAULT_IMMR */
@ -143,7 +142,7 @@ _start: /* time t 0 */
. = EXC_OFF_SYS_RESET + 0x10 . = EXC_OFF_SYS_RESET + 0x10
.globl _start_warm .globl _start_warm
_start_warm: _start_warm:
li r21, BOOTFLAG_WARM /* Software reboot */ li r21, BOOTFLAG_WARM /* Software reboot */
b boot_warm b boot_warm
@ -156,12 +155,12 @@ boot_warm: /* time t 5 */
lis r3, CFG_IMMRBAR@h lis r3, CFG_IMMRBAR@h
ori r3, r3, CFG_IMMRBAR@l ori r3, r3, CFG_IMMRBAR@l
stw r3, IMMRBAR(r4) stw r3, IMMRBAR(r4)
/* Initialise the E300 processor core */ /* Initialise the E300 processor core */
/*------------------------------------------*/ /*------------------------------------------*/
bl init_e300_core bl init_e300_core
#ifndef CFG_RAMBOOT #ifndef CFG_RAMBOOT
/* Inflate flash location so it appears everywhere, calculate */ /* Inflate flash location so it appears everywhere, calculate */
@ -218,7 +217,7 @@ _start_of_vectors:
/* External Interrupt exception. */ /* External Interrupt exception. */
#ifndef FIXME #ifndef FIXME
STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
#endif #endif
/* Alignment exception. */ /* Alignment exception. */
. = 0x600 . = 0x600
@ -417,9 +416,9 @@ init_e300_core: /* time t 10 */
lis r4, CFG_WATCHDOG_VALUE lis r4, CFG_WATCHDOG_VALUE
ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
stw r4, SWCRR(r3) stw r4, SWCRR(r3)
/* and reset it */ /* and reset it */
li r4, 0x556C li r4, 0x556C
sth r4, SWSRR@l(r3) sth r4, SWSRR@l(r3)
li r4, 0xAA39 li r4, 0xAA39
@ -502,7 +501,7 @@ init_e300_core: /* time t 10 */
/* Done! */ /* Done! */
/*------------------------------*/ /*------------------------------*/
blr blr
/* Cache functions. /* Cache functions.
* *
@ -645,8 +644,8 @@ relocate_code:
mtctr r0 mtctr r0
la r8,-4(r4) la r8,-4(r4)
la r7,-4(r3) la r7,-4(r3)
/* and compare */ /* and compare */
20: lwzu r20,4(r8) 20: lwzu r20,4(r8)
lwzu r21,4(r7) lwzu r21,4(r7)
xor. r22, r20, r21 xor. r22, r20, r21
@ -664,21 +663,19 @@ relocate_code:
3: lwzu r0,-4(r8) 3: lwzu r0,-4(r8)
stwu r0,-4(r7) stwu r0,-4(r7)
bdnz 3b bdnz 3b
/* /*
* Now flush the cache: note that we must start from a cache aligned * Now flush the cache: note that we must start from a cache aligned
* address. Otherwise we might miss one cache line. * address. Otherwise we might miss one cache line.
*/ */
4: 4:
bl un_setup_stack_in_data_cache bl un_setup_stack_in_data_cache
mr r7, r3 mr r7, r3
mr r8, r4 mr r8, r4
bl dcache_disable bl dcache_disable
mr r3, r7 mr r3, r7
mr r4, r8 mr r4, r8
cmpwi r6,0 cmpwi r6,0
add r5,r3,r5 add r5,r3,r5
beq 7f /* Always flush prefetch queue in any case */ beq 7f /* Always flush prefetch queue in any case */
@ -889,9 +886,9 @@ map_flash_by_law1:
/* Address Mask in OR0 so ROM appears everywhere */ /* Address Mask in OR0 so ROM appears everywhere */
/*----------------------------------------------------*/ /*----------------------------------------------------*/
lis r3, (CFG_IMMRBAR)@h /* r3 <= CFG_IMMRBAR */ lis r3, (CFG_IMMRBAR)@h /* r3 <= CFG_IMMRBAR */
lwz r4, OR0@l(r3) lwz r4, OR0@l(r3)
li r5, 0x7fff /* r5 <= 0x00007FFFF */ li r5, 0x7fff /* r5 <= 0x00007FFFF */
and r4, r4, r5 and r4, r4, r5
stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */ stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
/* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0, /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
@ -926,9 +923,9 @@ remap_flash_by_law0:
/* Initialize the BR0 with the boot ROM starting address. */ /* Initialize the BR0 with the boot ROM starting address. */
lwz r4, BR0(r3) lwz r4, BR0(r3)
li r5, 0x7FFF li r5, 0x7FFF
and r4, r4, r5 and r4, r4, r5
lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h
ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l
or r5, r5, r4 or r5, r5, r4
stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */ stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
@ -950,9 +947,9 @@ remap_flash_by_law0:
stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */ stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
blr blr
setup_stack_in_data_cache_on_r1: setup_stack_in_data_cache_on_r1:
lis r3, (CFG_IMMRBAR)@h lis r3, (CFG_IMMRBAR)@h
/* setup D-BAT for the D-Cache (with out real memory backup) */ /* setup D-BAT for the D-Cache (with out real memory backup) */
lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
@ -961,13 +958,13 @@ setup_stack_in_data_cache_on_r1:
mtspr DBAT0L, r4 mtspr DBAT0L, r4
isync isync
#if 0 #if 0
/* Enable MMU */ /* Enable MMU */
mfmsr r4 mfmsr r4
ori r4, r4, (MSR_DR | MSR_IR)@l ori r4, r4, (MSR_DR | MSR_IR)@l
mtmsr r4 mtmsr r4
#endif #endif
/* Enable and invalidate data cache. */ /* Enable and invalidate data cache. */
mfspr r4, HID0 mfspr r4, HID0
mr r5, r4 mr r5, r4
@ -977,19 +974,19 @@ setup_stack_in_data_cache_on_r1:
mtspr HID0, r4 mtspr HID0, r4
mtspr HID0, r5 mtspr HID0, r5
sync sync
/* Allocate Initial RAM in data cache.*/ /* Allocate Initial RAM in data cache.*/
li r0, 0 li r0, 0
lis r4, (CFG_INIT_RAM_ADDR)@h lis r4, (CFG_INIT_RAM_ADDR)@h
ori r4, r4, (CFG_INIT_RAM_ADDR)@l ori r4, r4, (CFG_INIT_RAM_ADDR)@l
li r5, 128*8 /* 128*8*32=32Kb */ li r5, 128*8 /* 128*8*32=32Kb */
mtctr r5 mtctr r5
1: 1:
dcbz r0, r4 dcbz r0, r4
addi r4, r4, 32 addi r4, r4, 32
bdnz 1b bdnz 1b
isync isync
/* Lock all the D-cache, basically leaving the reset of the program without dcache */ /* Lock all the D-cache, basically leaving the reset of the program without dcache */
mfspr r4, HID0 mfspr r4, HID0
ori r4, r4, (HID0_DLOCK)@l ori r4, r4, (HID0_DLOCK)@l
@ -1010,14 +1007,14 @@ un_setup_stack_in_data_cache:
blr blr
mr r14, r4 mr r14, r4
mr r15, r5 mr r15, r5
lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h lis r4, (CFG_INIT_RAM_ADDR & 0xFFFE0000)@h
mtspr DBAT0U, r4 mtspr DBAT0U, r4
ori r4, r4, 0x0002 ori r4, r4, 0x0002
mtspr DBAT0L, r4 mtspr DBAT0L, r4
isync isync
/* un lock all the D-cache */ /* un lock all the D-cache */
mfspr r4, HID0 mfspr r4, HID0
lis r5, (~(HID0_DLOCK))@h lis r5, (~(HID0_DLOCK))@h
@ -1030,20 +1027,20 @@ un_setup_stack_in_data_cache:
li r0, 0 li r0, 0
lis r4, (CFG_INIT_RAM_ADDR)@h lis r4, (CFG_INIT_RAM_ADDR)@h
ori r4, r4, (CFG_INIT_RAM_ADDR)@l ori r4, r4, (CFG_INIT_RAM_ADDR)@l
li r5, 128*8 /* 128*8*32=32Kb */ li r5, 128*8 /* 128*8*32=32Kb */
mtctr r5 mtctr r5
1: 1:
dcbz r0, r4 dcbz r0, r4
addi r4, r4, 32 addi r4, r4, 32
bdnz 1b bdnz 1b
isync isync
mflr r16 mflr r16
bl dcache_disable bl dcache_disable
mtlr r16 mtlr r16
blr blr
#if 0 #if 0
#define GREEN_LIGHT 0x2B0D4046 #define GREEN_LIGHT 0x2B0D4046
#define RED_LIGHT 0x250D4046 #define RED_LIGHT 0x250D4046
@ -1054,7 +1051,7 @@ un_setup_stack_in_data_cache:
*/ */
.globl liblight .globl liblight
liblight: liblight:
lis r3, CFG_IMMRBAR@h lis r3, CFG_IMMRBAR@h
ori r3, r3, CFG_IMMRBAR@l ori r3, r3, CFG_IMMRBAR@l
li r4, 0x3002 li r4, 0x3002
@ -1063,7 +1060,7 @@ liblight:
mtspr HID0, r4 mtspr HID0, r4
mtspr HID2, r4 mtspr HID2, r4
lis r4, 0xF8000000@h lis r4, 0xF8000000@h
ori r4, r4, 0xF8000000@l ori r4, r4, 0xF8000000@l
stw r4, LBLAWBAR1(r3) stw r4, LBLAWBAR1(r3)
lis r4, 0x8000000E@h lis r4, 0x8000000E@h
ori r4, r4, 0x8000000E@l ori r4, r4, 0x8000000E@l
@ -1083,14 +1080,14 @@ liblight:
ori r6, r6, RED_LIGHT@l ori r6, r6, RED_LIGHT@l
lis r7, LIB_CNT@h lis r7, LIB_CNT@h
ori r7, r7, LIB_CNT@l ori r7, r7, LIB_CNT@l
1: 1:
stw r5, 0(r4) stw r5, 0(r4)
mtctr r7 mtctr r7
2: bdnz 2b 2: bdnz 2b
stw r6, 0(r4) stw r6, 0(r4)
mtctr r7 mtctr r7
3: bdnz 3b 3: bdnz 3b
b 1b b 1b
#endif #endif

4
cpu/mpc85xx/spd_sdram.c
View File

@ -630,7 +630,7 @@ spd_sdram(void)
ddr->timing_cfg_2 = (0 ddr->timing_cfg_2 = (0
| ((add_lat & 0x7) << 28) /* ADD_LAT */ | ((add_lat & 0x7) << 28) /* ADD_LAT */
| ((cpo & 0x1f) << 23) /* CPO */ | ((cpo & 0x1f) << 23) /* CPO */
| ((wr_lat & 0x7) << 19) /* WR_LAT */ | ((wr_lat & 0x7) << 19) /* WR_LAT */
| ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */ | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
| ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */ | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
@ -822,7 +822,7 @@ spd_sdram(void)
/* /*
* Memory will be initialized via DMA, or not at all. * Memory will be initialized via DMA, or not at all.
*/ */
d_init = 0; d_init = 0;
#endif #endif
ddr->sdram_cfg_2 = (0 ddr->sdram_cfg_2 = (0

10
drivers/tsec.c
View File

@ -524,11 +524,11 @@ static void adjust_link(struct eth_device *dev)
regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF)) regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
| MACCFG2_MII); | MACCFG2_MII);
/* If We're in reduced mode, we /* If We're in reduced mode, we need
* need to say whether we're 10 * to say whether we're 10 or 100 MB.
* or 100 MB. */ */
if ((priv->speed == 100) if ((priv->speed == 100)
&& (priv->flags & TSEC_REDUCED)) && (priv->flags & TSEC_REDUCED))
regs->ecntrl |= ECNTRL_R100; regs->ecntrl |= ECNTRL_R100;
else else
regs->ecntrl &= ~(ECNTRL_R100); regs->ecntrl &= ~(ECNTRL_R100);

4
include/asm-ppc/e300.h
View File

@ -7,7 +7,7 @@
#define __E300_H__ #define __E300_H__
/* /*
* e300 Processor Version & Revision Numbers * e300 Processor Version & Revision Numbers
*/ */
#define PVR_83xx 0x80830000 #define PVR_83xx 0x80830000
#define PVR_8349_REV10 (PVR_83xx | 0x0010) #define PVR_8349_REV10 (PVR_83xx | 0x0010)
@ -16,7 +16,7 @@
/* /*
* Hardware Implementation-Dependent Register 0 (HID0) * Hardware Implementation-Dependent Register 0 (HID0)
*/ */
/* #define HID0 1008 already defined in processor.h */ /* #define HID0 1008 already defined in processor.h */
#define HID0_MASK_MACHINE_CHECK 0x00000000 #define HID0_MASK_MACHINE_CHECK 0x00000000
#define HID0_ENABLE_MACHINE_CHECK 0x80000000 #define HID0_ENABLE_MACHINE_CHECK 0x80000000

17
include/asm-ppc/i2c.h
View File

@ -36,13 +36,12 @@ typedef struct i2c
#define I2C_ADR 0xFE #define I2C_ADR 0xFE
#define I2C_ADR_SHIFT 1 #define I2C_ADR_SHIFT 1
#define I2C_ADR_RES ~(I2C_ADR) #define I2C_ADR_RES ~(I2C_ADR)
u8 res0[3]; u8 res0[3];
u8 fdr; /**< I2C frequency divider register */ u8 fdr; /**< I2C frequency divider register */
#define IC2_FDR 0x3F #define IC2_FDR 0x3F
#define IC2_FDR_SHIFT 0 #define IC2_FDR_SHIFT 0
#define IC2_FDR_RES ~(IC2_FDR) #define IC2_FDR_RES ~(IC2_FDR)
u8 res1[3]; u8 res1[3];
u8 cr; /**< I2C control redister */ u8 cr; /**< I2C control redister */
#define I2C_CR_MEN 0x80 #define I2C_CR_MEN 0x80
#define I2C_CR_MIEN 0x40 #define I2C_CR_MIEN 0x40
@ -51,7 +50,7 @@ typedef struct i2c
#define I2C_CR_TXAK 0x08 #define I2C_CR_TXAK 0x08
#define I2C_CR_RSTA 0x04 #define I2C_CR_RSTA 0x04
#define I2C_CR_BCST 0x01 #define I2C_CR_BCST 0x01
u8 res2[3]; u8 res2[3];
u8 sr; /**< I2C status register */ u8 sr; /**< I2C status register */
#define I2C_SR_MCF 0x80 #define I2C_SR_MCF 0x80
#define I2C_SR_MAAS 0x40 #define I2C_SR_MAAS 0x40
@ -61,18 +60,18 @@ typedef struct i2c
#define I2C_SR_SRW 0x04 #define I2C_SR_SRW 0x04
#define I2C_SR_MIF 0x02 #define I2C_SR_MIF 0x02
#define I2C_SR_RXAK 0x01 #define I2C_SR_RXAK 0x01
u8 res3[3]; u8 res3[3];
u8 dr; /**< I2C data register */ u8 dr; /**< I2C data register */
#define I2C_DR 0xFF #define I2C_DR 0xFF
#define I2C_DR_SHIFT 0 #define I2C_DR_SHIFT 0
#define I2C_DR_RES ~(I2C_DR) #define I2C_DR_RES ~(I2C_DR)
u8 res4[3]; u8 res4[3];
u8 dfsrr; /**< I2C digital filter sampling rate register */ u8 dfsrr; /**< I2C digital filter sampling rate register */
#define I2C_DFSRR 0x3F #define I2C_DFSRR 0x3F
#define I2C_DFSRR_SHIFT 0 #define I2C_DFSRR_SHIFT 0
#define I2C_DFSRR_RES ~(I2C_DR) #define I2C_DFSRR_RES ~(I2C_DR)
u8 res5[3]; u8 res5[3];
u8 res6[0xE8]; u8 res6[0xE8];
} i2c_t; } i2c_t;
#ifndef CFG_HZ #ifndef CFG_HZ
@ -89,8 +88,8 @@ typedef struct i2c
#endif #endif
#ifdef CONFIG_MPC8349ADS #ifdef CONFIG_MPC8349ADS
/* /*
* MPC8349 have two i2c bus * MPC8349 have two i2c bus
*/ */
extern i2c_t * mpc8349_i2c; extern i2c_t * mpc8349_i2c;
#define I2C mpc8349_i2c #define I2C mpc8349_i2c

484
include/asm-ppc/immap_83xx.h
View File

@ -2,7 +2,7 @@
* MPC8349 Internal Memory Map * MPC8349 Internal Memory Map
* Copyright (c) 2004 Freescale Semiconductor. * Copyright (c) 2004 Freescale Semiconductor.
* Eran Liberty (liberty@freescale.com) * Eran Liberty (liberty@freescale.com)
* *
* based on: * based on:
* - MPC8260 Internal Memory Map * - MPC8260 Internal Memory Map
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net) * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
@ -16,20 +16,32 @@
#include <asm/types.h> #include <asm/types.h>
#include <asm/i2c.h> #include <asm/i2c.h>
/* /*
* Local Access Window. * Local Access Window.
*/ */
typedef struct law8349 { typedef struct law8349 {
u32 bar; /* LBIU local access window base address register */ u32 bar; /* LBIU local access window base address register */
#define LAWBAR_BAR 0xFFFFF000 /* Identifies the 20 most-significant address bits of the base of local access window n. The specified base address should be aligned to the window size, as defined by LBLAWARn[SIZE]. */ /* Identifies the 20 most-significant address bits of the base of local
* access window n. The specified base address should be aligned to the
* window size, as defined by LBLAWARn[SIZE].
*/
#define LAWBAR_BAR 0xFFFFF000
#define LAWBAR_RES ~(LAWBAR_BAR) #define LAWBAR_RES ~(LAWBAR_BAR)
u32 ar; /* LBIU local access window attribute register */ u32 ar; /* LBIU local access window attribute register */
/* /*
* This Macro were moved into mmu.h * This Macro were moved into mmu.h
*/ */
#if 0 #if 0
#define LAWAR_EN 0x80000000 /* 0 The local bus local access window n is disabled. 1 The local bus local access window n is enabled and other LBLAWAR0 and LBLAWBAR0 fields combine to identify an address range for this window. */ /* 0 The local bus local access window n is disabled. 1 The local bus
#define LAWAR_SIZE 0x0000003F /* Identifies the size of the window from the starting address. Window size is 2^(SIZE+1) bytes. 000000–001010Reserved. Window is undefined. */ * local access window n is enabled and other LBLAWAR0 and LBLAWBAR0 fields
* combine to identify an address range for this window.
*/
#define LAWAR_EN 0x80000000
/* Identifies the size of the window from the starting address. Window
* size is 2^(SIZE+1) bytes. 000000–001010Reserved. Window is
* undefined.
*/
#define LAWAR_SIZE 0x0000003F
#define LAWAR_SIZE_4K 0x0000000B #define LAWAR_SIZE_4K 0x0000000B
#define LAWAR_SIZE_8K 0x0000000C #define LAWAR_SIZE_8K 0x0000000C
#define LAWAR_SIZE_16K 0x0000000D #define LAWAR_SIZE_16K 0x0000000D
@ -55,14 +67,17 @@ typedef struct law8349 {
} law8349_t; } law8349_t;
/* /*
* System configuration registers. * System configuration registers.
*/ */
typedef struct sysconf8349 { typedef struct sysconf8349 {
u32 immrbar; /* Internal memory map base address register */ u32 immrbar; /* Internal memory map base address register */
u8 res0[0x04]; u8 res0[0x04];
u32 altcbar; /* Alternate configuration base address register */ u32 altcbar; /* Alternate configuration base address register */
#define ALTCBAR_BASE_ADDR 0xFFF00000 /* Identifies the12 most significant address bits of an alternate base address used for boot sequencer configuration accesses. */ /* Identifies the12 most significant address bits of an alternate base
* address used for boot sequencer configuration accesses.
*/
#define ALTCBAR_BASE_ADDR 0xFFF00000
#define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */ #define ALTCBAR_RES ~(ALTCBAR_BASE_ADDR) /* Reserved. Write has no effect, read returns 0. */
u8 res1[0x14]; u8 res1[0x14];
law8349_t lblaw[4]; /* LBIU local access window */ law8349_t lblaw[4]; /* LBIU local access window */
@ -77,7 +92,7 @@ typedef struct sysconf8349 {
#define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */ #define SPRIDR_PARTID 0xFFFF0000 /* Part Identification. */
#define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */ #define SPRIDR_REVID 0x0000FFFF /* Revision Identification. */
u8 res5[0x04]; u8 res5[0x04];
u32 spcr; /* System Priority Configuration Register */ u32 spcr; /* System Priority Configuration Register */
#define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */ #define SPCR_PCIHPE 0x10000000 /* PCI Highest Priority Enable. */
#define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */ #define SPCR_PCIPR 0x03000000 /* PCI bridge system bus request priority. */
#define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */ #define SPCR_TBEN 0x00400000 /* E300 PowerPC core time base unit enable. */
@ -88,8 +103,9 @@ typedef struct sysconf8349 {
#define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */ #define SPCR_TSEC2DP 0x00000030 /* TSEC2 data priority. */
#define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */ #define SPCR_TSEC2BDP 0x0000000C /* TSEC2 buffer descriptor priority. */
#define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */ #define SPCR_TSEC2EP 0x00000003 /* TSEC2 emergency priority. */
#define SPCR_RES ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_TBEN|SPCR_COREPR|SPCR_TSEC1DP \ #define SPCR_RES ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
|SPCR_TSEC1BDP|SPCR_TSEC1EP|SPCR_TSEC2DP|SPCR_TSEC2BDP|SPCR_TSEC2EP) | SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
| SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
u32 sicrl; /* System General Purpose Register Low */ u32 sicrl; /* System General Purpose Register Low */
#define SICRL_LDP_A 0x80000000 #define SICRL_LDP_A 0x80000000
#define SICRL_USB0 0x40000000 #define SICRL_USB0 0x40000000
@ -107,10 +123,11 @@ typedef struct sysconf8349 {
#define SICRL_GPIO1_J 0x00008000 #define SICRL_GPIO1_J 0x00008000
#define SICRL_GPIO1_K 0x00004000 #define SICRL_GPIO1_K 0x00004000
#define SICRL_GPIO1_L 0x00003000 #define SICRL_GPIO1_L 0x00003000
#define SICRL_RES ~(SICRL_LDP_A|SICRL_USB0|SICRL_USB1|SICRL_UART|SICRL_GPIO1_A \ #define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \
|SICRL_GPIO1_B|SICRL_GPIO1_C|SICRL_GPIO1_D|SICRL_GPIO1_E \ | SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \
|SICRL_GPIO1_F|SICRL_GPIO1_G|SICRL_GPIO1_H|SICRL_GPIO1_I \ | SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \
|SICRL_GPIO1_J|SICRL_GPIO1_K|SICRL_GPIO1_L ) | SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \
| SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L )
u32 sicrh; /* System General Purpose Register High */ u32 sicrh; /* System General Purpose Register High */
#define SICRH_DDR 0x80000000 #define SICRH_DDR 0x80000000
#define SICRH_TSEC1_A 0x10000000 #define SICRH_TSEC1_A 0x10000000
@ -137,30 +154,32 @@ typedef struct sysconf8349 {
#define SICRH_GPIO2_H 0x00000060 #define SICRH_GPIO2_H 0x00000060
#define SICRH_TSOBI1 0x00000002 #define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001 #define SICRH_TSOBI2 0x00000001
#define SICRh_RES ~(SICRH_DDR|SICRH_TSEC1_A|SICRH_TSEC1_B|SICRH_TSEC1_C \ #define SICRh_RES ~( SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
|SICRH_TSEC1_D|SICRH_TSEC1_E|SICRH_TSEC1_F|SICRH_TSEC2_A \ | SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
|SICRH_TSEC2_B|SICRH_TSEC2_C|SICRH_TSEC2_D|SICRH_TSEC2_E \ | SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
|SICRH_TSEC2_F|SICRH_TSEC2_G|SICRH_TSEC2_H|SICRH_GPIO2_A \ | SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
|SICRH_GPIO2_B|SICRH_GPIO2_C|SICRH_GPIO2_D|SICRH_GPIO2_E \ | SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \
|SICRH_GPIO2_F|SICRH_GPIO2_G|SICRH_GPIO2_H|SICRH_TSOBI1 \ | SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \
|SICRH_TSOBI2) | SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \
| SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
| SICRH_TSOBI2)
u8 res6[0xE4]; u8 res6[0xE4];
} sysconf8349_t; } sysconf8349_t;
/* /*
* Watch Dog Timer (WDT) Registers * Watch Dog Timer (WDT) Registers
*/ */
typedef struct wdt8349 { typedef struct wdt8349 {
u8 res0[4]; u8 res0[4];
u32 swcrr; /* System watchdog control register */ u32 swcrr; /* System watchdog control register */
u32 swcnr; /* System watchdog count register */ u32 swcnr; /* System watchdog count register */
#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field. #define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
#define SWCNR_RES ~(SWCNR_SWCN) #define SWCNR_RES ~(SWCNR_SWCN)
u8 res1[2]; u8 res1[2];
u16 swsrr; /* System watchdog service register */ u16 swsrr; /* System watchdog service register */
u8 res2[0xF0]; u8 res2[0xF0];
} wdt8349_t; } wdt8349_t;
/* /*
* RTC/PIT Module Registers * RTC/PIT Module Registers
*/ */
@ -173,7 +192,7 @@ typedef struct rtclk8349 {
#define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM) #define CNR_RES ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
u32 ldr; /* load register */ u32 ldr; /* load register */
u32 psr; /* prescale register */ u32 psr; /* prescale register */
u32 ctr; /* register */ u32 ctr; /* register */
u32 evr; /* event register */ u32 evr; /* event register */
#define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */ #define RTEVR_SIF 0x00000001 /* Second Interrupt Flag Bit */
#define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */ #define RTEVR_AIF 0x00000002 /* Alarm Interrupt Flag Bit */
@ -187,7 +206,7 @@ typedef struct rtclk8349 {
*/ */
typedef struct gtm8349 { typedef struct gtm8349 {
u8 cfr1; /* Timer1/2 Configuration */ u8 cfr1; /* Timer1/2 Configuration */
#define CFR1_PCAS 0x80 /* Pair Cascade mode */ #define CFR1_PCAS 0x80 /* Pair Cascade mode */
#define CFR1_BCM 0x40 /* Backward compatible mode */ #define CFR1_BCM 0x40 /* Backward compatible mode */
#define CFR1_STP2 0x20 /* Stop timer */ #define CFR1_STP2 0x20 /* Stop timer */
@ -196,8 +215,8 @@ typedef struct gtm8349 {
#define CFR1_GM1 0x04 /* Gate mode for pin 1 */ #define CFR1_GM1 0x04 /* Gate mode for pin 1 */
#define CFR1_STP1 0x02 /* Stop timer */ #define CFR1_STP1 0x02 /* Stop timer */
#define CFR1_RST1 0x01 /* Reset timer */ #define CFR1_RST1 0x01 /* Reset timer */
u8 res0[3]; u8 res0[3];
u8 cfr2; /* Timer3/4 Configuration */ u8 cfr2; /* Timer3/4 Configuration */
#define CFR2_PCAS 0x80 /* Pair Cascade mode */ #define CFR2_PCAS 0x80 /* Pair Cascade mode */
#define CFR2_SCAS 0x40 /* Super Cascade mode */ #define CFR2_SCAS 0x40 /* Super Cascade mode */
#define CFR2_STP4 0x20 /* Stop timer */ #define CFR2_STP4 0x20 /* Stop timer */
@ -206,8 +225,8 @@ typedef struct gtm8349 {
#define CFR2_GM3 0x04 /* Gate mode for pin 3 */ #define CFR2_GM3 0x04 /* Gate mode for pin 3 */
#define CFR2_STP3 0x02 /* Stop timer */ #define CFR2_STP3 0x02 /* Stop timer */
#define CFR2_RST3 0x01 /* Reset timer */ #define CFR2_RST3 0x01 /* Reset timer */
u8 res1[10]; u8 res1[10];
u16 mdr1; /* Timer1 Mode Register */ u16 mdr1; /* Timer1 Mode Register */
#define MDR_SPS 0xff00 /* Secondary Prescaler value */ #define MDR_SPS 0xff00 /* Secondary Prescaler value */
#define MDR_CE 0x00c0 /* Capture edge and enable interrupt */ #define MDR_CE 0x00c0 /* Capture edge and enable interrupt */
#define MDR_OM 0x0020 /* Output mode */ #define MDR_OM 0x0020 /* Output mode */
@ -215,40 +234,40 @@ typedef struct gtm8349 {
#define MDR_FRR 0x0008 /* Free run/restart */ #define MDR_FRR 0x0008 /* Free run/restart */
#define MDR_ICLK 0x0006 /* Input clock source for the timer */ #define MDR_ICLK 0x0006 /* Input clock source for the timer */
#define MDR_GE 0x0001 /* Gate enable */ #define MDR_GE 0x0001 /* Gate enable */
u16 mdr2; /* Timer2 Mode Register */ u16 mdr2; /* Timer2 Mode Register */
u16 rfr1; /* Timer1 Reference Register */ u16 rfr1; /* Timer1 Reference Register */
u16 rfr2; /* Timer2 Reference Register */ u16 rfr2; /* Timer2 Reference Register */
u16 cpr1; /* Timer1 Capture Register */ u16 cpr1; /* Timer1 Capture Register */
u16 cpr2; /* Timer2 Capture Register */ u16 cpr2; /* Timer2 Capture Register */
u16 cnr1; /* Timer1 Counter Register */ u16 cnr1; /* Timer1 Counter Register */
u16 cnr2; /* Timer2 Counter Register */ u16 cnr2; /* Timer2 Counter Register */
u16 mdr3; /* Timer3 Mode Register */ u16 mdr3; /* Timer3 Mode Register */
u16 mdr4; /* Timer4 Mode Register */ u16 mdr4; /* Timer4 Mode Register */
u16 rfr3; /* Timer3 Reference Register */ u16 rfr3; /* Timer3 Reference Register */
u16 rfr4; /* Timer4 Reference Register */ u16 rfr4; /* Timer4 Reference Register */
u16 cpr3; /* Timer3 Capture Register */ u16 cpr3; /* Timer3 Capture Register */
u16 cpr4; /* Timer4 Capture Register */ u16 cpr4; /* Timer4 Capture Register */
u16 cnr3; /* Timer3 Counter Register */ u16 cnr3; /* Timer3 Counter Register */
u16 cnr4; /* Timer4 Counter Register */ u16 cnr4; /* Timer4 Counter Register */
u16 evr1; /* Timer1 Event Register */ u16 evr1; /* Timer1 Event Register */
u16 evr2; /* Timer2 Event Register */ u16 evr2; /* Timer2 Event Register */
u16 evr3; /* Timer3 Event Register */ u16 evr3; /* Timer3 Event Register */
u16 evr4; /* Timer4 Event Register */ u16 evr4; /* Timer4 Event Register */
#define GTEVR_REF 0x0002 /* Output reference event */ #define GTEVR_REF 0x0002 /* Output reference event */
#define GTEVR_CAP 0x0001 /* Counter Capture event */ #define GTEVR_CAP 0x0001 /* Counter Capture event */
#define GTEVR_RES ~(EVR_CAP|EVR_REF) #define GTEVR_RES ~(EVR_CAP|EVR_REF)
u16 psr1; /* Timer1 Prescaler Register */ u16 psr1; /* Timer1 Prescaler Register */
u16 psr2; /* Timer2 Prescaler Register */ u16 psr2; /* Timer2 Prescaler Register */
u16 psr3; /* Timer3 Prescaler Register */ u16 psr3; /* Timer3 Prescaler Register */
u16 psr4; /* Timer4 Prescaler Register */ u16 psr4; /* Timer4 Prescaler Register */
u8 res[0xC0]; u8 res[0xC0];
} gtm8349_t; } gtm8349_t;
/* /*
* Integrated Programmable Interrupt Controller * Integrated Programmable Interrupt Controller
*/ */
typedef struct ipic8349 { typedef struct ipic8349 {
u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */ u32 sicfr; /* System Global Interrupt Configuration Register (SICFR) */
#define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */ #define SICFR_HPI 0x7f000000 /* Highest Priority Interrupt */
#define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */ #define SICFR_MPSB 0x00400000 /* Mixed interrupts Priority Scheme for group B */
#define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */ #define SICFR_MPSA 0x00200000 /* Mixed interrupts Priority Scheme for group A */
@ -256,11 +275,11 @@ typedef struct ipic8349 {
#define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */ #define SICFR_IPSA 0x00010000 /* Internal interrupts Priority Scheme for group A */
#define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */ #define SICFR_HPIT 0x00000300 /* HPI priority position IPIC output interrupt Type */
#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT) #define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */ u32 sivcr; /* System Global Interrupt Vector Register (SIVCR) */
#define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */ #define SICVR_IVECX 0xfc000000 /* Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation) */
#define SICVR_IVEC 0x0000007f /* Interrupt vector */ #define SICVR_IVEC 0x0000007f /* Interrupt vector */
#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC) #define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */ u32 sipnr_h; /* System Internal Interrupt Pending Register - High (SIPNR_H) */
#define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */ #define SIIH_TSEC1TX 0x80000000 /* TSEC1 Tx interrupt */
#define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */ #define SIIH_TSEC1RX 0x40000000 /* TSEC1 Rx interrupt */
#define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */ #define SIIH_TSEC1ER 0x20000000 /* TSEC1 Eror interrupt */
@ -275,11 +294,12 @@ typedef struct ipic8349 {
#define SIIH_I2C1 0x00000004 /* I2C1 interrupt */ #define SIIH_I2C1 0x00000004 /* I2C1 interrupt */
#define SIIH_I2C2 0x00000002 /* I2C1 interrupt */ #define SIIH_I2C2 0x00000002 /* I2C1 interrupt */
#define SIIH_SPI 0x00000001 /* SPI interrupt */ #define SIIH_SPI 0x00000001 /* SPI interrupt */
#define SIIH_RES ~(SIIH_TSEC1TX|SIIH_TSEC1RX|SIIH_TSEC1ER|SIIH_TSEC2TX \ #define SIIH_RES ~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
|SIIH_TSEC2RX|SIIH_TSEC2ER|SIIH_USB2DR|SIIH_USB2MPH \ | SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
|SIIH_UART1 |SIIH_UART2 |SIIH_SEC |SIIH_I2C1 \ | SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \
|SIIH_I2C2 |SIIH_SPI) | SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \
u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */ | SIIH_I2C2 | SIIH_SPI)
u32 sipnr_l; /* System Internal Interrupt Pending Register - Low (SIPNR_L) */
#define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */ #define SIIL_RTCS 0x80000000 /* RTC SECOND interrupt */
#define SIIL_PIT 0x40000000 /* PIT interrupt */ #define SIIL_PIT 0x40000000 /* PIT interrupt */
#define SIIL_PCI1 0x20000000 /* PCI1 interrupt */ #define SIIL_PCI1 0x20000000 /* PCI1 interrupt */
@ -302,20 +322,21 @@ typedef struct ipic8349 {
#define SIIL_GTM1 0x00000020 /* GTM1 interrupt */ #define SIIL_GTM1 0x00000020 /* GTM1 interrupt */
#define SIIL_GTM5 0x00000010 /* GTM5 interrupt */ #define SIIL_GTM5 0x00000010 /* GTM5 interrupt */
#define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */ #define SIIL_DPTC 0x00000001 /* DPTC interrupt (!!! Invisible for user !!!) */
#define SIIL_RES ~(SIIL_RTCS |SIIL_PIT |SIIL_PCI1 |SIIL_PCI2 |SIIL_RTCA \ #define SIIL_RES ~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
|SIIL_MU |SIIL_SBA |SIIL_DMA |SIIL_GTM4 |SIIL_GTM8 \ | SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
|SIIL_GPIO1|SIIL_GPIO2|SIIL_DDR |SIIL_LBC |SIIL_GTM2 \ | SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
|SIIL_GTM6 |SIIL_PMC |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \ | SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \
|SIIL_GTM5 |SIIL_DPTC ) | SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \
u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */ | SIIL_GTM5 |SIIL_DPTC )
u8 res0[8]; u32 siprr_a; /* System Internal Interrupt Group A Priority Register (PRR) */
u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */ u8 res0[8];
u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */ u32 siprr_d; /* System Internal Interrupt Group D Priority Register (PRR) */
u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */ u32 simsr_h; /* System Internal Interrupt Mask Register - High (SIIH) */
u8 res1[4]; u32 simsr_l; /* System Internal Interrupt Mask Register - Low (SIIL) */
u32 sepnr; /* System External Interrupt Pending Register (SEI) */ u8 res1[4];
u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */ u32 sepnr; /* System External Interrupt Pending Register (SEI) */
u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */ u32 smprr_a; /* System Mixed Interrupt Group A Priority Register (PRR) */
u32 smprr_b; /* System Mixed Interrupt Group B Priority Register (PRR) */
#define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */ #define PRR_0 0xe0000000 /* Priority Register, Position 0 programming */
#define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */ #define PRR_1 0x1c000000 /* Priority Register, Position 1 programming */
#define PRR_2 0x03800000 /* Priority Register, Position 2 programming */ #define PRR_2 0x03800000 /* Priority Register, Position 2 programming */
@ -325,7 +346,7 @@ typedef struct ipic8349 {
#define PRR_6 0x00000380 /* Priority Register, Position 6 programming */ #define PRR_6 0x00000380 /* Priority Register, Position 6 programming */
#define PRR_7 0x00000070 /* Priority Register, Position 7 programming */ #define PRR_7 0x00000070 /* Priority Register, Position 7 programming */
#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7) #define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
u32 semsr; /* System External Interrupt Mask Register (SEI) */ u32 semsr; /* System External Interrupt Mask Register (SEI) */
#define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */ #define SEI_IRQ0 0x80000000 /* IRQ0 external interrupt */
#define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */ #define SEI_IRQ1 0x40000000 /* IRQ1 external interrupt */
#define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */ #define SEI_IRQ2 0x20000000 /* IRQ2 external interrupt */
@ -335,9 +356,10 @@ typedef struct ipic8349 {
#define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */ #define SEI_IRQ6 0x02000000 /* IRQ6 external interrupt */
#define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */ #define SEI_IRQ7 0x01000000 /* IRQ7 external interrupt */
#define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */ #define SEI_SIRQ0 0x00008000 /* SIRQ0 external interrupt */
#define SEI_RES ~( SEI_IRQ0 |SEI_IRQ1 |SEI_IRQ2 |SEI_IRQ3 |SEI_IRQ4 \ #define SEI_RES ~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \
|SEI_IRQ5 |SEI_IRQ6 |SEI_IRQ7 |SEI_SIRQ0) | SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \
u32 secnr; /* System External Interrupt Control Register (SECNR) */ | SEI_SIRQ0)
u32 secnr; /* System External Interrupt Control Register (SECNR) */
#define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */ #define SECNR_MIXB0T 0xc0000000 /* MIXB0 priority position IPIC output interrupt type */
#define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */ #define SECNR_MIXB1T 0x30000000 /* MIXB1 priority position IPIC output interrupt type */
#define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */ #define SECNR_MIXA0T 0x00c00000 /* MIXA0 priority position IPIC output interrupt type */
@ -350,11 +372,12 @@ typedef struct ipic8349 {
#define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */ #define SECNR_EDI5 0x00000400 /* IRQ5 external interrupt edge/level detect */
#define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */ #define SECNR_EDI6 0x00000200 /* IRQ6 external interrupt edge/level detect */
#define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */ #define SECNR_EDI7 0x00000100 /* IRQ7 external interrupt edge/level detect */
#define SECNR_RES ~( SECNR_MIXB0T|SECNR_MIXB1T|SECNR_MIXA0T|SECNR_SYSA1T \ #define SECNR_RES ~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \
|SECNR_EDI0 |SECNR_EDI1 |SECNR_EDI2 |SECNR_EDI3 \ | SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \
|SECNR_EDI4 |SECNR_EDI5 |SECNR_EDI6 |SECNR_EDI7) | SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \
u32 sersr; /* System Error Status Register (SERR) */ | SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7)
u32 sermr; /* System Error Mask Register (SERR) */ u32 sersr; /* System Error Status Register (SERR) */
u32 sermr; /* System Error Mask Register (SERR) */
#define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */ #define SERR_IRQ0 0x80000000 /* IRQ0 MCP request */
#define SERR_WDT 0x40000000 /* WDT MCP request */ #define SERR_WDT 0x40000000 /* WDT MCP request */
#define SERR_SBA 0x20000000 /* SBA MCP request */ #define SERR_SBA 0x20000000 /* SBA MCP request */
@ -364,17 +387,18 @@ typedef struct ipic8349 {
#define SERR_PCI2 0x02000000 /* PCI2 MCP request */ #define SERR_PCI2 0x02000000 /* PCI2 MCP request */
#define SERR_MU 0x01000000 /* MU MCP request */ #define SERR_MU 0x01000000 /* MU MCP request */
#define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */ #define SERR_RNC 0x00010000 /* MU MCP request (!!! Non-visible for users !!!) */
#define SERR_RES ~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_DDR |SERR_LBC \ #define SERR_RES ~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
|SERR_PCI1|SERR_PCI2|SERR_MU |SERR_RNC ) |SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
u32 sercr; /* System Error Control Register (SERCR) */ |SERR_RNC )
u32 sercr; /* System Error Control Register (SERCR) */
#define SERCR_MCPR 0x00000001 /* MCP Route */ #define SERCR_MCPR 0x00000001 /* MCP Route */
#define SERCR_RES ~(SERCR_MCPR) #define SERCR_RES ~(SERCR_MCPR)
u8 res2[4]; u8 res2[4];
u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */ u32 sifcr_h; /* System Internal Interrupt Force Register - High (SIIH) */
u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */ u32 sifcr_l; /* System Internal Interrupt Force Register - Low (SIIL) */
u32 sefcr; /* System External Interrupt Force Register (SEI) */ u32 sefcr; /* System External Interrupt Force Register (SEI) */
u32 serfr; /* System Error Force Register (SERR) */ u32 serfr; /* System Error Force Register (SERR) */
u8 res3[0xA0]; u8 res3[0xA0];
} ipic8349_t; } ipic8349_t;
/* /*
@ -382,10 +406,10 @@ typedef struct ipic8349 {
*/ */
typedef struct arbiter8349 { typedef struct arbiter8349 {
u32 acr; /* Arbiter Configuration Register */ u32 acr; /* Arbiter Configuration Register */
#define ACR_COREDIS 0x10000000 /* Core disable. */ #define ACR_COREDIS 0x10000000 /* Core disable. */
#define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */ #define ACR_PIPE_DEP 0x00070000 /* Pipeline depth (number of outstanding transactions). */
#define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */ #define ACR_PCI_RPTCNT 0x00007000 /* PCI repeat count. */
#define ACR_RPTCNT 0x00000700 /* Repeat count. */ #define ACR_RPTCNT 0x00000700 /* Repeat count. */
#define ACR_APARK 0x00000030 /* Address parking. */ #define ACR_APARK 0x00000030 /* Address parking. */
#define ACR_PARKM 0x0000000F /* Parking master. */ #define ACR_PARKM 0x0000000F /* Parking master. */
#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM) #define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
@ -420,7 +444,7 @@ typedef struct arbiter8349 {
* Reset Module * Reset Module
*/ */
typedef struct reset8349 { typedef struct reset8349 {
u32 rcwl; /* RCWL Register */ u32 rcwl; /* RCWL Register */
#define RCWL_LBIUCM 0x80000000 /* LBIUCM */ #define RCWL_LBIUCM 0x80000000 /* LBIUCM */
#define RCWL_LBIUCM_SHIFT 31 #define RCWL_LBIUCM_SHIFT 31
#define RCWL_DDRCM 0x40000000 /* DDRCM */ #define RCWL_DDRCM 0x40000000 /* DDRCM */
@ -433,8 +457,8 @@ typedef struct reset8349 {
#define RCWL_CEVCOD 0x000000C0 /* CEVCOD */ #define RCWL_CEVCOD 0x000000C0 /* CEVCOD */
#define RCWL_CEPDF 0x00000020 /* CEPDF */ #define RCWL_CEPDF 0x00000020 /* CEPDF */
#define RCWL_CEPMF 0x0000001F /* CEPMF */ #define RCWL_CEPMF 0x0000001F /* CEPMF */
#define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF) #define RCWL_RES ~(RCWL_BIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
u32 rcwh; /* RCHL Register */ u32 rcwh; /* RCHL Register */
#define RCWH_PCIHOST 0x80000000 /* PCIHOST */ #define RCWH_PCIHOST 0x80000000 /* PCIHOST */
#define RCWH_PCIHOST_SHIFT 31 #define RCWH_PCIHOST_SHIFT 31
#define RCWH_PCI64 0x40000000 /* PCI64 */ #define RCWH_PCI64 0x40000000 /* PCI64 */
@ -450,11 +474,13 @@ typedef struct reset8349 {
#define RCWH_TPR 0x00000100 /* TPR */ #define RCWH_TPR 0x00000100 /* TPR */
#define RCWH_TLE 0x00000008 /* TLE */ #define RCWH_TLE 0x00000008 /* TLE */
#define RCWH_LALE 0x00000004 /* LALE */ #define RCWH_LALE 0x00000004 /* LALE */
#define RCWH_RES ~(RCWH_PCIHOST|RCWH_PCI64|RCWH_PCI1ARB|RCWH_PCI2ARB \ #define RCWH_RES ~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
|RCWH_COREDIS|RCWH_BMS|RCWH_BOOTSEQ|RCWH_SWEN|RCWH_ROMLOC \ | RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
|RCWH_TSEC1M|RCWH_TSEC2M|RCWH_TPR|RCWH_TLE|RCWH_LALE) | RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
u8 res0[8]; | RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \
u32 rsr; /* Reset status Register */ | RCWH_TLE | RCWH_LALE)
u8 res0[8];
u32 rsr; /* Reset status Register */
#define RSR_RSTSRC 0xE0000000 /* Reset source */ #define RSR_RSTSRC 0xE0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 29 #define RSR_RSTSRC_SHIFT 29
#define RSR_BSF 0x00010000 /* Boot seq. fail */ #define RSR_BSF 0x00010000 /* Boot seq. fail */
@ -477,37 +503,38 @@ typedef struct reset8349 {
#define RSR_SRS_SHIFT 1 #define RSR_SRS_SHIFT 1
#define RSR_HRS 0x00000001 /* hard reset status */ #define RSR_HRS 0x00000001 /* hard reset status */
#define RSR_HRS_SHIFT 0 #define RSR_HRS_SHIFT 0
#define RSR_RES ~(RSR_RSTSRC|RSR_BSF|RSR_SWSR|RSR_SWHR|RSR_JHRS|RSR_JSRS|RSR_CSHR|RSR_SWRS|RSR_BMRS|RSR_SRS|RSR_HRS) #define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS)
u32 rmr; /* Reset mode Register */ u32 rmr; /* Reset mode Register */
#define RMR_CSRE 0x00000001 /* checkstop reset enable */ #define RMR_CSRE 0x00000001 /* checkstop reset enable */
#define RMR_CSRE_SHIFT 0 #define RMR_CSRE_SHIFT 0
#define RMR_RES ~(RMR_CSRE) #define RMR_RES ~(RMR_CSRE)
u32 rpr; /* Reset protection Register */ u32 rpr; /* Reset protection Register */
u32 rcr; /* Reset Control Register */ u32 rcr; /* Reset Control Register */
#define RCR_SWHR 0x00000002 /* software hard reset */ #define RCR_SWHR 0x00000002 /* software hard reset */
#define RCR_SWSR 0x00000001 /* software soft reset */ #define RCR_SWSR 0x00000001 /* software soft reset */
#define RCR_RES ~(RCR_SWHR|RCR_SWSR) #define RCR_RES ~(RCR_SWHR | RCR_SWSR)
u32 rcer; /* Reset Control Enable Register */ u32 rcer; /* Reset Control Enable Register */
#define RCER_CRE 0x00000001 /* software hard reset */ #define RCER_CRE 0x00000001 /* software hard reset */
#define RCER_RES ~(RCER_CRE) #define RCER_RES ~(RCER_CRE)
u8 res1[0xDC]; u8 res1[0xDC];
} reset8349_t; } reset8349_t;
typedef struct clk8349 { typedef struct clk8349 {
u32 spmr; /* system PLL mode Register */ u32 spmr; /* system PLL mode Register */
#define SPMR_LBIUCM 0x80000000 /* LBIUCM */ #define SPMR_LBIUCM 0x80000000 /* LBIUCM */
#define SPMR_DDRCM 0x40000000 /* DDRCM */ #define SPMR_DDRCM 0x40000000 /* DDRCM */
#define SPMR_SVCOD 0x30000000 /* SVCOD */ #define SPMR_SVCOD 0x30000000 /* SVCOD */
#define SPMR_SPMF 0x0F000000 /* SPMF */ #define SPMR_SPMF 0x0F000000 /* SPMF */
#define SPMR_CKID 0x00800000 /* CKID */ #define SPMR_CKID 0x00800000 /* CKID */
#define SPMR_CKID_SHIFT 23 #define SPMR_CKID_SHIFT 23
#define SPMR_COREPLL 0x007F0000 /* COREPLL */ #define SPMR_COREPLL 0x007F0000 /* COREPLL */
#define SPMR_CEVCOD 0x000000C0 /* CEVCOD */ #define SPMR_CEVCOD 0x000000C0 /* CEVCOD */
#define SPMR_CEPDF 0x00000020 /* CEPDF */ #define SPMR_CEPDF 0x00000020 /* CEPDF */
#define SPMR_CEPMF 0x0000001F /* CEPMF */ #define SPMR_CEPMF 0x0000001F /* CEPMF */
#define SPMR_RES ~(SPMR_LBIUCM|SPMR_DDRCM|SPMR_SVCOD|SPMR_SPMF|SPMR_CKID \ #define SPMR_RES ~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
|SPMR_COREPLL|SPMR_CEVCOD|SPMR_CEPDF|SPMR_CEPMF) | SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
u32 occr; /* output clock control Register */ | SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
u32 occr; /* output clock control Register */
#define OCCR_PCICOE0 0x80000000 /* PCICOE0 */ #define OCCR_PCICOE0 0x80000000 /* PCICOE0 */
#define OCCR_PCICOE1 0x40000000 /* PCICOE1 */ #define OCCR_PCICOE1 0x40000000 /* PCICOE1 */
#define OCCR_PCICOE2 0x20000000 /* PCICOE2 */ #define OCCR_PCICOE2 0x20000000 /* PCICOE2 */
@ -526,11 +553,13 @@ typedef struct clk8349 {
#define OCCR_PCICD7 0x00010000 /* PCICD7 */ #define OCCR_PCICD7 0x00010000 /* PCICD7 */
#define OCCR_PCI1CR 0x00000002 /* PCI1CR */ #define OCCR_PCI1CR 0x00000002 /* PCI1CR */
#define OCCR_PCI2CR 0x00000001 /* PCI2CR */ #define OCCR_PCI2CR 0x00000001 /* PCI2CR */
#define OCCR_RES ~(OCCR_PCICOE0|OCCR_PCICOE1|OCCR_PCICOE2|OCCR_PCICOE3|OCCR_PCICOE4 \ #define OCCR_RES ~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \
|OCCR_PCICOE5|OCCR_PCICOE6|OCCR_PCICOE7|OCCR_PCICD0|OCCR_PCICD1 \ | OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \
|OCCR_PCICD2 |OCCR_PCICD3 |OCCR_PCICD4 |OCCR_PCICD5|OCCR_PCICD6 \ | OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \
|OCCR_PCICD7 |OCCR_PCI1CR |OCCR_PCI2CR ) | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICD3 \
u32 sccr; /* system clock control Register */ | OCCR_PCICD4 | OCCR_PCICD5 | OCCR_PCICD6 \
| OCCR_PCICD7 | OCCR_PCI1CR | OCCR_PCI2CR )
u32 sccr; /* system clock control Register */
#define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */ #define SCCR_TSEC1CM 0xc0000000 /* TSEC1CM */
#define SCCR_TSEC1CM_SHIFT 30 #define SCCR_TSEC1CM_SHIFT 30
#define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */ #define SCCR_TSEC2CM 0x30000000 /* TSEC2CM */
@ -542,23 +571,23 @@ typedef struct clk8349 {
#define SCCR_USBDRCM 0x00300000 /* USBDRCM */ #define SCCR_USBDRCM 0x00300000 /* USBDRCM */
#define SCCR_USBDRCM_SHIFT 20 #define SCCR_USBDRCM_SHIFT 20
#define SCCR_PCICM 0x00010000 /* PCICM */ #define SCCR_PCICM 0x00010000 /* PCICM */
#define SCCR_RES ~( SCCR_TSEC1CM|SCCR_TSEC2CM|SCCR_ENCCM|SCCR_USBMPHCM \ #define SCCR_RES ~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
|SCCR_USBDRCM|SCCR_PCICM) | SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
u8 res0[0xF4]; u8 res0[0xF4];
} clk8349_t; } clk8349_t;
/* /*
* Power Management Control Module * Power Management Control Module
*/ */
typedef struct pmc8349 { typedef struct pmc8349 {
u32 pmccr; /* PMC Configuration Register */ u32 pmccr; /* PMC Configuration Register */
#define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */ #define PMCCR_SLPEN 0x00000001 /* System Low Power Enable */
#define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */ #define PMCCR_DLPEN 0x00000002 /* DDR SDRAM Low Power Enable */
#define PMCCR_RES ~(PMCCR_SLPEN|PMCCR_DLPEN) #define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN)
u32 pmcer; /* PMC Event Register */ u32 pmcer; /* PMC Event Register */
#define PMCER_PMCI 0x00000001 /* PMC Interrupt */ #define PMCER_PMCI 0x00000001 /* PMC Interrupt */
#define PMCER_RES ~(PMCER_PMCI) #define PMCER_RES ~(PMCER_PMCI)
u32 pmcmr; /* PMC Mask Register */ u32 pmcmr; /* PMC Mask Register */
#define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */ #define PMCMR_PMCIE 0x0001 /* PMC Interrupt Enable */
#define PMCMR_RES ~(PMCMR_PMCIE) #define PMCMR_RES ~(PMCMR_PMCIE)
u8 res0[0xF4]; u8 res0[0xF4];
@ -570,7 +599,7 @@ typedef struct pmc8349 {
*/ */
typedef struct gpio8349 { typedef struct gpio8349 {
u32 dir; /* direction register */ u32 dir; /* direction register */
u32 odr; /* open drain register */ u32 odr; /* open drain register */
u32 dat; /* data register */ u32 dat; /* data register */
u32 ier; /* interrupt event register */ u32 ier; /* interrupt event register */
u32 imr; /* interrupt mask register */ u32 imr; /* interrupt mask register */
@ -578,22 +607,22 @@ typedef struct gpio8349 {
u8 res0[0xE8]; u8 res0[0xE8];
} gpio8349_t; } gpio8349_t;
/* /*
* DDR Memory Controller Memory Map * DDR Memory Controller Memory Map
*/ */
typedef struct ddr_cs_bnds{ typedef struct ddr_cs_bnds{
u32 csbnds; u32 csbnds;
#define CSBNDS_SA 0x00FF0000 #define CSBNDS_SA 0x00FF0000
#define CSBNDS_SA_SHIFT 16 #define CSBNDS_SA_SHIFT 16
#define CSBNDS_EA 0x000000FF #define CSBNDS_EA 0x000000FF
#define CSBNDS_EA_SHIFT 0 #define CSBNDS_EA_SHIFT 0
u8 res0[4]; u8 res0[4];
} ddr_cs_bnds_t; } ddr_cs_bnds_t;
typedef struct ddr8349{ typedef struct ddr8349{
ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */ ddr_cs_bnds_t csbnds[4]; /**< Chip Select x Memory Bounds */
u8 res0[0x60]; u8 res0[0x60];
u32 cs_config[4]; /**< Chip Select x Configuration */ u32 cs_config[4]; /**< Chip Select x Configuration */
#define CSCONFIG_EN 0x80000000 #define CSCONFIG_EN 0x80000000
#define CSCONFIG_AP 0x00800000 #define CSCONFIG_AP 0x00800000
#define CSCONFIG_ROW_BIT 0x00000700 #define CSCONFIG_ROW_BIT 0x00000700
@ -605,8 +634,8 @@ typedef struct ddr8349{
#define CSCONFIG_COL_BIT_9 0x00000001 #define CSCONFIG_COL_BIT_9 0x00000001
#define CSCONFIG_COL_BIT_10 0x00000002 #define CSCONFIG_COL_BIT_10 0x00000002
#define CSCONFIG_COL_BIT_11 0x00000003 #define CSCONFIG_COL_BIT_11 0x00000003
u8 res1[0x78]; u8 res1[0x78];
u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */ u32 timing_cfg_1; /**< SDRAM Timing Configuration 1 */
#define TIMING_CFG1_PRETOACT 0x70000000 #define TIMING_CFG1_PRETOACT 0x70000000
#define TIMING_CFG1_PRETOACT_SHIFT 28 #define TIMING_CFG1_PRETOACT_SHIFT 28
#define TIMING_CFG1_ACTTOPRE 0x0F000000 #define TIMING_CFG1_ACTTOPRE 0x0F000000
@ -620,18 +649,18 @@ typedef struct ddr8349{
#define TIMING_CFG1_WRREC 0x00000700 #define TIMING_CFG1_WRREC 0x00000700
#define TIMING_CFG1_WRREC_SHIFT 8 #define TIMING_CFG1_WRREC_SHIFT 8
#define TIMING_CFG1_ACTTOACT 0x00000070 #define TIMING_CFG1_ACTTOACT 0x00000070
#define TIMING_CFG1_ACTTOACT_SHIFT 4 #define TIMING_CFG1_ACTTOACT_SHIFT 4
#define TIMING_CFG1_WRTORD 0x00000007 #define TIMING_CFG1_WRTORD 0x00000007
#define TIMING_CFG1_WRTORD_SHIFT 0 #define TIMING_CFG1_WRTORD_SHIFT 0
u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */ u32 timing_cfg_2; /**< SDRAM Timing Configuration 2 */
#define TIMING_CFG2_CPO 0x0F000000 #define TIMING_CFG2_CPO 0x0F000000
#define TIMING_CFG2_CPO_SHIFT 24 #define TIMING_CFG2_CPO_SHIFT 24
#define TIMING_CFG2_ACSM 0x00080000 #define TIMING_CFG2_ACSM 0x00080000
#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00 #define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
#define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10 #define TIMING_CFG2_WR_DATA_DELAY_SHIFT 10
u32 sdram_cfg; /**< SDRAM Control Configuration */ u32 sdram_cfg; /**< SDRAM Control Configuration */
#define SDRAM_CFG_MEM_EN 0x80000000 #define SDRAM_CFG_MEM_EN 0x80000000
#define SDRAM_CFG_SREN 0x40000000 #define SDRAM_CFG_SREN 0x40000000
#define SDRAM_CFG_ECC_EN 0x20000000 #define SDRAM_CFG_ECC_EN 0x20000000
@ -644,109 +673,108 @@ typedef struct ddr8349{
#define SDRAM_CFG_NCAP 0x00020000 #define SDRAM_CFG_NCAP 0x00020000
#define SDRAM_CFG_2T_EN 0x00008000 #define SDRAM_CFG_2T_EN 0x00008000
u8 res2[4]; u8 res2[4];
u32 sdram_mode; /**< SDRAM Mode Configuration */ u32 sdram_mode; /**< SDRAM Mode Configuration */
#define SDRAM_MODE_ESD 0xFFFF0000 #define SDRAM_MODE_ESD 0xFFFF0000
#define SDRAM_MODE_ESD_SHIFT 16 #define SDRAM_MODE_ESD_SHIFT 16
#define SDRAM_MODE_SD 0x0000FFFF #define SDRAM_MODE_SD 0x0000FFFF
#define SDRAM_MODE_SD_SHIFT 0 #define SDRAM_MODE_SD_SHIFT 0
u8 res3[8]; u8 res3[8];
u32 sdram_interval; /**< SDRAM Interval Configuration */ u32 sdram_interval; /**< SDRAM Interval Configuration */
#define SDRAM_INTERVAL_REFINT 0x3FFF0000 #define SDRAM_INTERVAL_REFINT 0x3FFF0000
#define SDRAM_INTERVAL_REFINT_SHIFT 16 #define SDRAM_INTERVAL_REFINT_SHIFT 16
#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF #define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
#define SDRAM_INTERVAL_BSTOPRE_SHIFT 0 #define SDRAM_INTERVAL_BSTOPRE_SHIFT 0
u8 res9[8]; u8 res9[8];
u32 sdram_clk_cntl; u32 sdram_clk_cntl;
u8 res4[0xCCC]; u8 res4[0xCCC];
u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */ u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */ u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */ u32 ecc_err_inject; /**< Memory Data Path Error Injection Mask ECC */
u8 res5[0x14]; u8 res5[0x14];
u32 capture_data_hi; /**< Memory Data Path Read Capture High */ u32 capture_data_hi; /**< Memory Data Path Read Capture High */
u32 capture_data_lo; /**< Memory Data Path Read Capture Low */ u32 capture_data_lo; /**< Memory Data Path Read Capture Low */
u32 capture_ecc; /**< Memory Data Path Read Capture ECC */ u32 capture_ecc; /**< Memory Data Path Read Capture ECC */
u8 res6[0x14]; u8 res6[0x14];
u32 err_detect; /**< Memory Error Detect */ u32 err_detect; /**< Memory Error Detect */
u32 err_disable; /**< Memory Error Disable */ u32 err_disable; /**< Memory Error Disable */
u32 err_int_en; /**< Memory Error Interrupt Enable */ u32 err_int_en; /**< Memory Error Interrupt Enable */
u32 capture_attributes; /**< Memory Error Attributes Capture */ u32 capture_attributes; /**< Memory Error Attributes Capture */
u32 capture_address; /**< Memory Error Address Capture */ u32 capture_address; /**< Memory Error Address Capture */
u32 capture_ext_address;/**< Memory Error Extended Address Capture */ u32 capture_ext_address;/**< Memory Error Extended Address Capture */
u32 err_sbe; /**< Memory Single-Bit ECC Error Management */ u32 err_sbe; /**< Memory Single-Bit ECC Error Management */
u8 res7[0xA4]; u8 res7[0xA4];
u32 debug_reg; u32 debug_reg;
u8 res8[0xFC]; u8 res8[0xFC];
} ddr8349_t; } ddr8349_t;
/* /*
* I2C1 Controller * I2C1 Controller
*/ */
/* /*
* DUART * DUART
*/ */
typedef struct duart8349{ typedef struct duart8349{
u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */ u8 urbr_ulcr_udlb; /**< combined register for URBR, UTHR and UDLB */
u8 uier_udmb; /**< combined register for UIER and UDMB */ u8 uier_udmb; /**< combined register for UIER and UDMB */
u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */ u8 uiir_ufcr_uafr; /**< combined register for UIIR, UFCR and UAFR */
u8 ulcr; /**< line control register */ u8 ulcr; /**< line control register */
u8 umcr; /**< MODEM control register */ u8 umcr; /**< MODEM control register */
u8 ulsr; /**< line status register */ u8 ulsr; /**< line status register */
u8 umsr; /**< MODEM status register */ u8 umsr; /**< MODEM status register */
u8 uscr; /**< scratch register */ u8 uscr; /**< scratch register */
u8 res0[8]; u8 res0[8];
u8 udsr; /**< DMA status register */ u8 udsr; /**< DMA status register */
u8 res1[3]; u8 res1[3];
u8 res2[0xEC]; u8 res2[0xEC];
} duart8349_t; } duart8349_t;
/* /*
* Local Bus Controller Registers * Local Bus Controller Registers
*/ */
typedef struct lbus_bank{ typedef struct lbus_bank{
u32 br; /**< Base Register */ u32 br; /**< Base Register */
u32 or; /**< Base Register */ u32 or; /**< Base Register */
} lbus_bank_t; } lbus_bank_t;
typedef struct lbus8349 { typedef struct lbus8349 {
lbus_bank_t bank[8]; lbus_bank_t bank[8];
u8 res0[0x28]; u8 res0[0x28];
u32 mar; /**< UPM Address Register */ u32 mar; /**< UPM Address Register */
u8 res1[0x4]; u8 res1[0x4];
u32 mamr; /**< UPMA Mode Register */ u32 mamr; /**< UPMA Mode Register */
u32 mbmr; /**< UPMB Mode Register */ u32 mbmr; /**< UPMB Mode Register */
u32 mcmr; /**< UPMC Mode Register */ u32 mcmr; /**< UPMC Mode Register */
u8 res2[0x8]; u8 res2[0x8];
u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */ u32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
u32 mdr; /**< UPM Data Register */ u32 mdr; /**< UPM Data Register */
u8 res3[0x8]; u8 res3[0x8];
u32 lsdmr; /**< SDRAM Mode Register */ u32 lsdmr; /**< SDRAM Mode Register */
u8 res4[0x8]; u8 res4[0x8];
u32 lurt; /**< UPM Refresh Timer */ u32 lurt; /**< UPM Refresh Timer */
u32 lsrt; /**< SDRAM Refresh Timer */ u32 lsrt; /**< SDRAM Refresh Timer */
u8 res5[0x8]; u8 res5[0x8];
u32 ltesr; /**< Transfer Error Status Register */ u32 ltesr; /**< Transfer Error Status Register */
u32 ltedr; /**< Transfer Error Disable Register */ u32 ltedr; /**< Transfer Error Disable Register */
u32 lteir; /**< Transfer Error Interrupt Register */ u32 lteir; /**< Transfer Error Interrupt Register */
u32 lteatr; /**< Transfer Error Attributes Register */ u32 lteatr; /**< Transfer Error Attributes Register */
u32 ltear; /**< Transfer Error Address Register */ u32 ltear; /**< Transfer Error Address Register */
u8 res6[0xC]; u8 res6[0xC];
u32 lbcr; /**< Configuration Register */ u32 lbcr; /**< Configuration Register */
#define LBCR_LDIS 0x80000000 #define LBCR_LDIS 0x80000000
#define LBCR_LDIS_SHIFT 31 #define LBCR_LDIS_SHIFT 31
#define LBCR_BCTLC 0x00C00000 #define LBCR_BCTLC 0x00C00000
#define LBCR_BCTLC_SHIFT 22 #define LBCR_BCTLC_SHIFT 22
#define LBCR_LPBSE 0x00020000 #define LBCR_LPBSE 0x00020000
#define LBCR_LPBSE_SHIFT 17 #define LBCR_LPBSE_SHIFT 17
#define LBCR_EPAR 0x00010000 #define LBCR_EPAR 0x00010000
#define LBCR_EPAR_SHIFT 16 #define LBCR_EPAR_SHIFT 16
#define LBCR_BMT 0x0000FF00 #define LBCR_BMT 0x0000FF00
#define LBCR_BMT_SHIFT 8 #define LBCR_BMT_SHIFT 8
u32 lcrr; /**< Clock Ratio Register */ u32 lcrr; /**< Clock Ratio Register */
#define LCRR_DBYP 0x80000000 #define LCRR_DBYP 0x80000000
#define LCRR_DBYP_SHIFT 31 #define LCRR_DBYP_SHIFT 31
#define LCRR_BUFCMDC 0x30000000 #define LCRR_BUFCMDC 0x30000000
@ -759,8 +787,8 @@ typedef struct lbus8349 {
#define LCRR_CLKDIV_SHIFT 0 #define LCRR_CLKDIV_SHIFT 0
u8 res7[0x28]; u8 res7[0x28];
u8 res8[0xF00]; u8 res8[0xF00];
} lbus8349_t; } lbus8349_t;
/* /*
@ -768,16 +796,16 @@ typedef struct lbus8349 {
*/ */
typedef struct spi8349 typedef struct spi8349
{ {
u32 mode; /**< mode register */ u32 mode; /**< mode register */
u32 event; /**< event register */ u32 event; /**< event register */
u32 mask; /**< mask register */ u32 mask; /**< mask register */
u32 com; /**< command register */ u32 com; /**< command register */
u8 res0[0x10]; u8 res0[0x10];
u32 tx; /**< transmit register */ u32 tx; /**< transmit register */
u32 rx; /**< receive register */ u32 rx; /**< receive register */
u8 res1[0xD8]; u8 res1[0xD8];
} spi8349_t; } spi8349_t;
typedef struct dma8349 { typedef struct dma8349 {
u8 fixme[0x300]; u8 fixme[0x300];
} dma8349_t; } dma8349_t;
@ -814,7 +842,7 @@ typedef struct pci_outbound_window {
} pot8349_t; } pot8349_t;
/* /*
* Sequencer * Sequencer
*/ */
typedef struct ios8349 { typedef struct ios8349 {
pot8349_t pot[6]; pot8349_t pot[6];
#define POTAR_TA_MASK 0x000fffff #define POTAR_TA_MASK 0x000fffff
@ -905,7 +933,7 @@ typedef struct pcictrl8349 {
#define EATCR_TS_3 0x00300000 #define EATCR_TS_3 0x00300000
#define EATCR_ES_MASK 0x000f0000 /* error source */ #define EATCR_ES_MASK 0x000f0000 /* error source */
#define EATCR_ES_EM 0x00000000 /* external master */ #define EATCR_ES_EM 0x00000000 /* external master */
#define EATCR_ES_DMA 0x00050000 #define EATCR_ES_DMA 0x00050000
#define EATCR_CMD_MASK 0x0000f000 #define EATCR_CMD_MASK 0x0000f000
#define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable*/ #define EATCR_HBE_MASK 0x00000f00 /* PCI high byte enable*/
#define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */ #define EATCR_BE_MASK 0x000000f0 /* PCI byte enable */
@ -948,7 +976,7 @@ typedef struct pcictrl8349 {
#define PIWAR_RTT_SNOOP 0x00050000 #define PIWAR_RTT_SNOOP 0x00050000
#define PIWAR_WTT_MASK 0x0000f000 #define PIWAR_WTT_MASK 0x0000f000
#define PIWAR_WTT_NO_SNOOP 0x00004000 #define PIWAR_WTT_NO_SNOOP 0x00004000
#define PIWAR_WTT_SNOOP 0x00005000 #define PIWAR_WTT_SNOOP 0x00005000
#define PIWAR_IWS_MASK 0x0000003F #define PIWAR_IWS_MASK 0x0000003F
#define PIWAR_IWS_4K 0x0000000B #define PIWAR_IWS_4K 0x0000000B
#define PIWAR_IWS_8K 0x0000000C #define PIWAR_IWS_8K 0x0000000C
@ -973,7 +1001,7 @@ typedef struct pcictrl8349 {
} pcictrl8349_t; } pcictrl8349_t;
/* /*
* USB * USB
*/ */
typedef struct usb8349 { typedef struct usb8349 {
u8 fixme[0x2000]; u8 fixme[0x2000];
@ -1000,9 +1028,9 @@ typedef struct immap {
rtclk8349_t pit; /* Periodic Interval Timer */ rtclk8349_t pit; /* Periodic Interval Timer */
gtm8349_t gtm[2]; /* Global Timers Module */ gtm8349_t gtm[2]; /* Global Timers Module */
ipic8349_t ipic; /* Integrated Programmable Interrupt Controller */ ipic8349_t ipic; /* Integrated Programmable Interrupt Controller */
arbiter8349_t arbiter; /* System Arbiter Registers */ arbiter8349_t arbiter; /* System Arbiter Registers */
reset8349_t reset; /* Reset Module */ reset8349_t reset; /* Reset Module */
clk8349_t clk; /* System Clock Module */ clk8349_t clk; /* System Clock Module */
pmc8349_t pmc; /* Power Management Control Module */ pmc8349_t pmc; /* Power Management Control Module */
gpio8349_t pgio[2]; /* general purpose I/O module */ gpio8349_t pgio[2]; /* general purpose I/O module */
u8 res0[0x200]; u8 res0[0x200];
@ -1026,7 +1054,7 @@ typedef struct immap {
usb8349_t usb; usb8349_t usb;
tsec8349_t tsec[2]; tsec8349_t tsec[2];
u8 res7[0xA000]; u8 res7[0xA000];
security8349_t security; security8349_t security;
} immap_t; } immap_t;
#endif /* __IMMAP_8349__ */ #endif /* __IMMAP_8349__ */

69
include/asm-ppc/immap_85xx.h
View File

@ -9,9 +9,9 @@
#ifndef __IMMAP_85xx__ #ifndef __IMMAP_85xx__
#define __IMMAP_85xx__ #define __IMMAP_85xx__
/*
/* Local-Access Registers and ECM Registers(0x0000-0x2000) */ * Local-Access Registers and ECM Registers(0x0000-0x2000)
*/
typedef struct ccsr_local_ecm { typedef struct ccsr_local_ecm {
uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */ uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
char res1[4]; char res1[4];
@ -65,9 +65,9 @@ typedef struct ccsr_local_ecm {
char res24[492]; char res24[492];
} ccsr_local_ecm_t; } ccsr_local_ecm_t;
/*
/* DDR memory controller registers(0x2000-0x3000) */ * DDR memory controller registers(0x2000-0x3000)
*/
typedef struct ccsr_ddr { typedef struct ccsr_ddr {
uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */
char res1[4]; char res1[4];
@ -125,11 +125,9 @@ typedef struct ccsr_ddr {
char res12[240]; char res12[240];
} ccsr_ddr_t; } ccsr_ddr_t;
/*
* I2C Registers(0x3000-0x4000)
*/
/* I2C Registers(0x3000-0x4000) */
typedef struct ccsr_i2c { typedef struct ccsr_i2c {
u_char i2cadr; /* 0x3000 - I2C Address Register */ u_char i2cadr; /* 0x3000 - I2C Address Register */
#define MPC85xx_I2CADR_MASK 0xFE #define MPC85xx_I2CADR_MASK 0xFE
@ -246,10 +244,10 @@ typedef struct ccsr_lbc {
char res8[12072]; char res8[12072];
} ccsr_lbc_t; } ccsr_lbc_t;
/*
/* PCI Registers(0x8000-0x9000) */ * PCI Registers(0x8000-0x9000)
/* Omitting Reserved(0x9000-0x2_0000) */ * Omitting Reserved(0x9000-0x2_0000)
*/
typedef struct ccsr_pcix { typedef struct ccsr_pcix {
uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */ uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */
uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */ uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */
@ -314,9 +312,9 @@ typedef struct ccsr_pcix {
char res11[94688]; char res11[94688];
} ccsr_pcix_t; } ccsr_pcix_t;
/*
/* L2 Cache Registers(0x2_0000-0x2_1000) */ * L2 Cache Registers(0x2_0000-0x2_1000)
*/
typedef struct ccsr_l2cache { typedef struct ccsr_l2cache {
uint l2ctl; /* 0x20000 - L2 configuration register 0 */ uint l2ctl; /* 0x20000 - L2 configuration register 0 */
char res1[12]; char res1[12];
@ -358,9 +356,9 @@ typedef struct ccsr_l2cache {
char res15[420]; char res15[420];
} ccsr_l2cache_t; } ccsr_l2cache_t;
/*
/* DMA Registers(0x2_1000-0x2_2000) */ * DMA Registers(0x2_1000-0x2_2000)
*/
typedef struct ccsr_dma { typedef struct ccsr_dma {
char res1[256]; char res1[256];
uint mr0; /* 0x21100 - DMA 0 Mode Register */ uint mr0; /* 0x21100 - DMA 0 Mode Register */
@ -439,7 +437,9 @@ typedef struct ccsr_dma {
char res22[11516]; char res22[11516];
} ccsr_dma_t; } ccsr_dma_t;
/* tsec1 tsec2: 24000-26000 */ /*
* tsec1 tsec2: 24000-26000
*/
typedef struct ccsr_tsec { typedef struct ccsr_tsec {
char res1[16]; char res1[16];
uint ievent; /* 0x24010 - Interrupt Event Register */ uint ievent; /* 0x24010 - Interrupt Event Register */
@ -726,8 +726,9 @@ typedef struct ccsr_tsec {
char res74[1024]; char res74[1024];
} ccsr_tsec_t; } ccsr_tsec_t;
/* PIC Registers(0x2_6000-0x4_0000-0x8_0000) */ /*
* PIC Registers(0x2_6000-0x4_0000-0x8_0000)
*/
typedef struct ccsr_pic { typedef struct ccsr_pic {
char res0[106496]; /* 0x26000-0x40000 */ char res0[106496]; /* 0x26000-0x40000 */
char res1[64]; char res1[64];
@ -1033,15 +1034,18 @@ typedef struct ccsr_pic {
char res150[130892]; char res150[130892];
} ccsr_pic_t; } ccsr_pic_t;
/* CPM Block(0x8_0000-0xc_0000) */ /*
* CPM Block(0x8_0000-0xc_0000)
*/
#ifndef CONFIG_CPM2 #ifndef CONFIG_CPM2
typedef struct ccsr_cpm { typedef struct ccsr_cpm {
char res[262144]; char res[262144];
} ccsr_cpm_t; } ccsr_cpm_t;
#else #else
/* 0x8000-0x8ffff:DPARM */ /*
* 0x8000-0x8ffff:DPARM
/* 0x9000-0x90bff: General SIU */ * 0x9000-0x90bff: General SIU
*/
typedef struct ccsr_cpm_siu { typedef struct ccsr_cpm_siu {
char res1[80]; char res1[80];
uint smaer; uint smaer;
@ -1332,7 +1336,6 @@ typedef struct ccsr_cpm {
char res1[16*1024]; char res1[16*1024];
u_char im_dpram2[16*1024]; u_char im_dpram2[16*1024];
char res2[16*1024]; char res2[16*1024];
ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */
ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */ ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */
ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */
@ -1357,8 +1360,10 @@ typedef struct ccsr_cpm {
ccsr_cpm_iram_t im_cpm_iram; ccsr_cpm_iram_t im_cpm_iram;
} ccsr_cpm_t; } ccsr_cpm_t;
#endif #endif
/* RapidIO Registers(0xc_0000-0xe_0000) */
/*
* RapidIO Registers(0xc_0000-0xe_0000)
*/
typedef struct ccsr_rio { typedef struct ccsr_rio {
uint didcar; /* 0xc0000 - Device Identity Capability Register */ uint didcar; /* 0xc0000 - Device Identity Capability Register */
uint dicar; /* 0xc0004 - Device Information Capability Register */ uint dicar; /* 0xc0004 - Device Information Capability Register */
@ -1524,7 +1529,9 @@ typedef struct ccsr_rio {
char res58[60176]; char res58[60176];
} ccsr_rio_t; } ccsr_rio_t;
/* Global Utilities Register Block(0xe_0000-0xf_ffff) */ /*
* Global Utilities Register Block(0xe_0000-0xf_ffff)
*/
typedef struct ccsr_gur { typedef struct ccsr_gur {
uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ uint porpllsr; /* 0xe0000 - POR PLL ratio status register */
uint porbmsr; /* 0xe0004 - POR boot mode status register */ uint porbmsr; /* 0xe0004 - POR boot mode status register */

150
include/configs/MPC8349ADS.h
View File

@ -73,8 +73,6 @@
#define CFG_MEMTEST_START 0x00000000 /* memtest region */ #define CFG_MEMTEST_START 0x00000000 /* memtest region */
#define CFG_MEMTEST_END 0x00100000 #define CFG_MEMTEST_END 0x00100000
/* /*
* DDR Setup * DDR Setup
*/ */
@ -85,25 +83,23 @@
#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
#if defined(CONFIG_SPD_EEPROM) #if defined(CONFIG_SPD_EEPROM)
/* /*
* Determine DDR configuration from I2C interface. * Determine DDR configuration from I2C interface.
*/ */
#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
#else #else
/* /*
* Manually set up DDR parameters * Manually set up DDR parameters
*/ */
#define CFG_DDR_SIZE 256 /* Mb */ #define CFG_DDR_SIZE 256 /* Mb */
#define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) #define CFG_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
#define CFG_DDR_TIMING_1 0x37344321 #define CFG_DDR_TIMING_1 0x37344321
#define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ #define CFG_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ #define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
#define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ #define CFG_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
#define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ #define CFG_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
#endif #endif
/* /*
* SDRAM on the Local Bus * SDRAM on the Local Bus
*/ */
@ -126,7 +122,6 @@
#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
#define CFG_LBLAWAR0_PRELIM 0x80000016 /* 16Mb window size */ #define CFG_LBLAWAR0_PRELIM 0x80000016 /* 16Mb window size */
#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
#define CFG_MAX_FLASH_SECT 64 /* sectors per device */ #define CFG_MAX_FLASH_SECT 64 /* sectors per device */
@ -137,7 +132,6 @@
#define CFG_MID_FLASH_JUMP 0x7F000000 #define CFG_MID_FLASH_JUMP 0x7F000000
#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT #define CFG_RAMBOOT
#else #else
@ -153,7 +147,6 @@
#define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ #define CFG_BR1_PRELIM (CFG_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */
#define CFG_OR1_PRELIM 0xFFFFE8f0 /* length 32K */ #define CFG_OR1_PRELIM 0xFFFFE8f0 /* length 32K */
#define CONFIG_L1_INIT_RAM #define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_LOCK 1
#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
@ -198,11 +191,8 @@
*/ */
#define CFG_BR2_PRELIM 0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/ #define CFG_BR2_PRELIM 0xf0001861 /*Port-size=32bit, MSEL=SDRAM*/
#define CFG_LBLAWBAR2_PRELIM 0xF0000000
#define CFG_LBLAWBAR2_PRELIM 0xF0000000 #define CFG_LBLAWAR2_PRELIM 0x80000019 /*64M*/
#define CFG_LBLAWAR2_PRELIM 0x80000019 /*64M*/
/* /*
* The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64. * The SDRAM size in MB, CFG_LBC_SDRAM_SIZE, is 64.
@ -255,7 +245,7 @@
#define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) #define CFG_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
#define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \ #define CFG_LBC_LSDMR_COMMON ( CFG_LBC_LSDMR_RFEN \
| CFG_LBC_LSDMR_BSMA1516 \ | CFG_LBC_LSDMR_BSMA1516 \
| CFG_LBC_LSDMR_RFCR8 \ | CFG_LBC_LSDMR_RFCR8 \
| CFG_LBC_LSDMR_PRETOACT6 \ | CFG_LBC_LSDMR_PRETOACT6 \
| CFG_LBC_LSDMR_ACTTORW3 \ | CFG_LBC_LSDMR_ACTTORW3 \
@ -264,7 +254,6 @@
| CFG_LBC_LSDMR_CL3 \ | CFG_LBC_LSDMR_CL3 \
) )
/* /*
* SDRAM Controller configuration sequence. * SDRAM Controller configuration sequence.
*/ */
@ -278,13 +267,8 @@
| CFG_LBC_LSDMR_OP_MRW) | CFG_LBC_LSDMR_OP_MRW)
#define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \ #define CFG_LBC_LSDMR_5 ( CFG_LBC_LSDMR_COMMON \
| CFG_LBC_LSDMR_OP_NORMAL) | CFG_LBC_LSDMR_OP_NORMAL)
#endif #endif
/* /*
* Serial Port * Serial Port
*/ */
@ -322,7 +306,6 @@
#define CFG_TSEC2_OFFSET 0x25000 #define CFG_TSEC2_OFFSET 0x25000
#define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET) #define CFG_TSEC2 (CFG_IMMRBAR+CFG_TSEC2_OFFSET)
/* IO Configuration */ /* IO Configuration */
#define CFG_IO_CONF (\ #define CFG_IO_CONF (\
IO_CONF_UART |\ IO_CONF_UART |\
@ -347,7 +330,6 @@
#define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_PHYS 0xe2000000
#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
#define CFG_PCI2_MEM_BASE 0xA0000000 #define CFG_PCI2_MEM_BASE 0xA0000000
#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE #define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
@ -356,10 +338,7 @@
#define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */ #define CFG_PCI2_IO_SIZE 0x1000000 /* 16M */
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
//#define PCI_64BIT
#define PCI_ALL_PCI1 #define PCI_ALL_PCI1
//#define PCI_ONE_PCI1
//#define PCI_TWO_PCI1
#if defined(PCI_64BIT) #if defined(PCI_64BIT)
#undef PCI_ALL_PCI1 #undef PCI_ALL_PCI1
#undef PCI_TWO_PCI1 #undef PCI_TWO_PCI1
@ -373,9 +352,9 @@
#undef CONFIG_TULIP #undef CONFIG_TULIP
#if !defined(CONFIG_PCI_PNP) #if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xFIXME #define PCI_ENET0_IOADDR 0xFIXME
#define PCI_ENET0_MEMADDR 0xFIXME #define PCI_ENET0_MEMADDR 0xFIXME
#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
#endif #endif
#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
@ -383,9 +362,7 @@
#endif /* CONFIG_PCI */ #endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET) #if defined(CONFIG_TSEC_ENET)
#ifndef CONFIG_NET_MULTI #ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI 1 #define CONFIG_NET_MULTI 1
#endif #endif
@ -405,55 +382,54 @@
#endif /* CONFIG_TSEC_ENET */ #endif /* CONFIG_TSEC_ENET */
/* /*
* Environment * Environment
*/ */
#ifndef CFG_RAMBOOT #ifndef CFG_RAMBOOT
#define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SIZE 0x2000 #define CFG_ENV_SIZE 0x2000
#else #else
#define CFG_NO_FLASH 1 /* Flash is not usable now */ #define CFG_NO_FLASH 1 /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
#define CFG_ENV_SIZE 0x2000 #define CFG_ENV_SIZE 0x2000
#endif #endif
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if defined(CFG_RAMBOOT) #if defined(CFG_RAMBOOT)
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \ | CFG_CMD_PING \
| CFG_CMD_PCI \ | CFG_CMD_PCI \
| CFG_CMD_I2C) \ | CFG_CMD_I2C) \
& \ & \
~(CFG_CMD_ENV \ ~(CFG_CMD_ENV \
| CFG_CMD_LOADS)) | CFG_CMD_LOADS))
#else #else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL \
| CFG_CMD_PING \ | CFG_CMD_PING \
| CFG_CMD_I2C) \ | CFG_CMD_I2C) \
& \ & \
~(CFG_CMD_ENV \ ~(CFG_CMD_ENV \
| CFG_CMD_LOADS)) | CFG_CMD_LOADS))
#endif #endif
#else #else
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PCI \ | CFG_CMD_PCI \
| CFG_CMD_PING \ | CFG_CMD_PING \
| CFG_CMD_I2C) | CFG_CMD_I2C)
#else #else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \ #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_PING \ | CFG_CMD_PING \
| CFG_CMD_I2C \ | CFG_CMD_I2C \
| CFG_CMD_MII \ | CFG_CMD_MII \
) )
#endif #endif
#endif #endif
#include <cmd_confdefs.h> #include <cmd_confdefs.h>
@ -468,9 +444,9 @@
#define CFG_PROMPT "=> " /* Monitor Command Prompt */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB) #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#else #else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif #endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
@ -529,7 +505,6 @@
HRCWH_TSEC2M_IN_GMII ) HRCWH_TSEC2M_IN_GMII )
#endif #endif
#define CFG_HID0_INIT 0x000000000 #define CFG_HID0_INIT 0x000000000
#define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID0_FINAL CFG_HID0_INIT
@ -554,7 +529,6 @@
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif #endif
/* /*
* Environment Configuration * Environment Configuration
*/ */
@ -565,13 +539,13 @@
#define CONFIG_ETH1ADDR 00:E0:0C:00:7D:01 #define CONFIG_ETH1ADDR 00:E0:0C:00:7D:01
#endif #endif
#define CONFIG_IPADDR 10.193.20.150 #define CONFIG_IPADDR 192.168.1.253
#define CONFIG_HOSTNAME unknown #define CONFIG_HOSTNAME unknown
#define CONFIG_ROOTPATH /tftpboot/10.193.20.150 #define CONFIG_ROOTPATH /nfsroot
#define CONFIG_BOOTFILE /tftpboot/vmlinux.150 #define CONFIG_BOOTFILE your.uImage
#define CONFIG_SERVERIP 10.193.20.58 #define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK 255.255.255.0 #define CONFIG_NETMASK 255.255.255.0
@ -583,26 +557,26 @@
#define CONFIG_BAUDRATE 115200 #define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \ "netdev=eth0\0" \
"consoledev=ttyS0\0" \ "consoledev=ttyS0\0" \
"ramdiskaddr=400000\0" \ "ramdiskaddr=400000\0" \
"ramdiskfile=ramfs.83xx\0" \ "ramdiskfile=ramfs.83xx\0"
#define CONFIG_NFSBOOTCOMMAND \ #define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \ "setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \ "nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \ "console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \ "tftp $loadaddr $bootfile;" \
"bootm $loadaddr" "bootm $loadaddr"
#define CONFIG_RAMBOOTCOMMAND \ #define CONFIG_RAMBOOTCOMMAND \
"setenv bootargs root=/dev/ram rw " \ "setenv bootargs root=/dev/ram rw " \
"console=$consoledev,$baudrate $othbootargs;" \ "console=$consoledev,$baudrate $othbootargs;" \
"tftp $ramdiskaddr $ramdiskfile;" \ "tftp $ramdiskaddr $ramdiskfile;" \
"tftp $loadaddr $bootfile;" \ "tftp $loadaddr $bootfile;" \
"bootm $loadaddr $ramdiskaddr" "bootm $loadaddr $ramdiskaddr"
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND

69
include/configs/MPC8540EVAL.h
View File

@ -51,10 +51,13 @@
/* sysclk for MPC8540EVAL */ /* sysclk for MPC8540EVAL */
#if defined(CONFIG_SYSCLK_66M) #if defined(CONFIG_SYSCLK_66M)
#define CONFIG_SYS_CLK_FREQ 66000000 /* the oscillator on board is 66Mhz */ /*
/* can also get 66M clock from external PCI */ * the oscillator on board is 66Mhz
* can also get 66M clock from external PCI
*/
#define CONFIG_SYS_CLK_FREQ 66000000
#else #else
#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
#endif #endif
/* below can be toggled for performance analysis. otherwise use default */ /* below can be toggled for performance analysis. otherwise use default */
@ -194,11 +197,11 @@
#undef CONFIG_EEPRO100 #undef CONFIG_EEPRO100
#define CONFIG_TULIP #define CONFIG_TULIP
#define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_PNP /* do pci plug-and-play */
#if !defined(CONFIG_PCI_PNP) #if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xe0000000 #define PCI_ENET0_IOADDR 0xe0000000
#define PCI_ENET0_MEMADDR 0xe0000000 #define PCI_ENET0_MEMADDR 0xe0000000
#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/ #define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
#endif #endif
#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
#define CFG_PCI_SUBSYS_DEVICEID 0x0008 #define CFG_PCI_SUBSYS_DEVICEID 0x0008
@ -221,23 +224,23 @@
#define CONFIG_ETHPRIME "TSEC0" #define CONFIG_ETHPRIME "TSEC0"
#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */ #define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
#define INTEL_LXT971_PHY 1 /* on EVAL board. It is Davicom 9161 on ADS. */ #define INTEL_LXT971_PHY 1
#endif #endif
#undef DEBUG #undef DEBUG
/* Environment */ /* Environment */
#ifndef CFG_RAMBOOT #ifndef CFG_RAMBOOT
#if defined(CONFIG_RAM_AS_FLASH) #if defined(CONFIG_RAM_AS_FLASH)
#define CFG_ENV_IS_NOWHERE #define CFG_ENV_IS_NOWHERE
#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000) #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x100000)
#define CFG_ENV_SIZE 0x2000 #define CFG_ENV_SIZE 0x2000
#else #else
#define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ #define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#endif #endif
#define CFG_ENV_SIZE 0x2000 #define CFG_ENV_SIZE 0x2000
#else #else
/* #define CFG_NO_FLASH 1 */ /* Flash is not usable now */ /* #define CFG_NO_FLASH 1 */ /* Flash is not usable now */
#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
@ -245,7 +248,6 @@
#define CFG_ENV_SIZE 0x2000 #define CFG_ENV_SIZE 0x2000
#endif #endif
/*#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.1.10:/tftproot/192.168.1.11 ip=192.168.1.11:192.168.1.10:192.168.1.0:255.255.255.0:mpc8540ads-003:eth0:off console=ttyS0,115200"*/
#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200" #define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000" #define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
@ -254,21 +256,24 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
#if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH) #if defined(CFG_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_PCI | CFG_CMD_I2C ) & \ #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \
| CFG_CMD_PCI | CFG_CMD_I2C ) & \
~(CFG_CMD_ENV | CFG_CMD_LOADS )) ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
#else
#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C ) & \
~(CFG_CMD_ENV | \
CFG_CMD_LOADS ))
#endif
#else #else
#if defined(CONFIG_PCI) #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_PING \
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_PING | CFG_CMD_I2C ) | CFG_CMD_I2C ) & \
#else ~(CFG_CMD_ENV | CFG_CMD_LOADS ))
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C )
#endif
#endif #endif
#else
#if defined(CONFIG_PCI)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PCI \
| CFG_CMD_PING | CFG_CMD_I2C )
#else
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING | CFG_CMD_I2C )
#endif
#endif
#include <cmd_confdefs.h> #include <cmd_confdefs.h>
#undef CONFIG_WATCHDOG /* watchdog disabled */ #undef CONFIG_WATCHDOG /* watchdog disabled */

13
include/mpc83xx.h
View File

@ -53,10 +53,10 @@
/* /*
* Watchdog * Watchdog
*/ */
#define SWCRR 0x0204 #define SWCRR 0x0204
#define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */ #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
#define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */ #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
#define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */ #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit. */
#define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */ #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
#define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR) #define SWCRR_RES ~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
@ -172,7 +172,7 @@
/* /*
* Hard Reset Configration Word - High * Hard Reset Configration Word - High
*/ */
#define HRCWH_PCI_AGENT 0x00000000 #define HRCWH_PCI_AGENT 0x00000000
#define HRCWH_PCI_HOST 0x80000000 #define HRCWH_PCI_HOST 0x80000000
@ -195,8 +195,8 @@
#define HRCWH_BOOTSEQ_NORMAL 0x01000000 #define HRCWH_BOOTSEQ_NORMAL 0x01000000
#define HRCWH_BOOTSEQ_EXTENDED 0x02000000 #define HRCWH_BOOTSEQ_EXTENDED 0x02000000
#define HRCWH_SW_WATCHDOG_DISABLE 0x00000000 #define HRCWH_SW_WATCHDOG_DISABLE 0x00000000
#define HRCWH_SW_WATCHDOG_ENABLE 0x00800000 #define HRCWH_SW_WATCHDOG_ENABLE 0x00800000
#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000 #define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
#define HRCWH_ROM_LOC_PCI1 0x00100000 #define HRCWH_ROM_LOC_PCI1 0x00100000
@ -257,7 +257,7 @@
#define HRCWL_CORE_TO_CSB_3X1 0x00060000 #define HRCWL_CORE_TO_CSB_3X1 0x00060000
/* /*
* LCRR - Clock Ratio Register (10.3.1.16) * LCRR - Clock Ratio Register (10.3.1.16)
*/ */
#define LCRR_DBYP 0x80000000 #define LCRR_DBYP 0x80000000
#define LCRR_DBYP_SHIFT 31 #define LCRR_DBYP_SHIFT 31
@ -284,6 +284,5 @@
#define LCRR_CLKDIV_4 0x00000004 #define LCRR_CLKDIV_4 0x00000004
#define LCRR_CLKDIV_8 0x00000008 #define LCRR_CLKDIV_8 0x00000008
#define LCRR_CLKDIV_SHIFT 0 #define LCRR_CLKDIV_SHIFT 0
#endif /* __MPC83XX_H__ */ #endif /* __MPC83XX_H__ */

2
include/spd.h
View File

@ -103,6 +103,4 @@ typedef struct spd_eeprom_s {
#define SPD_MEMTYPE_DDR (0x07) #define SPD_MEMTYPE_DDR (0x07)
#define SPD_MEMTYPE_DDR2 (0x08) #define SPD_MEMTYPE_DDR2 (0x08)
#endif /* _SPD_H_ */ #endif /* _SPD_H_ */