CCM: remove code for yet another corpse
The CCM board has long reached EOL, and support for it is no longer relevant in current versions of U-Boot. Remove it. Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
Wolfgang Denk
parent
544d97e9aa
commit
dff07e18e5
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@ -207,8 +207,6 @@ Wolfgang Grandegger <wg@denx.de>
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ipek01 MPC5200
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ipek01 MPC5200
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CCM MPC855
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PN62 MPC8240
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PN62 MPC8240
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IPHASE4539 MPC8260
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IPHASE4539 MPC8260
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SCM MPC8260
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SCM MPC8260
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@ -1,56 +0,0 @@
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#
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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ifneq ($(OBJTREE),$(SRCTREE))
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$(shell mkdir -p $(obj)../common)
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$(shell mkdir -p $(obj)../../tqc/tqm8xx)
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endif
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LIB = $(obj)lib$(BOARD).a
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COBJS = ccm.o flash.o fpga_ccm.o ../common/fpga.o \
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../../tqc/tqm8xx/load_sernum_ethaddr.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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@ -1,408 +0,0 @@
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/*
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* (C) Copyright 2001
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc8xx.h>
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#include <commproc.h>
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#include <command.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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void can_driver_enable (void);
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void can_driver_disable (void);
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int fpga_init(void);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] =
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{
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
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0x1FF5FC47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
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0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0x7FFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*
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* Always return 1 (no second DRAM bank since based on TQM8xxL module)
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*/
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int checkboard (void)
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{
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unsigned char *s;
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unsigned char buf[64];
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s = (getenv_f("serial#", (char *)&buf, sizeof(buf)) > 0) ? buf : NULL;
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puts ("Board: Siemens CCM");
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if (s) {
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puts (" (");
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for (; *s; ++s) {
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if (*s == ' ')
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break;
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putc (*s);
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}
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putc (')');
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}
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putc ('\n');
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* If Power-On-Reset switch off the Red and Green LED: At reset, the
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* data direction registers are cleared and must therefore be restored.
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*/
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#define RSR_CSRS 0x08000000
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int power_on_reset(void)
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{
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/* Test Reset Status Register */
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return ((volatile immap_t *)CONFIG_SYS_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1;
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}
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#define PB_LED_GREEN 0x10000 /* red LED is on PB.15 */
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#define PB_LED_RED 0x20000 /* red LED is on PB.14 */
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#define PB_LEDS (PB_LED_GREEN | PB_LED_RED);
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static void init_leds (void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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immap->im_cpm.cp_pbpar &= ~PB_LEDS;
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immap->im_cpm.cp_pbodr &= ~PB_LEDS;
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immap->im_cpm.cp_pbdir |= PB_LEDS;
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/* Check stop reset status */
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if (power_on_reset()) {
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immap->im_cpm.cp_pbdat &= ~PB_LEDS;
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}
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size8, size9;
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long int size = 0;
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unsigned long reg;
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upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
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* preliminary addresses - these have to be modified after the
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* SDRAM size has been determined.
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*/
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memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
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memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
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memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
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udelay(200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
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udelay(1);
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memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
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udelay(1);
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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* try 8 column mode
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*/
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size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
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udelay (1000);
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/*
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* try 9 column mode
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*/
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size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
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if (size8 < size9) { /* leave configuration at 9 columns */
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size = size9;
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/* debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20); */
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} else { /* back to 8 columns */
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size = size8;
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memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
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udelay(500);
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/* debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20); */
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}
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udelay (1000);
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/*
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* Adjust refresh rate depending on SDRAM type
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* For types > 128 MBit leave it at the current (fast) rate
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*/
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if (size < 0x02000000) {
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/* reduce to 15.6 us (62.4 us / quad) */
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memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
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udelay(1000);
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}
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/*
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* Final mapping
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*/
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memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
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memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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/* adjust refresh rate depending on SDRAM type, one bank */
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reg = memctl->memc_mptpr;
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reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
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memctl->memc_mptpr = reg;
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can_driver_enable ();
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init_leds ();
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udelay(10000);
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return (size);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Warning - both the PUMA load mode and the CAN driver use UPM B,
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* so make sure only one of both is active.
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*/
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void can_driver_enable (void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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/* Initialize MBMR */
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memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
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/* Initialize UPMB for CAN: single read */
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memctl->memc_mdr = 0xFFFFC004;
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memctl->memc_mcr = 0x0100 | UPMB;
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memctl->memc_mdr = 0x0FFFD004;
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memctl->memc_mcr = 0x0101 | UPMB;
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memctl->memc_mdr = 0x0FFFC000;
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memctl->memc_mcr = 0x0102 | UPMB;
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memctl->memc_mdr = 0x3FFFC004;
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memctl->memc_mcr = 0x0103 | UPMB;
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memctl->memc_mdr = 0xFFFFDC05;
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memctl->memc_mcr = 0x0104 | UPMB;
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/* Initialize UPMB for CAN: single write */
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memctl->memc_mdr = 0xFFFCC004;
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memctl->memc_mcr = 0x0118 | UPMB;
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memctl->memc_mdr = 0xCFFCD004;
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memctl->memc_mcr = 0x0119 | UPMB;
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memctl->memc_mdr = 0x0FFCC000;
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memctl->memc_mcr = 0x011A | UPMB;
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memctl->memc_mdr = 0x7FFCC004;
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memctl->memc_mcr = 0x011B | UPMB;
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memctl->memc_mdr = 0xFFFDCC05;
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memctl->memc_mcr = 0x011C | UPMB;
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/* Initialize OR3 / BR3 for CAN Bus Controller */
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memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
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memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
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}
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void can_driver_disable (void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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|
||||||
/* Reset OR3 / BR3 to disable CAN Bus Controller */
|
|
||||||
memctl->memc_br3 = 0;
|
|
||||||
memctl->memc_or3 = 0;
|
|
||||||
|
|
||||||
memctl->memc_mbmr = 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Check memory range for valid RAM. A simple memory test determines
|
|
||||||
* the actually available RAM size between addresses `base' and
|
|
||||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
|
||||||
* - short between address lines
|
|
||||||
* - short between data lines
|
|
||||||
*/
|
|
||||||
|
|
||||||
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
|
|
||||||
{
|
|
||||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
|
||||||
|
|
||||||
return (get_ram_size(base, maxsize));
|
|
||||||
}
|
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
#define ETH_CFG_BITS (CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2 | CONFIG_SYS_PB_ETH_CFG3 )
|
|
||||||
|
|
||||||
#define ETH_ALL_BITS (ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN)
|
|
||||||
|
|
||||||
void reset_phy(void)
|
|
||||||
{
|
|
||||||
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
|
|
||||||
ulong value;
|
|
||||||
|
|
||||||
/* Configure all needed port pins for GPIO */
|
|
||||||
#ifdef CONFIG_SYS_ETH_MDDIS_VALUE
|
|
||||||
immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS;
|
|
||||||
#else
|
|
||||||
immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* Set low */
|
|
||||||
#endif
|
|
||||||
immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* GPIO */
|
|
||||||
immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET); /* active output */
|
|
||||||
immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET; /* output */
|
|
||||||
|
|
||||||
immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS); /* GPIO */
|
|
||||||
immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS); /* active output */
|
|
||||||
|
|
||||||
value = immr->im_cpm.cp_pbdat;
|
|
||||||
|
|
||||||
/* Assert Powerdown and Reset signals */
|
|
||||||
value |= CONFIG_SYS_PB_ETH_POWERDOWN;
|
|
||||||
|
|
||||||
/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
|
|
||||||
#ifdef CONFIG_SYS_ETH_CFG1_VALUE
|
|
||||||
value |= CONFIG_SYS_PB_ETH_CFG1;
|
|
||||||
#else
|
|
||||||
value &= ~(CONFIG_SYS_PB_ETH_CFG1);
|
|
||||||
#endif
|
|
||||||
#ifdef CONFIG_SYS_ETH_CFG2_VALUE
|
|
||||||
value |= CONFIG_SYS_PB_ETH_CFG2;
|
|
||||||
#else
|
|
||||||
value &= ~(CONFIG_SYS_PB_ETH_CFG2);
|
|
||||||
#endif
|
|
||||||
#ifdef CONFIG_SYS_ETH_CFG3_VALUE
|
|
||||||
value |= CONFIG_SYS_PB_ETH_CFG3;
|
|
||||||
#else
|
|
||||||
value &= ~(CONFIG_SYS_PB_ETH_CFG3);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* Drive output signals to initial state */
|
|
||||||
immr->im_cpm.cp_pbdat = value;
|
|
||||||
immr->im_cpm.cp_pbdir |= ETH_ALL_BITS;
|
|
||||||
udelay (10000);
|
|
||||||
|
|
||||||
/* De-assert Ethernet Powerdown */
|
|
||||||
immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
|
|
||||||
udelay (10000);
|
|
||||||
|
|
||||||
/* de-assert RESET signal of PHY */
|
|
||||||
immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_RESET;
|
|
||||||
udelay (1000);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
int misc_init_r (void)
|
|
||||||
{
|
|
||||||
fpga_init();
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
/* ------------------------------------------------------------------------- */
|
|
||||||
|
|
@ -1,28 +0,0 @@
|
||||||
#
|
|
||||||
# (C) Copyright 2001
|
|
||||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
#
|
|
||||||
# See file CREDITS for list of people who contributed to this
|
|
||||||
# project.
|
|
||||||
#
|
|
||||||
# This program is free software; you can redistribute it and/or
|
|
||||||
# modify it under the terms of the GNU General Public License as
|
|
||||||
# published by the Free Software Foundation; either version 2 of
|
|
||||||
# the License, or (at your option) any later version.
|
|
||||||
#
|
|
||||||
# This program is distributed in the hope that it will be useful,
|
|
||||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
# GNU General Public License for more details.
|
|
||||||
#
|
|
||||||
# You should have received a copy of the GNU General Public License
|
|
||||||
# along with this program; if not, write to the Free Software
|
|
||||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
# MA 02111-1307 USA
|
|
||||||
#
|
|
||||||
|
|
||||||
#
|
|
||||||
# TQM8xxL boards
|
|
||||||
#
|
|
||||||
|
|
||||||
TEXT_BASE = 0x40000000
|
|
||||||
|
|
@ -1,553 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2001
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <mpc8xx.h>
|
|
||||||
|
|
||||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Functions
|
|
||||||
*/
|
|
||||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
|
|
||||||
static int write_word (flash_info_t *info, ulong dest, ulong data);
|
|
||||||
static void flash_get_offsets (ulong base, flash_info_t *info);
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
unsigned long flash_init (void)
|
|
||||||
{
|
|
||||||
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
|
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
|
||||||
unsigned long size_b0, size_b1;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
/* Init: no FLASHes known */
|
|
||||||
for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
|
|
||||||
flash_info[i].flash_id = FLASH_UNKNOWN;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Static FLASH Bank configuration here - FIXME XXX */
|
|
||||||
|
|
||||||
size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
|
|
||||||
|
|
||||||
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
|
|
||||||
printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
|
|
||||||
size_b0, size_b0<<20);
|
|
||||||
}
|
|
||||||
|
|
||||||
size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
|
|
||||||
|
|
||||||
if (size_b1 > size_b0) {
|
|
||||||
printf ("## ERROR: "
|
|
||||||
"Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",
|
|
||||||
size_b1, size_b1<<20,
|
|
||||||
size_b0, size_b0<<20
|
|
||||||
);
|
|
||||||
flash_info[0].flash_id = FLASH_UNKNOWN;
|
|
||||||
flash_info[1].flash_id = FLASH_UNKNOWN;
|
|
||||||
flash_info[0].sector_count = -1;
|
|
||||||
flash_info[1].sector_count = -1;
|
|
||||||
flash_info[0].size = 0;
|
|
||||||
flash_info[1].size = 0;
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Remap FLASH according to real size */
|
|
||||||
memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
|
|
||||||
memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
|
|
||||||
|
|
||||||
/* Re-do sizing to get full correct info */
|
|
||||||
size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
|
|
||||||
|
|
||||||
flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
|
|
||||||
|
|
||||||
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
|
|
||||||
/* monitor protection ON by default */
|
|
||||||
flash_protect(FLAG_PROTECT_SET,
|
|
||||||
CONFIG_SYS_MONITOR_BASE,
|
|
||||||
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
|
|
||||||
&flash_info[0]);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
if (size_b1) {
|
|
||||||
memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
|
|
||||||
memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
|
|
||||||
BR_MS_GPCM | BR_V;
|
|
||||||
|
|
||||||
/* Re-do sizing to get full correct info */
|
|
||||||
size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
|
|
||||||
&flash_info[1]);
|
|
||||||
|
|
||||||
flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
|
|
||||||
|
|
||||||
#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
|
|
||||||
/* monitor protection ON by default */
|
|
||||||
flash_protect(FLAG_PROTECT_SET,
|
|
||||||
CONFIG_SYS_MONITOR_BASE,
|
|
||||||
CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
|
|
||||||
&flash_info[1]);
|
|
||||||
#endif
|
|
||||||
} else {
|
|
||||||
memctl->memc_br1 = 0; /* invalidate bank */
|
|
||||||
|
|
||||||
flash_info[1].flash_id = FLASH_UNKNOWN;
|
|
||||||
flash_info[1].sector_count = -1;
|
|
||||||
}
|
|
||||||
|
|
||||||
flash_info[0].size = size_b0;
|
|
||||||
flash_info[1].size = size_b1;
|
|
||||||
|
|
||||||
return (size_b0 + size_b1);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
static void flash_get_offsets (ulong base, flash_info_t *info)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
|
|
||||||
/* set up sector start address table */
|
|
||||||
if (info->flash_id & FLASH_BTYPE) {
|
|
||||||
/* set sector offsets for bottom boot block type */
|
|
||||||
info->start[0] = base + 0x00000000;
|
|
||||||
info->start[1] = base + 0x00008000;
|
|
||||||
info->start[2] = base + 0x0000C000;
|
|
||||||
info->start[3] = base + 0x00010000;
|
|
||||||
for (i = 4; i < info->sector_count; i++) {
|
|
||||||
info->start[i] = base + (i * 0x00020000) - 0x00060000;
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
/* set sector offsets for top boot block type */
|
|
||||||
i = info->sector_count - 1;
|
|
||||||
info->start[i--] = base + info->size - 0x00008000;
|
|
||||||
info->start[i--] = base + info->size - 0x0000C000;
|
|
||||||
info->start[i--] = base + info->size - 0x00010000;
|
|
||||||
for (; i >= 0; i--) {
|
|
||||||
info->start[i] = base + i * 0x00020000;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
void flash_print_info (flash_info_t *info)
|
|
||||||
{
|
|
||||||
int i;
|
|
||||||
|
|
||||||
if (info->flash_id == FLASH_UNKNOWN) {
|
|
||||||
printf ("missing or unknown FLASH type\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
switch (info->flash_id & FLASH_VENDMASK) {
|
|
||||||
case FLASH_MAN_AMD: printf ("AMD "); break;
|
|
||||||
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
|
|
||||||
default: printf ("Unknown Vendor "); break;
|
|
||||||
}
|
|
||||||
|
|
||||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
|
||||||
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
|
|
||||||
break;
|
|
||||||
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
|
|
||||||
break;
|
|
||||||
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
|
|
||||||
break;
|
|
||||||
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
|
|
||||||
break;
|
|
||||||
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
|
|
||||||
break;
|
|
||||||
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
|
|
||||||
break;
|
|
||||||
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
|
|
||||||
break;
|
|
||||||
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
|
|
||||||
break;
|
|
||||||
default: printf ("Unknown Chip Type\n");
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
printf (" Size: %ld MB in %d Sectors\n",
|
|
||||||
info->size >> 20, info->sector_count);
|
|
||||||
|
|
||||||
printf (" Sector Start Addresses:");
|
|
||||||
for (i=0; i<info->sector_count; ++i) {
|
|
||||||
if ((i % 5) == 0)
|
|
||||||
printf ("\n ");
|
|
||||||
printf (" %08lX%s",
|
|
||||||
info->start[i],
|
|
||||||
info->protect[i] ? " (RO)" : " "
|
|
||||||
);
|
|
||||||
}
|
|
||||||
printf ("\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The following code cannot be run from FLASH!
|
|
||||||
*/
|
|
||||||
|
|
||||||
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
|
|
||||||
{
|
|
||||||
short i;
|
|
||||||
ulong value;
|
|
||||||
ulong base = (ulong)addr;
|
|
||||||
|
|
||||||
|
|
||||||
/* Write auto select command: read Manufacturer ID */
|
|
||||||
addr[0x0555] = 0x00AA00AA;
|
|
||||||
addr[0x02AA] = 0x00550055;
|
|
||||||
addr[0x0555] = 0x00900090;
|
|
||||||
|
|
||||||
value = addr[0];
|
|
||||||
|
|
||||||
switch (value) {
|
|
||||||
case AMD_MANUFACT:
|
|
||||||
info->flash_id = FLASH_MAN_AMD;
|
|
||||||
break;
|
|
||||||
case FUJ_MANUFACT:
|
|
||||||
info->flash_id = FLASH_MAN_FUJ;
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
info->flash_id = FLASH_UNKNOWN;
|
|
||||||
info->sector_count = 0;
|
|
||||||
info->size = 0;
|
|
||||||
return (0); /* no or unknown flash */
|
|
||||||
}
|
|
||||||
|
|
||||||
value = addr[1]; /* device ID */
|
|
||||||
|
|
||||||
switch (value) {
|
|
||||||
case AMD_ID_LV400T:
|
|
||||||
info->flash_id += FLASH_AM400T;
|
|
||||||
info->sector_count = 11;
|
|
||||||
info->size = 0x00100000;
|
|
||||||
break; /* => 1 MB */
|
|
||||||
|
|
||||||
case AMD_ID_LV400B:
|
|
||||||
info->flash_id += FLASH_AM400B;
|
|
||||||
info->sector_count = 11;
|
|
||||||
info->size = 0x00100000;
|
|
||||||
break; /* => 1 MB */
|
|
||||||
|
|
||||||
case AMD_ID_LV800T:
|
|
||||||
info->flash_id += FLASH_AM800T;
|
|
||||||
info->sector_count = 19;
|
|
||||||
info->size = 0x00200000;
|
|
||||||
break; /* => 2 MB */
|
|
||||||
|
|
||||||
case AMD_ID_LV800B:
|
|
||||||
info->flash_id += FLASH_AM800B;
|
|
||||||
info->sector_count = 19;
|
|
||||||
info->size = 0x00200000;
|
|
||||||
break; /* => 2 MB */
|
|
||||||
|
|
||||||
case AMD_ID_LV160T:
|
|
||||||
info->flash_id += FLASH_AM160T;
|
|
||||||
info->sector_count = 35;
|
|
||||||
info->size = 0x00400000;
|
|
||||||
break; /* => 4 MB */
|
|
||||||
|
|
||||||
case AMD_ID_LV160B:
|
|
||||||
info->flash_id += FLASH_AM160B;
|
|
||||||
info->sector_count = 35;
|
|
||||||
info->size = 0x00400000;
|
|
||||||
break; /* => 4 MB */
|
|
||||||
#if 0 /* enable when device IDs are available */
|
|
||||||
case AMD_ID_LV320T:
|
|
||||||
info->flash_id += FLASH_AM320T;
|
|
||||||
info->sector_count = 67;
|
|
||||||
info->size = 0x00800000;
|
|
||||||
break; /* => 8 MB */
|
|
||||||
|
|
||||||
case AMD_ID_LV320B:
|
|
||||||
info->flash_id += FLASH_AM320B;
|
|
||||||
info->sector_count = 67;
|
|
||||||
info->size = 0x00800000;
|
|
||||||
break; /* => 8 MB */
|
|
||||||
#endif
|
|
||||||
default:
|
|
||||||
info->flash_id = FLASH_UNKNOWN;
|
|
||||||
return (0); /* => no or unknown flash */
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
/* set up sector start address table */
|
|
||||||
if (info->flash_id & FLASH_BTYPE) {
|
|
||||||
/* set sector offsets for bottom boot block type */
|
|
||||||
info->start[0] = base + 0x00000000;
|
|
||||||
info->start[1] = base + 0x00008000;
|
|
||||||
info->start[2] = base + 0x0000C000;
|
|
||||||
info->start[3] = base + 0x00010000;
|
|
||||||
for (i = 4; i < info->sector_count; i++) {
|
|
||||||
info->start[i] = base + (i * 0x00020000) - 0x00060000;
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
/* set sector offsets for top boot block type */
|
|
||||||
i = info->sector_count - 1;
|
|
||||||
info->start[i--] = base + info->size - 0x00008000;
|
|
||||||
info->start[i--] = base + info->size - 0x0000C000;
|
|
||||||
info->start[i--] = base + info->size - 0x00010000;
|
|
||||||
for (; i >= 0; i--) {
|
|
||||||
info->start[i] = base + i * 0x00020000;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* check for protected sectors */
|
|
||||||
for (i = 0; i < info->sector_count; i++) {
|
|
||||||
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
|
|
||||||
/* D0 = 1 if protected */
|
|
||||||
addr = (volatile unsigned long *)(info->start[i]);
|
|
||||||
info->protect[i] = addr[2] & 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Prevent writes to uninitialized FLASH.
|
|
||||||
*/
|
|
||||||
if (info->flash_id != FLASH_UNKNOWN) {
|
|
||||||
addr = (volatile unsigned long *)info->start[0];
|
|
||||||
|
|
||||||
*addr = 0x00F000F0; /* reset bank */
|
|
||||||
}
|
|
||||||
|
|
||||||
return (info->size);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
||||||
int flash_erase (flash_info_t *info, int s_first, int s_last)
|
|
||||||
{
|
|
||||||
vu_long *addr = (vu_long*)(info->start[0]);
|
|
||||||
int flag, prot, sect, l_sect;
|
|
||||||
ulong start, now, last;
|
|
||||||
|
|
||||||
if ((s_first < 0) || (s_first > s_last)) {
|
|
||||||
if (info->flash_id == FLASH_UNKNOWN) {
|
|
||||||
printf ("- missing\n");
|
|
||||||
} else {
|
|
||||||
printf ("- no sectors to erase\n");
|
|
||||||
}
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
if ((info->flash_id == FLASH_UNKNOWN) ||
|
|
||||||
(info->flash_id > FLASH_AMD_COMP)) {
|
|
||||||
printf ("Can't erase unknown flash type %08lx - aborted\n",
|
|
||||||
info->flash_id);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
prot = 0;
|
|
||||||
for (sect=s_first; sect<=s_last; ++sect) {
|
|
||||||
if (info->protect[sect]) {
|
|
||||||
prot++;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
if (prot) {
|
|
||||||
printf ("- Warning: %d protected sectors will not be erased!\n",
|
|
||||||
prot);
|
|
||||||
} else {
|
|
||||||
printf ("\n");
|
|
||||||
}
|
|
||||||
|
|
||||||
l_sect = -1;
|
|
||||||
|
|
||||||
/* Disable interrupts which might cause a timeout here */
|
|
||||||
flag = disable_interrupts();
|
|
||||||
|
|
||||||
addr[0x0555] = 0x00AA00AA;
|
|
||||||
addr[0x02AA] = 0x00550055;
|
|
||||||
addr[0x0555] = 0x00800080;
|
|
||||||
addr[0x0555] = 0x00AA00AA;
|
|
||||||
addr[0x02AA] = 0x00550055;
|
|
||||||
|
|
||||||
/* Start erase on unprotected sectors */
|
|
||||||
for (sect = s_first; sect<=s_last; sect++) {
|
|
||||||
if (info->protect[sect] == 0) { /* not protected */
|
|
||||||
addr = (vu_long*)(info->start[sect]);
|
|
||||||
addr[0] = 0x00300030;
|
|
||||||
l_sect = sect;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/* re-enable interrupts if necessary */
|
|
||||||
if (flag)
|
|
||||||
enable_interrupts();
|
|
||||||
|
|
||||||
/* wait at least 80us - let's wait 1 ms */
|
|
||||||
udelay (1000);
|
|
||||||
|
|
||||||
/*
|
|
||||||
* We wait for the last triggered sector
|
|
||||||
*/
|
|
||||||
if (l_sect < 0)
|
|
||||||
goto DONE;
|
|
||||||
|
|
||||||
start = get_timer (0);
|
|
||||||
last = start;
|
|
||||||
addr = (vu_long*)(info->start[l_sect]);
|
|
||||||
while ((addr[0] & 0x00800080) != 0x00800080) {
|
|
||||||
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
|
||||||
printf ("Timeout\n");
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
/* show that we're waiting */
|
|
||||||
if ((now - last) > 1000) { /* every second */
|
|
||||||
putc ('.');
|
|
||||||
last = now;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
DONE:
|
|
||||||
/* reset to read mode */
|
|
||||||
addr = (volatile unsigned long *)info->start[0];
|
|
||||||
addr[0] = 0x00F000F0; /* reset bank */
|
|
||||||
|
|
||||||
printf (" done\n");
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Copy memory to flash, returns:
|
|
||||||
* 0 - OK
|
|
||||||
* 1 - write timeout
|
|
||||||
* 2 - Flash not erased
|
|
||||||
*/
|
|
||||||
|
|
||||||
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
|
|
||||||
{
|
|
||||||
ulong cp, wp, data;
|
|
||||||
int i, l, rc;
|
|
||||||
|
|
||||||
wp = (addr & ~3); /* get lower word aligned address */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* handle unaligned start bytes
|
|
||||||
*/
|
|
||||||
if ((l = addr - wp) != 0) {
|
|
||||||
data = 0;
|
|
||||||
for (i=0, cp=wp; i<l; ++i, ++cp) {
|
|
||||||
data = (data << 8) | (*(uchar *)cp);
|
|
||||||
}
|
|
||||||
for (; i<4 && cnt>0; ++i) {
|
|
||||||
data = (data << 8) | *src++;
|
|
||||||
--cnt;
|
|
||||||
++cp;
|
|
||||||
}
|
|
||||||
for (; cnt==0 && i<4; ++i, ++cp) {
|
|
||||||
data = (data << 8) | (*(uchar *)cp);
|
|
||||||
}
|
|
||||||
|
|
||||||
if ((rc = write_word(info, wp, data)) != 0) {
|
|
||||||
return (rc);
|
|
||||||
}
|
|
||||||
wp += 4;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* handle word aligned part
|
|
||||||
*/
|
|
||||||
while (cnt >= 4) {
|
|
||||||
data = 0;
|
|
||||||
for (i=0; i<4; ++i) {
|
|
||||||
data = (data << 8) | *src++;
|
|
||||||
}
|
|
||||||
if ((rc = write_word(info, wp, data)) != 0) {
|
|
||||||
return (rc);
|
|
||||||
}
|
|
||||||
wp += 4;
|
|
||||||
cnt -= 4;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (cnt == 0) {
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* handle unaligned tail bytes
|
|
||||||
*/
|
|
||||||
data = 0;
|
|
||||||
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
|
|
||||||
data = (data << 8) | *src++;
|
|
||||||
--cnt;
|
|
||||||
}
|
|
||||||
for (; i<4; ++i, ++cp) {
|
|
||||||
data = (data << 8) | (*(uchar *)cp);
|
|
||||||
}
|
|
||||||
|
|
||||||
return (write_word(info, wp, data));
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Write a word to Flash, returns:
|
|
||||||
* 0 - OK
|
|
||||||
* 1 - write timeout
|
|
||||||
* 2 - Flash not erased
|
|
||||||
*/
|
|
||||||
static int write_word (flash_info_t *info, ulong dest, ulong data)
|
|
||||||
{
|
|
||||||
vu_long *addr = (vu_long*)(info->start[0]);
|
|
||||||
ulong start;
|
|
||||||
int flag;
|
|
||||||
|
|
||||||
/* Check if Flash is (sufficiently) erased */
|
|
||||||
if ((*((vu_long *)dest) & data) != data) {
|
|
||||||
return (2);
|
|
||||||
}
|
|
||||||
/* Disable interrupts which might cause a timeout here */
|
|
||||||
flag = disable_interrupts();
|
|
||||||
|
|
||||||
addr[0x0555] = 0x00AA00AA;
|
|
||||||
addr[0x02AA] = 0x00550055;
|
|
||||||
addr[0x0555] = 0x00A000A0;
|
|
||||||
|
|
||||||
*((vu_long *)dest) = data;
|
|
||||||
|
|
||||||
/* re-enable interrupts if necessary */
|
|
||||||
if (flag)
|
|
||||||
enable_interrupts();
|
|
||||||
|
|
||||||
/* data polling for D7 */
|
|
||||||
start = get_timer (0);
|
|
||||||
while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
|
|
||||||
if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
|
|
||||||
return (1);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
|
|
@ -1,169 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2002
|
|
||||||
* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <mpc8xx.h>
|
|
||||||
#include <commproc.h>
|
|
||||||
#include <common.h>
|
|
||||||
|
|
||||||
#include "../common/fpga.h"
|
|
||||||
|
|
||||||
fpga_t fpga_list[] = {
|
|
||||||
{ "PUMA" , PUMA_CONF_BASE ,
|
|
||||||
CONFIG_SYS_PC_PUMA_INIT , CONFIG_SYS_PC_PUMA_PROG , CONFIG_SYS_PC_PUMA_DONE }
|
|
||||||
};
|
|
||||||
int fpga_count = sizeof(fpga_list) / sizeof(fpga_t);
|
|
||||||
|
|
||||||
void can_driver_enable (void);
|
|
||||||
void can_driver_disable (void);
|
|
||||||
|
|
||||||
#define _NOT_USED_ 0xFFFFFFFF
|
|
||||||
|
|
||||||
/*
|
|
||||||
* PUMA access using UPM B
|
|
||||||
*/
|
|
||||||
const uint puma_table[] =
|
|
||||||
{
|
|
||||||
/*
|
|
||||||
* Single Read. (Offset 0 in UPM RAM)
|
|
||||||
*/
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_,
|
|
||||||
/*
|
|
||||||
* Precharge and MRS
|
|
||||||
*/
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
/*
|
|
||||||
* Burst Read. (Offset 8 in UPM RAM)
|
|
||||||
*/
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
/*
|
|
||||||
* Single Write. (Offset 18 in UPM RAM)
|
|
||||||
*/
|
|
||||||
0x0FFCF804, 0x0FFCF400, 0x3FFDFC47, /* last */
|
|
||||||
_NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
/*
|
|
||||||
* Burst Write. (Offset 20 in UPM RAM)
|
|
||||||
*/
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
/*
|
|
||||||
* Refresh (Offset 30 in UPM RAM)
|
|
||||||
*/
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
/*
|
|
||||||
* Exception. (Offset 3c in UPM RAM)
|
|
||||||
*/
|
|
||||||
0x7FFFFC07, /* last */
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
ulong fpga_control (fpga_t* fpga, int cmd)
|
|
||||||
{
|
|
||||||
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
|
|
||||||
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
|
||||||
|
|
||||||
switch (cmd) {
|
|
||||||
case FPGA_INIT_IS_HIGH:
|
|
||||||
immr->im_ioport.iop_pcdir &= ~fpga->init_mask; /* input */
|
|
||||||
return (immr->im_ioport.iop_pcdat & fpga->init_mask) ? 1:0;
|
|
||||||
|
|
||||||
case FPGA_INIT_SET_LOW:
|
|
||||||
immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */
|
|
||||||
immr->im_ioport.iop_pcdat &= ~fpga->init_mask;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case FPGA_INIT_SET_HIGH:
|
|
||||||
immr->im_ioport.iop_pcdir |= fpga->init_mask; /* output */
|
|
||||||
immr->im_ioport.iop_pcdat |= fpga->init_mask;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case FPGA_PROG_SET_LOW:
|
|
||||||
immr->im_ioport.iop_pcdat &= ~fpga->prog_mask;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case FPGA_PROG_SET_HIGH:
|
|
||||||
immr->im_ioport.iop_pcdat |= fpga->prog_mask;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case FPGA_DONE_IS_HIGH:
|
|
||||||
return (immr->im_ioport.iop_pcdat & fpga->done_mask) ? 1:0;
|
|
||||||
|
|
||||||
case FPGA_READ_MODE:
|
|
||||||
/* disable FPGA in memory controller */
|
|
||||||
memctl->memc_br4 = 0;
|
|
||||||
memctl->memc_or4 = PUMA_CONF_OR_READ;
|
|
||||||
memctl->memc_br4 = PUMA_CONF_BR_READ;
|
|
||||||
|
|
||||||
/* (re-) enable CAN drivers */
|
|
||||||
can_driver_enable ();
|
|
||||||
|
|
||||||
break;
|
|
||||||
|
|
||||||
case FPGA_LOAD_MODE:
|
|
||||||
/* disable FPGA in memory controller */
|
|
||||||
memctl->memc_br4 = 0;
|
|
||||||
/*
|
|
||||||
* We must disable the CAN drivers first because
|
|
||||||
* they use UPM B, too.
|
|
||||||
*/
|
|
||||||
can_driver_disable ();
|
|
||||||
/*
|
|
||||||
* Configure UPMB for FPGA
|
|
||||||
*/
|
|
||||||
upmconfig(UPMB,(uint *)puma_table,sizeof(puma_table)/sizeof(uint));
|
|
||||||
memctl->memc_or4 = PUMA_CONF_OR_LOAD;
|
|
||||||
memctl->memc_br4 = PUMA_CONF_BR_LOAD;
|
|
||||||
break;
|
|
||||||
|
|
||||||
case FPGA_GET_ID:
|
|
||||||
return *(volatile ulong *)fpga->conf_base;
|
|
||||||
|
|
||||||
case FPGA_INIT_PORTS:
|
|
||||||
immr->im_ioport.iop_pcpar &= ~fpga->init_mask; /* INIT I/O */
|
|
||||||
immr->im_ioport.iop_pcso &= ~fpga->init_mask;
|
|
||||||
immr->im_ioport.iop_pcdir &= ~fpga->init_mask;
|
|
||||||
|
|
||||||
immr->im_ioport.iop_pcpar &= ~fpga->prog_mask; /* PROG Output */
|
|
||||||
immr->im_ioport.iop_pcso &= ~fpga->prog_mask;
|
|
||||||
immr->im_ioport.iop_pcdir |= fpga->prog_mask;
|
|
||||||
|
|
||||||
immr->im_ioport.iop_pcpar &= ~fpga->done_mask; /* DONE Input */
|
|
||||||
immr->im_ioport.iop_pcso &= ~fpga->done_mask;
|
|
||||||
immr->im_ioport.iop_pcdir &= ~fpga->done_mask;
|
|
||||||
|
|
||||||
break;
|
|
||||||
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
@ -1,138 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2001
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
OUTPUT_ARCH(powerpc)
|
|
||||||
/* Do we need any of these for elf?
|
|
||||||
__DYNAMIC = 0; */
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
/* Read-only sections, merged into text segment: */
|
|
||||||
. = + SIZEOF_HEADERS;
|
|
||||||
.interp : { *(.interp) }
|
|
||||||
.hash : { *(.hash) }
|
|
||||||
.dynsym : { *(.dynsym) }
|
|
||||||
.dynstr : { *(.dynstr) }
|
|
||||||
.rel.text : { *(.rel.text) }
|
|
||||||
.rela.text : { *(.rela.text) }
|
|
||||||
.rel.data : { *(.rel.data) }
|
|
||||||
.rela.data : { *(.rela.data) }
|
|
||||||
.rel.rodata : { *(.rel.rodata) }
|
|
||||||
.rela.rodata : { *(.rela.rodata) }
|
|
||||||
.rel.got : { *(.rel.got) }
|
|
||||||
.rela.got : { *(.rela.got) }
|
|
||||||
.rel.ctors : { *(.rel.ctors) }
|
|
||||||
.rela.ctors : { *(.rela.ctors) }
|
|
||||||
.rel.dtors : { *(.rel.dtors) }
|
|
||||||
.rela.dtors : { *(.rela.dtors) }
|
|
||||||
.rel.bss : { *(.rel.bss) }
|
|
||||||
.rela.bss : { *(.rela.bss) }
|
|
||||||
.rel.plt : { *(.rel.plt) }
|
|
||||||
.rela.plt : { *(.rela.plt) }
|
|
||||||
.init : { *(.init) }
|
|
||||||
.plt : { *(.plt) }
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
/* WARNING - the following is hand-optimized to fit within */
|
|
||||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
|
||||||
|
|
||||||
arch/powerpc/cpu/mpc8xx/start.o (.text)
|
|
||||||
common/dlmalloc.o (.text)
|
|
||||||
arch/powerpc/lib/ppcstring.o (.text)
|
|
||||||
lib/vsprintf.o (.text)
|
|
||||||
lib/crc32.o (.text)
|
|
||||||
lib/zlib.o (.text)
|
|
||||||
|
|
||||||
. = env_offset;
|
|
||||||
common/env_embedded.o(.text)
|
|
||||||
|
|
||||||
*(.text)
|
|
||||||
*(.got1)
|
|
||||||
}
|
|
||||||
_etext = .;
|
|
||||||
PROVIDE (etext = .);
|
|
||||||
.rodata :
|
|
||||||
{
|
|
||||||
*(.eh_frame)
|
|
||||||
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
|
|
||||||
}
|
|
||||||
.fini : { *(.fini) } =0
|
|
||||||
.ctors : { *(.ctors) }
|
|
||||||
.dtors : { *(.dtors) }
|
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */
|
|
||||||
. = (. + 0x00FF) & 0xFFFFFF00;
|
|
||||||
_erotext = .;
|
|
||||||
PROVIDE (erotext = .);
|
|
||||||
.reloc :
|
|
||||||
{
|
|
||||||
*(.got)
|
|
||||||
_GOT2_TABLE_ = .;
|
|
||||||
*(.got2)
|
|
||||||
_FIXUP_TABLE_ = .;
|
|
||||||
*(.fixup)
|
|
||||||
}
|
|
||||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
|
||||||
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
*(.data)
|
|
||||||
*(.data1)
|
|
||||||
*(.sdata)
|
|
||||||
*(.sdata2)
|
|
||||||
*(.dynamic)
|
|
||||||
CONSTRUCTORS
|
|
||||||
}
|
|
||||||
_edata = .;
|
|
||||||
PROVIDE (edata = .);
|
|
||||||
|
|
||||||
. = .;
|
|
||||||
__u_boot_cmd_start = .;
|
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
|
||||||
__u_boot_cmd_end = .;
|
|
||||||
|
|
||||||
|
|
||||||
. = .;
|
|
||||||
__start___ex_table = .;
|
|
||||||
__ex_table : { *(__ex_table) }
|
|
||||||
__stop___ex_table = .;
|
|
||||||
|
|
||||||
. = ALIGN(256);
|
|
||||||
__init_begin = .;
|
|
||||||
.text.init : { *(.text.init) }
|
|
||||||
.data.init : { *(.data.init) }
|
|
||||||
. = ALIGN(256);
|
|
||||||
__init_end = .;
|
|
||||||
|
|
||||||
__bss_start = .;
|
|
||||||
.bss (NOLOAD) :
|
|
||||||
{
|
|
||||||
*(.sbss) *(.scommon)
|
|
||||||
*(.dynbss)
|
|
||||||
*(.bss)
|
|
||||||
*(COMMON)
|
|
||||||
. = ALIGN(4);
|
|
||||||
}
|
|
||||||
_end = . ;
|
|
||||||
PROVIDE (end = .);
|
|
||||||
}
|
|
||||||
|
|
@ -1,135 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2001
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
OUTPUT_ARCH(powerpc)
|
|
||||||
/* Do we need any of these for elf?
|
|
||||||
__DYNAMIC = 0; */
|
|
||||||
SECTIONS
|
|
||||||
{
|
|
||||||
/* Read-only sections, merged into text segment: */
|
|
||||||
. = + SIZEOF_HEADERS;
|
|
||||||
.interp : { *(.interp) }
|
|
||||||
.hash : { *(.hash) }
|
|
||||||
.dynsym : { *(.dynsym) }
|
|
||||||
.dynstr : { *(.dynstr) }
|
|
||||||
.rel.text : { *(.rel.text) }
|
|
||||||
.rela.text : { *(.rela.text) }
|
|
||||||
.rel.data : { *(.rel.data) }
|
|
||||||
.rela.data : { *(.rela.data) }
|
|
||||||
.rel.rodata : { *(.rel.rodata) }
|
|
||||||
.rela.rodata : { *(.rela.rodata) }
|
|
||||||
.rel.got : { *(.rel.got) }
|
|
||||||
.rela.got : { *(.rela.got) }
|
|
||||||
.rel.ctors : { *(.rel.ctors) }
|
|
||||||
.rela.ctors : { *(.rela.ctors) }
|
|
||||||
.rel.dtors : { *(.rel.dtors) }
|
|
||||||
.rela.dtors : { *(.rela.dtors) }
|
|
||||||
.rel.bss : { *(.rel.bss) }
|
|
||||||
.rela.bss : { *(.rela.bss) }
|
|
||||||
.rel.plt : { *(.rel.plt) }
|
|
||||||
.rela.plt : { *(.rela.plt) }
|
|
||||||
.init : { *(.init) }
|
|
||||||
.plt : { *(.plt) }
|
|
||||||
.text :
|
|
||||||
{
|
|
||||||
/* WARNING - the following is hand-optimized to fit within */
|
|
||||||
/* the sector layout of our flash chips! XXX FIXME XXX */
|
|
||||||
|
|
||||||
arch/powerpc/cpu/mpc8xx/start.o (.text)
|
|
||||||
common/dlmalloc.o (.text)
|
|
||||||
lib/vsprintf.o (.text)
|
|
||||||
lib/crc32.o (.text)
|
|
||||||
/*
|
|
||||||
. = env_offset;
|
|
||||||
common/env_embedded.o(.text)
|
|
||||||
*/
|
|
||||||
*(.text)
|
|
||||||
*(.got1)
|
|
||||||
}
|
|
||||||
_etext = .;
|
|
||||||
PROVIDE (etext = .);
|
|
||||||
.rodata :
|
|
||||||
{
|
|
||||||
*(.rodata)
|
|
||||||
*(.rodata1)
|
|
||||||
*(.rodata.str1.4)
|
|
||||||
*(.eh_frame)
|
|
||||||
}
|
|
||||||
.fini : { *(.fini) } =0
|
|
||||||
.ctors : { *(.ctors) }
|
|
||||||
.dtors : { *(.dtors) }
|
|
||||||
|
|
||||||
/* Read-write section, merged into data segment: */
|
|
||||||
. = (. + 0x0FFF) & 0xFFFFF000;
|
|
||||||
_erotext = .;
|
|
||||||
PROVIDE (erotext = .);
|
|
||||||
.reloc :
|
|
||||||
{
|
|
||||||
*(.got)
|
|
||||||
_GOT2_TABLE_ = .;
|
|
||||||
*(.got2)
|
|
||||||
_FIXUP_TABLE_ = .;
|
|
||||||
*(.fixup)
|
|
||||||
}
|
|
||||||
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
|
||||||
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
|
||||||
|
|
||||||
.data :
|
|
||||||
{
|
|
||||||
*(.data)
|
|
||||||
*(.data1)
|
|
||||||
*(.sdata)
|
|
||||||
*(.sdata2)
|
|
||||||
*(.dynamic)
|
|
||||||
CONSTRUCTORS
|
|
||||||
}
|
|
||||||
_edata = .;
|
|
||||||
PROVIDE (edata = .);
|
|
||||||
|
|
||||||
__u_boot_cmd_start = .;
|
|
||||||
.u_boot_cmd : { *(.u_boot_cmd) }
|
|
||||||
__u_boot_cmd_end = .;
|
|
||||||
|
|
||||||
|
|
||||||
__start___ex_table = .;
|
|
||||||
__ex_table : { *(__ex_table) }
|
|
||||||
__stop___ex_table = .;
|
|
||||||
|
|
||||||
. = ALIGN(4096);
|
|
||||||
__init_begin = .;
|
|
||||||
.text.init : { *(.text.init) }
|
|
||||||
.data.init : { *(.data.init) }
|
|
||||||
. = ALIGN(4096);
|
|
||||||
__init_end = .;
|
|
||||||
|
|
||||||
__bss_start = .;
|
|
||||||
.bss :
|
|
||||||
{
|
|
||||||
*(.sbss) *(.scommon)
|
|
||||||
*(.dynbss)
|
|
||||||
*(.bss)
|
|
||||||
*(COMMON)
|
|
||||||
}
|
|
||||||
_end = . ;
|
|
||||||
PROVIDE (end = .);
|
|
||||||
}
|
|
||||||
|
|
@ -161,7 +161,6 @@ mgsuvd powerpc mpc8xx km8xx keymile
|
||||||
KUP4K powerpc mpc8xx kup4k kup
|
KUP4K powerpc mpc8xx kup4k kup
|
||||||
KUP4X powerpc mpc8xx kup4x kup
|
KUP4X powerpc mpc8xx kup4x kup
|
||||||
ELPT860 powerpc mpc8xx elpt860 LEOX
|
ELPT860 powerpc mpc8xx elpt860 LEOX
|
||||||
CCM powerpc mpc8xx - siemens
|
|
||||||
IAD210 powerpc mpc8xx - siemens
|
IAD210 powerpc mpc8xx - siemens
|
||||||
QS823 powerpc mpc8xx qs850 snmc
|
QS823 powerpc mpc8xx qs850 snmc
|
||||||
QS850 powerpc mpc8xx qs850 snmc
|
QS850 powerpc mpc8xx qs850 snmc
|
||||||
|
|
|
||||||
|
|
@ -579,34 +579,6 @@ typedef struct scc_enet {
|
||||||
|
|
||||||
/*********************************************************************/
|
/*********************************************************************/
|
||||||
|
|
||||||
|
|
||||||
/*** CCM ***********************************************************/
|
|
||||||
|
|
||||||
/* The CCM uses the FEC on a MPC860T for Ethernet */
|
|
||||||
|
|
||||||
#if defined(CONFIG_CCM)
|
|
||||||
|
|
||||||
#define FEC_ENET /* use FEC for EThernet */
|
|
||||||
#undef SCC_ENET
|
|
||||||
|
|
||||||
#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */
|
|
||||||
#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */
|
|
||||||
#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */
|
|
||||||
#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */
|
|
||||||
#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */
|
|
||||||
#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */
|
|
||||||
#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */
|
|
||||||
#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */
|
|
||||||
#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */
|
|
||||||
#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */
|
|
||||||
#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */
|
|
||||||
#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */
|
|
||||||
#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */
|
|
||||||
|
|
||||||
#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */
|
|
||||||
|
|
||||||
#endif /* CONFIG_CCM */
|
|
||||||
|
|
||||||
/*** ELPT860 *********************************************************/
|
/*** ELPT860 *********************************************************/
|
||||||
|
|
||||||
#ifdef CONFIG_ELPT860
|
#ifdef CONFIG_ELPT860
|
||||||
|
|
|
||||||
|
|
@ -1,488 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2001-2005
|
|
||||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
/*
|
|
||||||
* configuration options, board specific, for Siemens Card Controller Module
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
#undef CCM_80MHz /* define for 80 MHz CPU only */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* High Level Configuration Options
|
|
||||||
* (easy to change)
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_MPC860 1 /* This is a MPC860 CPU ... */
|
|
||||||
#define CONFIG_CCM 1 /* on a Card Controller Module */
|
|
||||||
#define CONFIG_MISC_INIT_R /* Call misc_init_r() */
|
|
||||||
#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
|
|
||||||
|
|
||||||
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
|
||||||
#undef CONFIG_8xx_CONS_SMC2
|
|
||||||
#undef CONFIG_8xx_CONS_NONE
|
|
||||||
|
|
||||||
/* ENVIRONMENT */
|
|
||||||
|
|
||||||
#define CONFIG_BAUDRATE 19200 /* console baudrate in bps */
|
|
||||||
#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
|
|
||||||
|
|
||||||
#define CONFIG_IPADDR 192.168.0.42
|
|
||||||
#define CONFIG_NETMASK 255.255.255.0
|
|
||||||
#define CONFIG_GATEWAYIP 0.0.0.0
|
|
||||||
#define CONFIG_SERVERIP 192.168.0.254
|
|
||||||
|
|
||||||
#define CONFIG_HOSTNAME CCM
|
|
||||||
|
|
||||||
#define CONFIG_LOADADDR 40180000
|
|
||||||
|
|
||||||
#undef CONFIG_BOOTARGS
|
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND "setenv bootargs " \
|
|
||||||
"mem=${mem} " \
|
|
||||||
"root=/dev/ram rw ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
|
|
||||||
"wt_8xx=timeout:3600; " \
|
|
||||||
"bootm"
|
|
||||||
|
|
||||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
|
||||||
#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
|
||||||
|
|
||||||
#define CONFIG_WATCHDOG 1 /* watchdog enabled */
|
|
||||||
|
|
||||||
#undef CONFIG_STATUS_LED /* Status LED disabled */
|
|
||||||
|
|
||||||
#define CONFIG_PRAM 512 /* reserve 512kB "protected RAM"*/
|
|
||||||
|
|
||||||
#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
|
|
||||||
|
|
||||||
#define CONFIG_SPI /* enable SPI driver */
|
|
||||||
#define CONFIG_SPI_X /* 16 bit EEPROM addressing */
|
|
||||||
|
|
||||||
/* ----------------------------------------------------------------
|
|
||||||
* Offset to initial SPI buffers in DPRAM (used if the environment
|
|
||||||
* is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
|
|
||||||
* use at an early stage. It is used between the two initialization
|
|
||||||
* calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
|
|
||||||
* far enough from the start of the data area (as well as from the
|
|
||||||
* stack pointer).
|
|
||||||
* ---------------------------------------------------------------- */
|
|
||||||
#define CONFIG_SYS_SPI_INIT_OFFSET 0xB00
|
|
||||||
|
|
||||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32-byte page size */
|
|
||||||
|
|
||||||
|
|
||||||
#define CONFIG_MAC_PARTITION /* nod used yet */
|
|
||||||
#define CONFIG_DOS_PARTITION
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BOOTP options
|
|
||||||
*/
|
|
||||||
#define CONFIG_BOOTP_SUBNETMASK
|
|
||||||
#define CONFIG_BOOTP_GATEWAY
|
|
||||||
#define CONFIG_BOOTP_HOSTNAME
|
|
||||||
#define CONFIG_BOOTP_BOOTPATH
|
|
||||||
#define CONFIG_BOOTP_BOOTFILESIZE
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Command line configuration.
|
|
||||||
*/
|
|
||||||
#include <config_cmd_default.h>
|
|
||||||
|
|
||||||
#define CONFIG_CMD_BSP
|
|
||||||
#define CONFIG_CMD_DHCP
|
|
||||||
#define CONFIG_CMD_DATE
|
|
||||||
#define CONFIG_CMD_EEPROM
|
|
||||||
#define CONFIG_CMD_NFS
|
|
||||||
#define CONFIG_CMD_SNTP
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
|
||||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
|
||||||
#if defined(CONFIG_CMD_KGDB)
|
|
||||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
|
||||||
#endif
|
|
||||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
|
||||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
|
||||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
|
|
||||||
#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
|
|
||||||
|
|
||||||
/* Ethernet hardware configuration done using port pins */
|
|
||||||
#define CONFIG_SYS_PA_ETH_RESET 0x0200 /* PA 6 */
|
|
||||||
#define CONFIG_SYS_PA_ETH_MDDIS 0x4000 /* PA 1 */
|
|
||||||
#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
|
|
||||||
#define CONFIG_SYS_PB_ETH_CFG1 0x00000400 /* PB 21 */
|
|
||||||
#define CONFIG_SYS_PB_ETH_CFG2 0x00000200 /* PB 22 */
|
|
||||||
#define CONFIG_SYS_PB_ETH_CFG3 0x00000100 /* PB 23 */
|
|
||||||
|
|
||||||
/* Ethernet settings:
|
|
||||||
* MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_ETH_MDDIS_VALUE 0
|
|
||||||
#define CONFIG_SYS_ETH_CFG1_VALUE 1
|
|
||||||
#define CONFIG_SYS_ETH_CFG2_VALUE 1
|
|
||||||
#define CONFIG_SYS_ETH_CFG3_VALUE 1
|
|
||||||
|
|
||||||
/* PUMA configuration */
|
|
||||||
#define CONFIG_SYS_PC_PUMA_PROG 0x0200 /* PC 6 */
|
|
||||||
#define CONFIG_SYS_PC_PUMA_DONE 0x0008 /* PC 12 */
|
|
||||||
#define CONFIG_SYS_PC_PUMA_INIT 0x0004 /* PC 13 */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Low Level Configuration Settings
|
|
||||||
* (address mappings, register initial values, etc.)
|
|
||||||
* You should know what you are doing if you make changes here.
|
|
||||||
*/
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Internal Memory Mapped Register
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_IMMR 0xF0000000
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
|
||||||
#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
|
|
||||||
#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Address accessed to reset the board - must not be mapped/assigned
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_RESET_ADDRESS 0xFEFFFFFF
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Start addresses for the final memory configuration
|
|
||||||
* (Set up by the startup code)
|
|
||||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
|
||||||
#define CONFIG_SYS_FLASH_BASE 0x40000000
|
|
||||||
#if defined(DEBUG)
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
|
|
||||||
#endif
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data
|
|
||||||
* have to be in the first 8 MB of memory, since this is
|
|
||||||
* the maximum mapped by the Linux kernel during initialization.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* FLASH organization
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
|
||||||
#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
|
||||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
|
||||||
|
|
||||||
#if 1
|
|
||||||
/* Start port with environment in flash; switch to SPI EEPROM later */
|
|
||||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
|
||||||
#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
|
|
||||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
|
||||||
|
|
||||||
/* Address and size of Redundant Environment Sector */
|
|
||||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
|
|
||||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
|
||||||
#else
|
|
||||||
/* Final version: environment in EEPROM */
|
|
||||||
#define CONFIG_ENV_IS_IN_EEPROM 1
|
|
||||||
#define CONFIG_ENV_OFFSET 2048
|
|
||||||
#define CONFIG_ENV_SIZE 2048
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Hardware Information Block
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
|
|
||||||
#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
|
|
||||||
#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* Cache Configuration
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
|
||||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SYPCR - System Protection Control 11-9
|
|
||||||
* SYPCR can only be written once after reset!
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
|
||||||
*/
|
|
||||||
#if defined(CONFIG_WATCHDOG)
|
|
||||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
|
||||||
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
|
||||||
SYPCR_SWP)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SIUMCR - SIU Module Configuration 11-6
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* we must activate GPL5 in the SIUMCR for CAN
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* TBSCR - Time Base Status and Control 11-26
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* RTCSC - Real-Time Clock Status and Control Register 11-27
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* Reset PLL lock status sticky bit, timer expired status bit and timer
|
|
||||||
* interrupt status bit
|
|
||||||
*
|
|
||||||
* If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
|
|
||||||
*/
|
|
||||||
#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
|
||||||
#define CONFIG_SYS_PLPRCR \
|
|
||||||
( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
|
|
||||||
#else /* up to 50 MHz we use a 1:1 clock */
|
|
||||||
#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
|
|
||||||
#endif /* CCM_80MHz */
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
* SCCR - System Clock and reset Control Register 15-27
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
* Set clock output, timebase and RTC source and divider,
|
|
||||||
* power management and some other internal clocks
|
|
||||||
*/
|
|
||||||
#define SCCR_MASK SCCR_EBDF11
|
|
||||||
#ifdef CCM_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */
|
|
||||||
#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ \
|
|
||||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
|
||||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
|
||||||
SCCR_DFALCD00)
|
|
||||||
#else /* up to 50 MHz we use a 1:1 clock */
|
|
||||||
#define CONFIG_SYS_SCCR (SCCR_TBS | \
|
|
||||||
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
|
||||||
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
|
||||||
SCCR_DFALCD00)
|
|
||||||
#endif /* CCM_80MHz */
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*
|
|
||||||
* Interrupt Levels
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
|
|
||||||
|
|
||||||
/*-----------------------------------------------------------------------
|
|
||||||
*
|
|
||||||
*-----------------------------------------------------------------------
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_DER 0
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Init Memory Controller:
|
|
||||||
*
|
|
||||||
* BR0/1 and OR0/1 (FLASH)
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
|
|
||||||
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
|
|
||||||
|
|
||||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
|
||||||
* restrict access enough to keep SRAM working (if any)
|
|
||||||
* but not too much to meddle with FLASH accesses
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
|
||||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
|
|
||||||
|
|
||||||
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
|
|
||||||
#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
|
|
||||||
OR_SCY_5_CLK | OR_EHTR)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
|
||||||
#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
|
|
||||||
#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
|
|
||||||
|
|
||||||
#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
|
|
||||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
|
|
||||||
#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR2 and OR2 (SDRAM)
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
|
|
||||||
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
|
|
||||||
#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
|
|
||||||
|
|
||||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
|
||||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
|
|
||||||
|
|
||||||
#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
|
|
||||||
#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR3 and OR3 (CAN Controller)
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
|
|
||||||
#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
|
|
||||||
#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
|
|
||||||
#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
|
|
||||||
BR_PS_8 | BR_MS_UPMB | BR_V )
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR4/OR4: PUMA Config
|
|
||||||
*
|
|
||||||
* Memory controller will be used in 2 modes:
|
|
||||||
*
|
|
||||||
* - "read" mode:
|
|
||||||
* BR4: 0x10100801 OR4: 0xffff8520
|
|
||||||
* - "load" mode (chip select on UPM B):
|
|
||||||
* BR4: 0x101004c1 OR4: 0xffff8600
|
|
||||||
*
|
|
||||||
* Default initialization is in "read" mode
|
|
||||||
*/
|
|
||||||
#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
|
|
||||||
#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
|
|
||||||
#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_2_CLK)
|
|
||||||
#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_2_CLK)
|
|
||||||
|
|
||||||
#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
|
|
||||||
BR_PS_8 | BR_MS_UPMB | BR_V)
|
|
||||||
#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
|
|
||||||
|
|
||||||
#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
|
|
||||||
#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BR4_PRELIM PUMA_CONF_BR_READ
|
|
||||||
#define CONFIG_SYS_OR4_PRELIM PUMA_CONF_OR_READ
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR5/OR5: PUMA: SMA Bus 8 Bit
|
|
||||||
* BR5: 0x10200401 OR5: 0xffe0010a
|
|
||||||
*/
|
|
||||||
#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */
|
|
||||||
#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */
|
|
||||||
#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
|
|
||||||
#define CONFIG_SYS_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR6/OR6: PUMA: SMA Bus 16 Bit
|
|
||||||
* BR6: 0x10600801 OR6: 0xffe0010a
|
|
||||||
*/
|
|
||||||
#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */
|
|
||||||
#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */
|
|
||||||
#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
|
|
||||||
#define CONFIG_SYS_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* BR7/OR7: PUMA: external Flash
|
|
||||||
* BR7: 0x10a00801 OR7: 0xfe00010a
|
|
||||||
*/
|
|
||||||
#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */
|
|
||||||
#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */
|
|
||||||
#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
|
|
||||||
#define CONFIG_SYS_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory Periodic Timer Prescaler
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* periodic timer for refresh */
|
|
||||||
#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
|
|
||||||
|
|
||||||
/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
|
|
||||||
#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
|
||||||
#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
|
||||||
|
|
||||||
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
|
||||||
#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
|
||||||
#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* MAMR settings for SDRAM
|
|
||||||
*/
|
|
||||||
|
|
||||||
/* 8 column SDRAM */
|
|
||||||
#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
|
||||||
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
|
||||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
|
||||||
/* 9 column SDRAM */
|
|
||||||
#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
|
||||||
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
|
||||||
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
|
||||||
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Internal Definitions
|
|
||||||
*
|
|
||||||
* Boot Flags
|
|
||||||
*/
|
|
||||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
|
||||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
|
||||||
|
|
||||||
#endif /* __CONFIG_H */
|
|
||||||
|
|
@ -190,22 +190,6 @@ void status_led_set (int led, int state);
|
||||||
|
|
||||||
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
||||||
|
|
||||||
/***** CCM ************************************************************/
|
|
||||||
#elif defined(CONFIG_CCM)
|
|
||||||
|
|
||||||
# define STATUS_LED_PAR im_cpm.cp_pbpar
|
|
||||||
# define STATUS_LED_DIR im_cpm.cp_pbdir
|
|
||||||
# define STATUS_LED_ODR im_cpm.cp_pbodr
|
|
||||||
# define STATUS_LED_DAT im_cpm.cp_pbdat
|
|
||||||
|
|
||||||
# define STATUS_LED_BIT 0x00010000 /* green LED is on PB.15 */
|
|
||||||
# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
|
|
||||||
# define STATUS_LED_STATE STATUS_LED_BLINKING
|
|
||||||
|
|
||||||
# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
|
|
||||||
|
|
||||||
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
|
||||||
|
|
||||||
/***** ICU862 ********************************************************/
|
/***** ICU862 ********************************************************/
|
||||||
#elif defined(CONFIG_ICU862)
|
#elif defined(CONFIG_ICU862)
|
||||||
|
|
||||||
|
|
@ -270,7 +254,7 @@ void status_led_set (int led, int state);
|
||||||
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
|
||||||
|
|
||||||
/***** KUP4K, KUP4X ****************************************************/
|
/***** KUP4K, KUP4X ****************************************************/
|
||||||
#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) || defined(CONFIG_CCM)
|
#elif defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X)
|
||||||
|
|
||||||
# define STATUS_LED_PAR im_ioport.iop_papar
|
# define STATUS_LED_PAR im_ioport.iop_papar
|
||||||
# define STATUS_LED_DIR im_ioport.iop_padir
|
# define STATUS_LED_DIR im_ioport.iop_padir
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue