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u-boot
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Merge branch 'master' of git://git.denx.de/u-boot-sh

This commit is contained in:
Wolfgang Denk 2009-03-15 22:15:13 +01:00
parent 45f93d4e3c 94a353611b
commit e05825324a
17 changed files with 493 additions and 121 deletions
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15
Makefile
View File

@ -3398,10 +3398,23 @@ sh7763rdp_config : unconfig
@echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7763rdp renesas
xtract_sh7785lcr = $(subst _32bit,,$(subst _config,,$1))
sh7785lcr_32bit_config \
sh7785lcr_config : unconfig
@ >include/config.h
@echo "#define CONFIG_SH7785LCR 1" >> include/config.h
@$(MKCONFIG) -a $(@:_config=) sh sh4 sh7785lcr renesas
@if [ "$(findstring 32bit, $@)" ] ; then \
echo "#define CONFIG_SH_32BIT 1" >> $(obj)include/config.h ; \
cp $(obj)board/renesas/sh7785lcr/u-boot_32bit \
$(obj)board/renesas/sh7785lcr/u-boot.lds ; \
echo "TEXT_BASE = 0x8ff80000" > \
$(obj)board/renesas/sh7785lcr/config.tmp ; \
$(XECHO) " ... enable 32-Bit Address Extended Mode" ; \
else \
cp $(obj)board/renesas/sh7785lcr/u-boot_29bit \
$(obj)board/renesas/sh7785lcr/u-boot.lds ; \
fi
@$(MKCONFIG) -a $(call xtract_sh7785lcr,$@) sh sh4 sh7785lcr renesas
ap325rxa_config : unconfig
@mkdir -p $(obj)include

156
board/ms7720se/lowlevel_init.S
View File

@ -18,6 +18,8 @@
* MA 02111-1307 USA
*/
#include <asm/macro.h>
.global lowlevel_init
.text
@ -25,157 +27,83 @@
lowlevel_init:
mov.l WTCSR_A,r1
mov.l WTCSR_D,r0
mov.w r0,@r1
write16 WTCSR_A, WTCSR_D
mov.l WTCNT_A,r1
mov.l WTCNT_D,r0
mov.w r0,@r1
write16 WTCNT_A, WTCNT_D
mov.l FRQCR_A,r1
mov.l FRQCR_D,r0
mov.w r0,@r1
write16 FRQCR_A, FRQCR_D
mov.l UCLKCR_A,r1
mov.l UCLKCR_D,r0
mov.w r0,@r1
write16 UCLKCR_A, UCLKCR_D
mov.l CMNCR_A, r1
mov.l CMNCR_D, r0
mov.l r0, @r1
write32 CMNCR_A, CMNCR_D
mov.l CS0BCR_A, r1
mov.l CS0BCR_D, r0
mov.l r0, @r1
write32 CMNCR_A, CMNCR_D
mov.l CS2BCR_A, r1
mov.l CS2BCR_D, r0
mov.l r0, @r1
write32 CS0BCR_A, CS0BCR_D
mov.l CS3BCR_A, r1
mov.l CS3BCR_D, r0
mov.l r0, @r1
write32 CS2BCR_A, CS2BCR_D
mov.l CS4BCR_A, r1
mov.l CS4BCR_D, r0
mov.l r0, @r1
write32 CS3BCR_A, CS3BCR_D
mov.l CS5ABCR_A, r1
mov.l CS5ABCR_D, r0
mov.l r0, @r1
write32 CS4BCR_A, CS4BCR_D
mov.l CS5BBCR_A, r1
mov.l CS5BBCR_D, r0
mov.l r0, @r1
write32 CS5ABCR_A, CS5ABCR_D
mov.l CS6ABCR_A, r1
mov.l CS6ABCR_D, r0
mov.l r0, @r1
write32 CS5BBCR_A, CS5BBCR_D
mov.l CS6BBCR_A, r1
mov.l CS6BBCR_D, r0
mov.l r0, @r1
write32 CS6ABCR_A, CS6ABCR_D
mov.l CS0WCR_A, r1
mov.l CS0WCR_D, r0
mov.l r0, @r1
write32 CS6BBCR_A, CS6BBCR_D
mov.l CS2WCR_A, r1
mov.l CS2WCR_D, r0
mov.l r0, @r1
write32 CS0WCR_A, CS0WCR_D
mov.l CS3WCR_A, r1
mov.l CS3WCR_D, r0
mov.l r0, @r1
write32 CS2WCR_A, CS2WCR_D
mov.l CS4WCR_A, r1
mov.l CS4WCR_D, r0
mov.l r0, @r1
write32 CS3WCR_A, CS3WCR_D
mov.l CS5AWCR_A, r1
mov.l CS5AWCR_D, r0
mov.l r0, @r1
write32 CS4WCR_A, CS4WCR_D
mov.l CS5BWCR_A, r1
mov.l CS5BWCR_D, r0
mov.l r0, @r1
write32 CS5AWCR_A, CS5AWCR_D
mov.l CS6AWCR_A, r1
mov.l CS6AWCR_D, r0
mov.l r0, @r1
write32 CS5BWCR_A, CS5BWCR_D
mov.l CS6BWCR_A, r1
mov.l CS6BWCR_D, r0
mov.l r0, @r1
write32 CS6AWCR_A, CS6AWCR_D
mov.l SDCR_A, r1
mov.l SDCR_D1, r0
mov.l r0, @r1
write32 CS6BWCR_A, CS6BWCR_D
mov.l RTCSR_A, r1
mov.l RTCSR_D, r0
mov.l r0, @r1
write32 SDCR_A, SDCR_D1
mov.l RTCNT_A, r1
mov.l RTCNT_D, r0
mov.l r0, @r1
write32 RTCSR_A, RTCSR_D
mov.l RTCOR_A, r1
mov.l RTCOR_D, r0
mov.l r0, @r1
write32 RTCNT_A RTCNT_D
mov.l SDCR_A, r1
mov.l SDCR_D2, r0
mov.l r0, @r1
write32 RTCOR_A, RTCOR_D
mov.l SDMR3_A, r1
mov.l SDMR3_D, r0
mov.w r0, @r1
write32 SDCR_A, SDCR_D2
mov.l PCCR_A, r1
mov.l PCCR_D, r0
mov.w r0, @r1
write16 SDMR3_A, SDMR3_D
mov.l PDCR_A, r1
mov.l PDCR_D, r0
mov.w r0, @r1
write16 PCCR_A, PCCR_D
mov.l PECR_A, r1
mov.l PECR_D, r0
mov.w r0, @r1
write16 PDCR_A, PDCR_D
mov.l PGCR_A, r1
mov.l PGCR_D, r0
mov.w r0, @r1
write16 PECR_A, PECR_D
mov.l PHCR_A, r1
mov.l PHCR_D, r0
mov.w r0, @r1
write16 PGCR_A, PGCR_D
mov.l PPCR_A, r1
mov.l PPCR_D, r0
mov.w r0, @r1
write16 PHCR_A, PHCR_D
mov.l PTCR_A, r1
mov.l PTCR_D, r0
mov.w r0, @r1
write16 PPCR_A, PPCR_D
mov.l PVCR_A, r1
mov.l PVCR_D, r0
mov.w r0, @r1
write16 PTCR_A, PTCR_D
mov.l PSELA_A, r1
mov.l PSELA_D, r0
mov.w r0, @r1
write16 PVCR_A, PVCR_D
mov.l CCR_A, r1
mov.l CCR_D, r0
mov.l r0, @r1
write16 PSELA_A, PSELA_D
mov.l LED_A, r1
mov.l LED_D, r0
mov.b r0, @r1
write32 CCR_A, CCR_D
write8 LED_A, LED_D
rts
nop

2
board/renesas/ap325rxa/lowlevel_init.S
View File

@ -173,7 +173,7 @@ CS6BBCR_D: .long 0x24920600
CS0WCR_D: .long 0x00000480
CS4WCR_D: .long 0x00000480
CS5AWCR_D: .long 0x00000380
CS5BWCR_D: .long 0x00000600
CS5BWCR_D: .long 0x00000080
CS6AWCR_D: .long 0x00000300
CS6BWCR_D: .long 0x00000540

4
board/renesas/sh7785lcr/config.mk
View File

@ -22,4 +22,8 @@
#
# NOTE: Must match value used in u-boot.lds (in this directory).
#
sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
TEXT_BASE = 0x0ff80000
endif

94
board/renesas/sh7785lcr/lowlevel_init.S
View File

@ -130,6 +130,46 @@ lbsc_29bit:
write32 CS6WCR_A, CS_SD_WCR_D
lbsc_end:
#if defined(CONFIG_SH_32BIT)
/*------- set PMB -------*/
write32 PASCR_A, PASCR_29BIT_D
write32 MMUCR_A, MMUCR_D
/*****************************************************************
* ent virt phys v sz c wt
* 0 0xa0000000 0x00000000 1 64M 0 0
* 1 0xa4000000 0x04000000 1 16M 0 0
* 2 0xa6000000 0x08000000 1 16M 0 0
* 9 0x88000000 0x48000000 1 128M 1 1
* 10 0x90000000 0x50000000 1 128M 1 1
* 11 0x98000000 0x58000000 1 128M 1 1
* 13 0xa8000000 0x48000000 1 128M 0 0
* 14 0xb0000000 0x50000000 1 128M 0 0
* 15 0xb8000000 0x58000000 1 128M 0 0
*/
write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D
write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D
write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D
write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D
write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D
write32 PMB_DATA_USB_A, PMB_DATA_USB_D
write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D
write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D
write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D
write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D
write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D
write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D
write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D
write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D
write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D
write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D
write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D
write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D
write32 PASCR_A, PASCR_INIT
mov.l DUMMY_ADDR, r0
icbi @r0
#endif
write32 CCR_A, CCR_D
@ -140,7 +180,11 @@ lbsc_end:
/*------- LBSC -------*/
MMSELR_A: .long 0xfc400020
#if defined(CONFIG_SH_32BIT)
MMSELR_D: .long 0xa5a50005
#else
MMSELR_D: .long 0xa5a50002
#endif
/*------- DBSC2 -------*/
#define DBSC2_BASE 0xfe800000
@ -287,5 +331,55 @@ CS_SD_WCR_D: .long 0x00030108
CS_I2C_BCR_D: .long 0x11111100
CS_I2C_WCR_D: .long 0x00000003
#if defined(CONFIG_SH_32BIT)
/*------- set PMB -------*/
PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0)
PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1)
PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2)
PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9)
PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10)
PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11)
PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13)
PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14)
PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15)
PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0)
PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4)
PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6)
PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88)
PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90)
PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98)
PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8)
PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0)
PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8)
PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0)
PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1)
PMB_DATA_USB_A: .long PMB_DATA_BASE(2)
PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9)
PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10)
PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11)
PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13)
PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14)
PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15)
/* ppn ub v s1 s0 c wt */
PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1)
PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1)
PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1)
PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1)
PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1)
PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1)
PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1)
DUMMY_ADDR: .long 0xa0000000
PASCR_29BIT_D: .long 0x00000000
PASCR_INIT: .long 0x80000080 /* check booting mode */
MMUCR_A: .long 0xff000010
MMUCR_D: .long 0x00000004 /* clear ITLB */
#endif /* CONFIG_SH_32BIT */
CCR_A: .long 0xff00001c
CCR_D: .long 0x0000090b

32
board/renesas/sh7785lcr/sh7785lcr.c
View File

@ -54,3 +54,35 @@ int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}
#if defined(CONFIG_SH_32BIT)
int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
/* clear ITLB */
writel(0x00000004, 0xff000010);
/* delete PMB for peripheral */
writel(0, PMB_ADDR_BASE(0));
writel(0, PMB_DATA_BASE(0));
writel(0, PMB_ADDR_BASE(1));
writel(0, PMB_DATA_BASE(1));
writel(0, PMB_ADDR_BASE(2));
writel(0, PMB_DATA_BASE(2));
/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8));
writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8));
writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12));
writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12));
return 0;
}
U_BOOT_CMD(
pmb, 1, 1, do_pmb,
"pmb - PMB setting\n",
"\n"
" - PMB setting for all SDRAM mapping\n"
);
#endif

4
board/renesas/sh7785lcr/u-boot.lds
View File

@ -1,7 +1,7 @@
/*
* Copyrigth (c) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyrigth (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
* Copyrigth (c) 2008-2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -28,7 +28,7 @@ ENTRY(_start)
SECTIONS
{
. = 0x08000000 + (128 * 1024 * 1024) - (512 * 1024);
. = 0x88000000 + (128 * 1024 * 1024) - (512 * 1024);
PROVIDE (reloc_dst = .);

96
board/renesas/sh7785lcr/u-boot_29bit Normal file
View File

@ -0,0 +1,96 @@
/*
* Copyrigth (c) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyrigth (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
OUTPUT_ARCH(sh)
ENTRY(_start)
SECTIONS
{
. = 0x08000000 + (128 * 1024 * 1024) - (512 * 1024);
PROVIDE (reloc_dst = .);
PROVIDE (_ftext = .);
PROVIDE (_fcode = .);
PROVIDE (_start = .);
.text :
{
cpu/sh4/start.o (.text)
. = ALIGN(8192);
common/env_embedded.o (.ppcenv)
. = ALIGN(8192);
common/env_embedded.o (.ppcenvr)
. = ALIGN(8192);
*(.text)
. = ALIGN(4);
} =0xFF
PROVIDE (_ecode = .);
.rodata :
{
*(.rodata)
. = ALIGN(4);
}
PROVIDE (_etext = .);
PROVIDE (_fdata = .);
.data :
{
*(.data)
. = ALIGN(4);
}
PROVIDE (_edata = .);
PROVIDE (_fgot = .);
.got :
{
*(.got)
. = ALIGN(4);
}
PROVIDE (_egot = .);
PROVIDE (__u_boot_cmd_start = .);
.u_boot_cmd :
{
*(.u_boot_cmd)
. = ALIGN(4);
}
PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
PROVIDE (bss_start = .);
PROVIDE (__bss_start = .);
.bss :
{
*(.bss)
. = ALIGN(4);
}
PROVIDE (bss_end = .);
PROVIDE (_end = .);
}

96
board/renesas/sh7785lcr/u-boot_32bit Normal file
View File

@ -0,0 +1,96 @@
/*
* Copyrigth (c) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Copyrigth (c) 2008-2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
OUTPUT_ARCH(sh)
ENTRY(_start)
SECTIONS
{
. = 0x88000000 + (128 * 1024 * 1024) - (512 * 1024);
PROVIDE (reloc_dst = .);
PROVIDE (_ftext = .);
PROVIDE (_fcode = .);
PROVIDE (_start = .);
.text :
{
cpu/sh4/start.o (.text)
. = ALIGN(8192);
common/env_embedded.o (.ppcenv)
. = ALIGN(8192);
common/env_embedded.o (.ppcenvr)
. = ALIGN(8192);
*(.text)
. = ALIGN(4);
} =0xFF
PROVIDE (_ecode = .);
.rodata :
{
*(.rodata)
. = ALIGN(4);
}
PROVIDE (_etext = .);
PROVIDE (_fdata = .);
.data :
{
*(.data)
. = ALIGN(4);
}
PROVIDE (_edata = .);
PROVIDE (_fgot = .);
.got :
{
*(.got)
. = ALIGN(4);
}
PROVIDE (_egot = .);
PROVIDE (__u_boot_cmd_start = .);
.u_boot_cmd :
{
*(.u_boot_cmd)
. = ALIGN(4);
}
PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
PROVIDE (bss_start = .);
PROVIDE (__bss_start = .);
.bss :
{
*(.bss)
. = ALIGN(4);
}
PROVIDE (bss_end = .);
PROVIDE (_end = .);
}

1
cpu/sh4/cpu.c
View File

@ -23,6 +23,7 @@
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/processor.h>
#include <asm/cache.h>

41
doc/README.sh7785lcr
View File

@ -33,6 +33,38 @@ This board has 2 physical memory maps. It can be changed with DIP switch(S2-5).
0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
configuration for This board:
=============================
You can choose configuration as follows:
- make sh7785lcr_config
- make sh7785lcr_32bit_config
When you use "make sh7785lcr_config", there is build U-Boot for 29-bit
address mode. This mode can use 128MB DDR-SDRAM.
When you use "make sh7785lcr_32bit_config", there is build U-Boot for 32-bit
extended address mode. This mode can use 384MB DDR-SDRAM. And if you run
"pmb" command, this mode can use 512MB DDR-SDRAM.
* 32-bit extended address mode PMB mapping *
a) on start-up
virt | phys | size | device
-------------+---------------+---------------+---------------
0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
0xa0000000 | 0x00000000 | 64MB | NOR Flash
0xa4000000 | 0x04000000 | 16MB | PLD
0xa6000000 | 0x08000000 | 16MB | USB
0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable)
b) after "pmb" command
virt | phys | size | device
-------------+---------------+---------------+---------------
0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable)
0xa0000000 | 0x40000000 | 512MB | DDR-SDRAM (Non-cacheable)
This board specific command:
============================
@ -41,6 +73,7 @@ This board has the following its specific command:
- hwtest
- printmac
- setmac
- pmb (sh7785lcr_32bit_config only)
1. hwtest
@ -80,3 +113,11 @@ This command writes MAC address of this board.
i.e)
=> setmac 00:00:87:**:**:**
4. pmb
This command change PMB for DDR-SDRAM all mapping. However you cannot use
NOR Flash and USB Host on U-Boot when you run this command.
i.e)
=> pmb

10
drivers/pci/pci_sh4.c
View File

@ -54,6 +54,16 @@ int pci_sh4_init(struct pci_controller *hose)
PCI_REGION_IO);
hose->region_count++;
#if defined(CONFIG_PCI_SYS_BUS)
/* PCI System Memory space */
pci_set_region(hose->regions + 2,
CONFIG_PCI_SYS_BUS,
CONFIG_PCI_SYS_PHYS,
CONFIG_PCI_SYS_SIZE,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count++;
#endif
udelay(1000);
pci_set_ops(hose,

6
drivers/pci/pci_sh7780.c
View File

@ -85,11 +85,11 @@ int pci_sh7780_init(struct pci_controller *hose)
p4_out(SH7780_PCICR_PREFIX, SH7780_PCICR);
p4_outw(0x0047, SH7780_PCICMD);
p4_out(0x07F00001, SH7780_PCILSR0);
p4_out(0x08000000, SH7780_PCILAR0);
p4_out(CONFIG_SH7780_PCI_LSR, SH7780_PCILSR0);
p4_out(CONFIG_SH7780_PCI_LAR, SH7780_PCILAR0);
p4_out(0x00000000, SH7780_PCILSR1);
p4_out(0, SH7780_PCILAR1);
p4_out(0x08000000, SH7780_PCIMBAR0);
p4_out(CONFIG_SH7780_PCI_BAR, SH7780_PCIMBAR0);
p4_out(0x00000000, SH7780_PCIMBAR1);
p4_out(0xFD000000, SH7780_PCIMBR0);

25
include/asm-sh/cpu_sh4.h
View File

@ -54,4 +54,29 @@
# error "Unknown SH4 variant"
#endif
#if defined(CONFIG_SH_32BIT)
#define PMB_ADDR_ARRAY 0xf6100000
#define PMB_ADDR_ENTRY 8
#define PMB_VPN 24
#define PMB_DATA_ARRAY 0xf7100000
#define PMB_DATA_ENTRY 8
#define PMB_PPN 24
#define PMB_UB 9 /* Buffered write */
#define PMB_V 8 /* Valid */
#define PMB_SZ1 7 /* Page size (upper bit) */
#define PMB_SZ0 4 /* Page size (lower bit) */
#define PMB_C 3 /* Cacheability */
#define PMB_WT 0 /* Write-through */
#define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY))
#define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY))
#define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN))
#define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \
((ppn << PMB_PPN) | (ub << PMB_UB) | \
(v << PMB_V) | (sz1 << PMB_SZ1) | \
(sz0 << PMB_SZ0) | (c << PMB_C) | \
(wt << PMB_WT))
#endif
#endif /* _ASM_CPU_SH4_H_ */

3
include/configs/r2dplus.h
View File

@ -114,6 +114,9 @@
#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
#define CONFIG_PCI_SYS_BUS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
#define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
/*
* Network device (RTL8139) support

3
include/configs/r7780mp.h
View File

@ -129,6 +129,9 @@
#define CONFIG_PCI
#define CONFIG_SH4_PCI
#define CONFIG_SH7780_PCI
#define CONFIG_SH7780_PCI_LSR 0x07f00001
#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW 1
#define __io

26
include/configs/sh7785lcr.h
View File

@ -61,11 +61,20 @@
#undef CONFIG_SHOW_BOOT_PROGRESS
/* MEMORY */
#if defined(CONFIG_SH_32BIT)
#define SH7785LCR_SDRAM_PHYS_BASE (0x48000000)
#define SH7785LCR_SDRAM_BASE (0x88000000)
#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
#define SH7785LCR_USB_BASE (0xa6000000)
#else
#define SH7785LCR_SDRAM_BASE (0x08000000)
#define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
#define SH7785LCR_FLASH_BASE_1 (0xa0000000)
#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
#define SH7785LCR_USB_BASE (0xb4000000)
#endif
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT "=> "
@ -133,6 +142,15 @@
#define CONFIG_PCI
#define CONFIG_SH4_PCI
#define CONFIG_SH7780_PCI
#if defined(CONFIG_SH_32BIT)
#define CONFIG_SH7780_PCI_LSR 0x1ff00001
#define CONFIG_SH7780_PCI_LAR 0x5f000000
#define CONFIG_SH7780_PCI_BAR 0x5f000000
#else
#define CONFIG_SH7780_PCI_LSR 0x07f00001
#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
#endif
#define CONFIG_PCI_PNP
#define CONFIG_PCI_SCAN_SHOW 1
@ -144,6 +162,14 @@
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
#if defined(CONFIG_SH_32BIT)
#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
#else
#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
#endif
#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
/* Network device (RTL8169) support */
#define CONFIG_NET_MULTI
#define CONFIG_RTL8169