From e0ff3d350d6b7960deb5a881dfc5acf3a63ef676 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Mon, 8 Sep 2008 08:51:29 -0500 Subject: [PATCH] 85xx: Ensure timebase is zero on secondary cores The e500um says the timebase is volatile out of reset. To ensure TB sync works we need to make sure its zero. Signed-off-by: Kumar Gala --- cpu/mpc85xx/release.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 75676b5b9e..ec5e4daf88 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -37,6 +37,11 @@ __secondary_start_page: li r3,0x201 mtspr SPRN_BUCSR,r3 + /* Ensure TB is 0 */ + li r3,0 + mttbl r3 + mttbu r3 + /* Enable/invalidate the I-Cache */ mfspr r0,SPRN_L1CSR1 ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)