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ARM: AM43xx: GP-EVM: Correct GPIO used for VTT regulator control 

Schematic indicates GPIO5_7 is to be used for VTT regulator control
rather than GPIO0_21 so modify enable_vtt_regulator to reflect this.
Without this some boards will experience DDR3 corruption and fail to
boot.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
This commit is contained in:
Dave Gerlach 2014-01-14 17:24:01 -06:00 committed by Tom Rini
parent ebd5028336
commit e2176acbb4
2 changed files with 11 additions and 13 deletions
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1
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h
View File

@ -19,6 +19,7 @@
/* GPIO Base address */
#define GPIO0_BASE 0x44E07000
#define GPIO2_BASE 0x481AC000
#define GPIO5_BASE 0x48322000
/* Watchdog Timer */
#define WDT_BASE 0x44E35000

23
board/ti/am43xx/board.c
View File

@ -252,26 +252,23 @@ static void enable_vtt_regulator(void)
{
u32 temp;
/*GPIO_VTTEN - GPIO0_21 PINMUX Setup*/
writel(0x20009, CTRL_BASE + 0x0A60);
/*GPIO_VTTEN - GPIO5_7 PINMUX Setup*/
writel(0x7, CTRL_BASE + 0x0A5C);
writel(0x40002, PRCM_BASE + 0x2B68);
writel(0x102, PRCM_BASE + 0x8C98);
/* Poll if module is functional */
while ((readl(PRCM_BASE + 0x2B68) & 0x30000) != 0x0)
;
while ((readl(PRCM_BASE + 0x2B00) & 0x100) != 0x100)
while ((readl(PRCM_BASE + 0x8C98) & 0x30000) != 0x0)
;
/* enable module */
writel(0x0, GPIO0_BASE + 0x0130);
writel(0x0, GPIO5_BASE + 0x0130);
/*enable output for GPIO0_21*/
writel((1 << 22), GPIO0_BASE + 0x0194);
temp = readl(GPIO0_BASE + 0x0134);
temp = temp & ~(1 << 22);
writel(temp, GPIO0_BASE + 0x0134);
/*enable output for GPIO5_7*/
writel((1 << 7), GPIO5_BASE + 0x0194);
temp = readl(GPIO5_BASE + 0x0134);
temp = temp & ~(1 << 7);
writel(temp, GPIO5_BASE + 0x0134);
}
void sdram_init(void)