exynos: clock: use the clear and set bits macros.
Use setbits/clrbits macro instead of readl/writel function. (Suggested by Wolfgang) Signed-off-by: Inha Song <ideal.song@samsung.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Inha Song
Minkyu Kang
parent
3cb007a9f2
commit
e25bfecf7b
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@ -870,7 +870,6 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
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struct exynos4_clock *clk =
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(struct exynos4_clock *)samsung_get_base_clock();
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unsigned int addr;
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unsigned int val;
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/*
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* CLK_DIV_FSYS1
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@ -890,10 +889,8 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
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dev_index -= 2;
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}
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val = readl(addr);
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val &= ~(0xff << ((dev_index << 4) + 8));
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val |= (div & 0xff) << ((dev_index << 4) + 8);
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writel(val, addr);
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clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
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(div & 0xff) << ((dev_index << 4) + 8));
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}
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/* exynos4x12: set the mmc clock */
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@ -902,7 +899,6 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
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struct exynos4x12_clock *clk =
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(struct exynos4x12_clock *)samsung_get_base_clock();
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unsigned int addr;
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unsigned int val;
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/*
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* CLK_DIV_FSYS1
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@ -917,10 +913,8 @@ static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
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dev_index -= 2;
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}
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val = readl(addr);
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val &= ~(0xff << ((dev_index << 4) + 8));
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val |= (div & 0xff) << ((dev_index << 4) + 8);
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writel(val, addr);
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clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
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(div & 0xff) << ((dev_index << 4) + 8));
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}
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/* exynos5: set the mmc clock */
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@ -929,7 +923,6 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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unsigned int addr;
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unsigned int val;
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/*
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* CLK_DIV_FSYS1
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@ -944,10 +937,8 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
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dev_index -= 2;
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}
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val = readl(addr);
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val &= ~(0xff << ((dev_index << 4) + 8));
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val |= (div & 0xff) << ((dev_index << 4) + 8);
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writel(val, addr);
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clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
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(div & 0xff) << ((dev_index << 4) + 8));
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}
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/* exynos5: set the mmc clock */
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@ -956,7 +947,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
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struct exynos5420_clock *clk =
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(struct exynos5420_clock *)samsung_get_base_clock();
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unsigned int addr;
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unsigned int val, shift;
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unsigned int shift;
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/*
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* CLK_DIV_FSYS1
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@ -967,10 +958,7 @@ static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
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addr = (unsigned int)&clk->div_fsys1;
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shift = dev_index * 10;
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val = readl(addr);
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val &= ~(0x3ff << shift);
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val |= (div & 0x3ff) << shift;
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writel(val, addr);
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clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
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}
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/* get_lcd_clk: return lcd clock frequency */
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@ -1061,7 +1049,6 @@ void exynos4_set_lcd_clk(void)
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{
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struct exynos4_clock *clk =
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(struct exynos4_clock *)samsung_get_base_clock();
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unsigned int cfg = 0;
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/*
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* CLK_GATE_BLOCK
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@ -1073,9 +1060,7 @@ void exynos4_set_lcd_clk(void)
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* CLK_LCD1 [5]
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* CLK_GPS [7]
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*/
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cfg = readl(&clk->gate_block);
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cfg |= 1 << 4;
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writel(cfg, &clk->gate_block);
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setbits_le32(&clk->gate_block, 1 << 4);
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/*
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* CLK_SRC_LCD0
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@ -1085,10 +1070,7 @@ void exynos4_set_lcd_clk(void)
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* MIPI0_SEL [12:15]
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* set lcd0 src clock 0x6: SCLK_MPLL
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*/
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cfg = readl(&clk->src_lcd0);
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cfg &= ~(0xf);
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cfg |= 0x6;
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writel(cfg, &clk->src_lcd0);
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clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
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/*
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* CLK_GATE_IP_LCD0
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@ -1100,9 +1082,7 @@ void exynos4_set_lcd_clk(void)
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* CLK_PPMULCD0 [5]
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* Gating all clocks for FIMD0
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*/
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cfg = readl(&clk->gate_ip_lcd0);
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cfg |= 1 << 0;
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writel(cfg, &clk->gate_ip_lcd0);
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setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
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/*
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* CLK_DIV_LCD0
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@ -1114,17 +1094,13 @@ void exynos4_set_lcd_clk(void)
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* MIPI0_PRE_RATIO [23:20]
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* set fimd ratio
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*/
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cfg = readl(&clk->div_lcd0);
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cfg &= ~(0xf);
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cfg |= 0x1;
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writel(cfg, &clk->div_lcd0);
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clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
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}
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void exynos5_set_lcd_clk(void)
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{
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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unsigned int cfg = 0;
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/*
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* CLK_GATE_BLOCK
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@ -1136,9 +1112,7 @@ void exynos5_set_lcd_clk(void)
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* CLK_LCD1 [5]
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* CLK_GPS [7]
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*/
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cfg = readl(&clk->gate_block);
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cfg |= 1 << 4;
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writel(cfg, &clk->gate_block);
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setbits_le32(&clk->gate_block, 1 << 4);
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/*
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* CLK_SRC_LCD0
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@ -1148,10 +1122,7 @@ void exynos5_set_lcd_clk(void)
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* MIPI0_SEL [12:15]
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* set lcd0 src clock 0x6: SCLK_MPLL
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*/
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cfg = readl(&clk->src_disp1_0);
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cfg &= ~(0xf);
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cfg |= 0x6;
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writel(cfg, &clk->src_disp1_0);
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clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
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/*
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* CLK_GATE_IP_LCD0
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@ -1163,9 +1134,7 @@ void exynos5_set_lcd_clk(void)
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* CLK_PPMULCD0 [5]
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* Gating all clocks for FIMD0
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*/
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cfg = readl(&clk->gate_ip_disp1);
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cfg |= 1 << 0;
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writel(cfg, &clk->gate_ip_disp1);
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setbits_le32(&clk->gate_ip_disp1, 1 << 0);
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/*
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* CLK_DIV_LCD0
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@ -1177,17 +1146,13 @@ void exynos5_set_lcd_clk(void)
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* MIPI0_PRE_RATIO [23:20]
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* set fimd ratio
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*/
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cfg = readl(&clk->div_disp1_0);
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cfg &= ~(0xf);
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cfg |= 0x0;
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writel(cfg, &clk->div_disp1_0);
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clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
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}
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void exynos4_set_mipi_clk(void)
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{
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struct exynos4_clock *clk =
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(struct exynos4_clock *)samsung_get_base_clock();
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unsigned int cfg = 0;
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/*
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* CLK_SRC_LCD0
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@ -1197,10 +1162,7 @@ void exynos4_set_mipi_clk(void)
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* MIPI0_SEL [12:15]
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* set mipi0 src clock 0x6: SCLK_MPLL
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*/
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cfg = readl(&clk->src_lcd0);
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cfg &= ~(0xf << 12);
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cfg |= (0x6 << 12);
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writel(cfg, &clk->src_lcd0);
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clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
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/*
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* CLK_SRC_MASK_LCD0
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@ -1210,9 +1172,7 @@ void exynos4_set_mipi_clk(void)
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* MIPI0_MASK [12]
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* set src mask mipi0 0x1: Unmask
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*/
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cfg = readl(&clk->src_mask_lcd0);
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cfg |= (0x1 << 12);
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writel(cfg, &clk->src_mask_lcd0);
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setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
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/*
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* CLK_GATE_IP_LCD0
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@ -1224,9 +1184,7 @@ void exynos4_set_mipi_clk(void)
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* CLK_PPMULCD0 [5]
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* Gating all clocks for MIPI0
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*/
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cfg = readl(&clk->gate_ip_lcd0);
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cfg |= 1 << 3;
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writel(cfg, &clk->gate_ip_lcd0);
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setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
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/*
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* CLK_DIV_LCD0
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@ -1238,10 +1196,7 @@ void exynos4_set_mipi_clk(void)
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* MIPI0_PRE_RATIO [23:20]
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* set mipi ratio
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*/
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cfg = readl(&clk->div_lcd0);
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cfg &= ~(0xf << 16);
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cfg |= (0x1 << 16);
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writel(cfg, &clk->div_lcd0);
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clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
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}
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/*
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