am33xx: move ti i2c baseboard header handling to board/ti/am335x/
The i2c header is specific to ti(-derived) boards, and not generic for all am335x boards. Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com> [trini: Make re-apply with rtc32k_enable() applied] Signed-off-by: Tom Rini <trini@ti.com>
This commit is contained in:
parent
c50cce2758
commit
e363426e99
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@ -36,11 +36,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
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#ifdef CONFIG_SPL_BUILD
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static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
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#endif
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static const struct gpio_bank gpio_bank_am33xx[4] = {
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static const struct gpio_bank gpio_bank_am33xx[4] = {
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{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
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{ (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
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{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
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{ (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
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@ -50,172 +45,6 @@ static const struct gpio_bank gpio_bank_am33xx[4] = {
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const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
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const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
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/* MII mode defines */
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#define MII_MODE_ENABLE 0x0
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#define RGMII_MODE_ENABLE 0xA
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/* GPIO that controls power to DDR on EVM-SK */
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#define GPIO_DDR_VTT_EN 7
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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static struct am335x_baseboard_id __attribute__((section (".data"))) header;
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static inline int board_is_bone(void)
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{
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return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
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}
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static inline int board_is_bone_lt(void)
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{
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return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
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}
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static inline int board_is_evm_sk(void)
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{
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return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
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}
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/*
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* Read header information from EEPROM into global structure.
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*/
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static int read_eeprom(void)
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{
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/* Check if baseboard eeprom is available */
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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
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puts("Could not probe the EEPROM; something fundamentally "
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"wrong on the I2C bus.\n");
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return -ENODEV;
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}
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/* read the eeprom using i2c */
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
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sizeof(header))) {
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puts("Could not read the EEPROM; something fundamentally"
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" wrong on the I2C bus.\n");
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return -EIO;
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}
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if (header.magic != 0xEE3355AA) {
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/*
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* read the eeprom using i2c again,
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* but use only a 1 byte address
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*/
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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
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(uchar *)&header, sizeof(header))) {
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puts("Could not read the EEPROM; something "
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"fundamentally wrong on the I2C bus.\n");
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return -EIO;
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}
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if (header.magic != 0xEE3355AA) {
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printf("Incorrect magic number (0x%x) in EEPROM\n",
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header.magic);
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return -EINVAL;
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}
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}
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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/* UART Defines */
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#define UART_RESET (0x1 << 1)
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#define UART_CLK_RUNNING_MASK 0x1
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#define UART_SMART_IDLE_EN (0x1 << 0x3)
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static void rtc32k_enable(void)
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{
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struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
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/*
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* Unlock the RTC's registers. For more details please see the
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* RTC_SS section of the TRM. In order to unlock we need to
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* write these specific values (keys) in this order.
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*/
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writel(0x83e70b13, &rtc->kick0r);
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writel(0x95a4f1e0, &rtc->kick1r);
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/* Enable the RTC 32K OSC by setting bits 3 and 6. */
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writel((1 << 3) | (1 << 6), &rtc->osc);
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}
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#endif
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/*
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* Determine what type of DDR we have.
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*/
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static short inline board_memory_type(void)
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{
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/* The following boards are known to use DDR3. */
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if (board_is_evm_sk() || board_is_bone_lt())
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return EMIF_REG_SDRAM_TYPE_DDR3;
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return EMIF_REG_SDRAM_TYPE_DDR2;
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}
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/*
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* early system init of muxing and clocks.
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*/
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void s_init(void)
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{
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/* WDT1 is already running when the bootloader gets control
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* Disable it to avoid "random" resets
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*/
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writel(0xAAAA, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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writel(0x5555, &wdtimer->wdtwspr);
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while (readl(&wdtimer->wdtwwps) != 0x0)
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;
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#ifdef CONFIG_SPL_BUILD
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/* Setup the PLLs and the clocks for the peripherals */
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pll_init();
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/* Enable RTC32K clock */
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rtc32k_enable();
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/* UART softreset */
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u32 regVal;
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enable_uart0_pin_mux();
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regVal = readl(&uart_base->uartsyscfg);
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regVal |= UART_RESET;
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writel(regVal, &uart_base->uartsyscfg);
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while ((readl(&uart_base->uartsyssts) &
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UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
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;
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/* Disable smart idle */
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regVal = readl(&uart_base->uartsyscfg);
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regVal |= UART_SMART_IDLE_EN;
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writel(regVal, &uart_base->uartsyscfg);
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gd = &gdata;
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preloader_console_init();
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/* Initalize the board header */
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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if (read_eeprom() < 0)
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puts("Could not get board ID.\n");
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enable_board_pin_mux(&header);
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if (board_is_evm_sk()) {
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/*
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* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
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* This is safe enough to do on older revs.
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*/
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gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
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gpio_direction_output(GPIO_DDR_VTT_EN, 1);
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}
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config_ddr(board_memory_type());
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#endif
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}
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#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
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#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
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int board_mmc_init(bd_t *bis)
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int board_mmc_init(bd_t *bis)
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{
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{
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@ -234,93 +63,3 @@ void setup_clocks_for_console(void)
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/* Not yet implemented */
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/* Not yet implemented */
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return;
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return;
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}
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}
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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if (read_eeprom() < 0)
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puts("Could not get board ID.\n");
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gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
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return 0;
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}
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#ifdef CONFIG_DRIVER_TI_CPSW
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_id = 0,
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},
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{
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.slave_reg_ofs = 0x308,
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.sliver_reg_ofs = 0xdc0,
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.phy_id = 1,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = AM335X_CPSW_MDIO_BASE,
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.cpsw_base = AM335X_CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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int board_eth_init(bd_t *bis)
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{
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
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debug("<ethaddr> not set. Reading from E-fuse\n");
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (is_valid_ether_addr(mac_addr))
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eth_setenv_enetaddr("ethaddr", mac_addr);
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else
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return -1;
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}
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if (board_is_bone() || board_is_bone_lt()) {
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writel(MII_MODE_ENABLE, &cdev->miisel);
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cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
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PHY_INTERFACE_MODE_MII;
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} else {
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writel(RGMII_MODE_ENABLE, &cdev->miisel);
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cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
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PHY_INTERFACE_MODE_RGMII;
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}
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return cpsw_register(&cpsw_data);
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}
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#endif
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@ -19,24 +19,6 @@
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#ifndef _SYS_PROTO_H_
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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/*
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* AM335x parts define a system EEPROM that defines certain sub-fields.
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* We use these fields to in turn see what board we are on, and what
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* that might require us to set or not set.
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*/
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#define HDR_NO_OF_MAC_ADDR 3
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#define HDR_ETH_ALEN 6
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#define HDR_NAME_LEN 8
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struct am335x_baseboard_id {
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unsigned int magic;
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char name[HDR_NAME_LEN];
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char version[4];
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char serial[12];
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char config[32];
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char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
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};
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#define BOARD_REV_ID 0x0
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#define BOARD_REV_ID 0x0
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u32 get_cpu_rev(void);
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u32 get_cpu_rev(void);
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@ -51,13 +33,4 @@ u32 get_device_type(void);
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void setup_clocks_for_console(void);
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void setup_clocks_for_console(void);
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void ddr_pll_config(unsigned int ddrpll_M);
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void ddr_pll_config(unsigned int ddrpll_M);
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/*
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* We have three pin mux functions that must exist. We must be able to enable
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* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
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* main pinmux function that can be overridden to enable all other pinmux that
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* is required on the board.
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*/
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void enable_uart0_pin_mux(void);
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void enable_i2c0_pin_mux(void);
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void enable_board_pin_mux(struct am335x_baseboard_id *header);
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#endif
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#endif
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@ -22,6 +22,7 @@ ifdef CONFIG_SPL_BUILD
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COBJS := mux.o
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COBJS := mux.o
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endif
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endif
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COBJS += board.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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@ -0,0 +1,299 @@
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/*
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* board.c
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*
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* Board functions for TI AM335X based boards
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <errno.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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||||||
|
#include <miiphy.h>
|
||||||
|
#include <cpsw.h>
|
||||||
|
#include "board.h"
|
||||||
|
|
||||||
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
|
static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
|
||||||
|
#ifdef CONFIG_SPL_BUILD
|
||||||
|
static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* MII mode defines */
|
||||||
|
#define MII_MODE_ENABLE 0x0
|
||||||
|
#define RGMII_MODE_ENABLE 0xA
|
||||||
|
|
||||||
|
/* GPIO that controls power to DDR on EVM-SK */
|
||||||
|
#define GPIO_DDR_VTT_EN 7
|
||||||
|
|
||||||
|
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
|
||||||
|
|
||||||
|
static struct am335x_baseboard_id __attribute__((section (".data"))) header;
|
||||||
|
|
||||||
|
static inline int board_is_bone(void)
|
||||||
|
{
|
||||||
|
return !strncmp(header.name, "A335BONE", HDR_NAME_LEN);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int board_is_bone_lt(void)
|
||||||
|
{
|
||||||
|
return !strncmp(header.name, "A335BNLT", HDR_NAME_LEN);
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int board_is_evm_sk(void)
|
||||||
|
{
|
||||||
|
return !strncmp("A335X_SK", header.name, HDR_NAME_LEN);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Read header information from EEPROM into global structure.
|
||||||
|
*/
|
||||||
|
static int read_eeprom(void)
|
||||||
|
{
|
||||||
|
/* Check if baseboard eeprom is available */
|
||||||
|
if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
|
||||||
|
puts("Could not probe the EEPROM; something fundamentally "
|
||||||
|
"wrong on the I2C bus.\n");
|
||||||
|
return -ENODEV;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* read the eeprom using i2c */
|
||||||
|
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)&header,
|
||||||
|
sizeof(header))) {
|
||||||
|
puts("Could not read the EEPROM; something fundamentally"
|
||||||
|
" wrong on the I2C bus.\n");
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (header.magic != 0xEE3355AA) {
|
||||||
|
/*
|
||||||
|
* read the eeprom using i2c again,
|
||||||
|
* but use only a 1 byte address
|
||||||
|
*/
|
||||||
|
if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1,
|
||||||
|
(uchar *)&header, sizeof(header))) {
|
||||||
|
puts("Could not read the EEPROM; something "
|
||||||
|
"fundamentally wrong on the I2C bus.\n");
|
||||||
|
return -EIO;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (header.magic != 0xEE3355AA) {
|
||||||
|
printf("Incorrect magic number (0x%x) in EEPROM\n",
|
||||||
|
header.magic);
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* UART Defines */
|
||||||
|
#ifdef CONFIG_SPL_BUILD
|
||||||
|
#define UART_RESET (0x1 << 1)
|
||||||
|
#define UART_CLK_RUNNING_MASK 0x1
|
||||||
|
#define UART_SMART_IDLE_EN (0x1 << 0x3)
|
||||||
|
|
||||||
|
static void rtc32k_enable(void)
|
||||||
|
{
|
||||||
|
struct rtc_regs *rtc = (struct rtc_regs *)AM335X_RTC_BASE;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Unlock the RTC's registers. For more details please see the
|
||||||
|
* RTC_SS section of the TRM. In order to unlock we need to
|
||||||
|
* write these specific values (keys) in this order.
|
||||||
|
*/
|
||||||
|
writel(0x83e70b13, &rtc->kick0r);
|
||||||
|
writel(0x95a4f1e0, &rtc->kick1r);
|
||||||
|
|
||||||
|
/* Enable the RTC 32K OSC by setting bits 3 and 6. */
|
||||||
|
writel((1 << 3) | (1 << 6), &rtc->osc);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Determine what type of DDR we have.
|
||||||
|
*/
|
||||||
|
static short inline board_memory_type(void)
|
||||||
|
{
|
||||||
|
/* The following boards are known to use DDR3. */
|
||||||
|
if (board_is_evm_sk() || board_is_bone_lt())
|
||||||
|
return EMIF_REG_SDRAM_TYPE_DDR3;
|
||||||
|
|
||||||
|
return EMIF_REG_SDRAM_TYPE_DDR2;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* early system init of muxing and clocks.
|
||||||
|
*/
|
||||||
|
void s_init(void)
|
||||||
|
{
|
||||||
|
/* WDT1 is already running when the bootloader gets control
|
||||||
|
* Disable it to avoid "random" resets
|
||||||
|
*/
|
||||||
|
writel(0xAAAA, &wdtimer->wdtwspr);
|
||||||
|
while (readl(&wdtimer->wdtwwps) != 0x0)
|
||||||
|
;
|
||||||
|
writel(0x5555, &wdtimer->wdtwspr);
|
||||||
|
while (readl(&wdtimer->wdtwwps) != 0x0)
|
||||||
|
;
|
||||||
|
|
||||||
|
#ifdef CONFIG_SPL_BUILD
|
||||||
|
/* Setup the PLLs and the clocks for the peripherals */
|
||||||
|
pll_init();
|
||||||
|
|
||||||
|
/* Enable RTC32K clock */
|
||||||
|
rtc32k_enable();
|
||||||
|
|
||||||
|
/* UART softreset */
|
||||||
|
u32 regVal;
|
||||||
|
|
||||||
|
enable_uart0_pin_mux();
|
||||||
|
|
||||||
|
regVal = readl(&uart_base->uartsyscfg);
|
||||||
|
regVal |= UART_RESET;
|
||||||
|
writel(regVal, &uart_base->uartsyscfg);
|
||||||
|
while ((readl(&uart_base->uartsyssts) &
|
||||||
|
UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
|
||||||
|
;
|
||||||
|
|
||||||
|
/* Disable smart idle */
|
||||||
|
regVal = readl(&uart_base->uartsyscfg);
|
||||||
|
regVal |= UART_SMART_IDLE_EN;
|
||||||
|
writel(regVal, &uart_base->uartsyscfg);
|
||||||
|
|
||||||
|
gd = &gdata;
|
||||||
|
|
||||||
|
preloader_console_init();
|
||||||
|
|
||||||
|
/* Initalize the board header */
|
||||||
|
enable_i2c0_pin_mux();
|
||||||
|
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||||
|
if (read_eeprom() < 0)
|
||||||
|
puts("Could not get board ID.\n");
|
||||||
|
|
||||||
|
enable_board_pin_mux(&header);
|
||||||
|
if (board_is_evm_sk()) {
|
||||||
|
/*
|
||||||
|
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
|
||||||
|
* This is safe enough to do on older revs.
|
||||||
|
*/
|
||||||
|
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
|
||||||
|
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
config_ddr(board_memory_type());
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Basic board specific setup. Pinmux has been handled already.
|
||||||
|
*/
|
||||||
|
int board_init(void)
|
||||||
|
{
|
||||||
|
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||||
|
if (read_eeprom() < 0)
|
||||||
|
puts("Could not get board ID.\n");
|
||||||
|
|
||||||
|
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef CONFIG_DRIVER_TI_CPSW
|
||||||
|
static void cpsw_control(int enabled)
|
||||||
|
{
|
||||||
|
/* VTP can be added here */
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static struct cpsw_slave_data cpsw_slaves[] = {
|
||||||
|
{
|
||||||
|
.slave_reg_ofs = 0x208,
|
||||||
|
.sliver_reg_ofs = 0xd80,
|
||||||
|
.phy_id = 0,
|
||||||
|
},
|
||||||
|
{
|
||||||
|
.slave_reg_ofs = 0x308,
|
||||||
|
.sliver_reg_ofs = 0xdc0,
|
||||||
|
.phy_id = 1,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static struct cpsw_platform_data cpsw_data = {
|
||||||
|
.mdio_base = AM335X_CPSW_MDIO_BASE,
|
||||||
|
.cpsw_base = AM335X_CPSW_BASE,
|
||||||
|
.mdio_div = 0xff,
|
||||||
|
.channels = 8,
|
||||||
|
.cpdma_reg_ofs = 0x800,
|
||||||
|
.slaves = 1,
|
||||||
|
.slave_data = cpsw_slaves,
|
||||||
|
.ale_reg_ofs = 0xd00,
|
||||||
|
.ale_entries = 1024,
|
||||||
|
.host_port_reg_ofs = 0x108,
|
||||||
|
.hw_stats_reg_ofs = 0x900,
|
||||||
|
.mac_control = (1 << 5),
|
||||||
|
.control = cpsw_control,
|
||||||
|
.host_port_num = 0,
|
||||||
|
.version = CPSW_CTRL_VERSION_2,
|
||||||
|
};
|
||||||
|
|
||||||
|
int board_eth_init(bd_t *bis)
|
||||||
|
{
|
||||||
|
uint8_t mac_addr[6];
|
||||||
|
uint32_t mac_hi, mac_lo;
|
||||||
|
|
||||||
|
if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
|
||||||
|
debug("<ethaddr> not set. Reading from E-fuse\n");
|
||||||
|
/* try reading mac address from efuse */
|
||||||
|
mac_lo = readl(&cdev->macid0l);
|
||||||
|
mac_hi = readl(&cdev->macid0h);
|
||||||
|
mac_addr[0] = mac_hi & 0xFF;
|
||||||
|
mac_addr[1] = (mac_hi & 0xFF00) >> 8;
|
||||||
|
mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
|
||||||
|
mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
|
||||||
|
mac_addr[4] = mac_lo & 0xFF;
|
||||||
|
mac_addr[5] = (mac_lo & 0xFF00) >> 8;
|
||||||
|
|
||||||
|
if (is_valid_ether_addr(mac_addr))
|
||||||
|
eth_setenv_enetaddr("ethaddr", mac_addr);
|
||||||
|
else
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (board_is_bone() || board_is_bone_lt()) {
|
||||||
|
writel(MII_MODE_ENABLE, &cdev->miisel);
|
||||||
|
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
|
||||||
|
PHY_INTERFACE_MODE_MII;
|
||||||
|
} else {
|
||||||
|
writel(RGMII_MODE_ENABLE, &cdev->miisel);
|
||||||
|
cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
|
||||||
|
PHY_INTERFACE_MODE_RGMII;
|
||||||
|
}
|
||||||
|
|
||||||
|
return cpsw_register(&cpsw_data);
|
||||||
|
}
|
||||||
|
#endif
|
|
@ -0,0 +1,49 @@
|
||||||
|
/*
|
||||||
|
* board.h
|
||||||
|
*
|
||||||
|
* TI AM335x boards information header
|
||||||
|
*
|
||||||
|
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _BOARD_H_
|
||||||
|
#define _BOARD_H_
|
||||||
|
|
||||||
|
/*
|
||||||
|
* TI AM335x parts define a system EEPROM that defines certain sub-fields.
|
||||||
|
* We use these fields to in turn see what board we are on, and what
|
||||||
|
* that might require us to set or not set.
|
||||||
|
*/
|
||||||
|
#define HDR_NO_OF_MAC_ADDR 3
|
||||||
|
#define HDR_ETH_ALEN 6
|
||||||
|
#define HDR_NAME_LEN 8
|
||||||
|
|
||||||
|
struct am335x_baseboard_id {
|
||||||
|
unsigned int magic;
|
||||||
|
char name[HDR_NAME_LEN];
|
||||||
|
char version[4];
|
||||||
|
char serial[12];
|
||||||
|
char config[32];
|
||||||
|
char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
|
||||||
|
};
|
||||||
|
|
||||||
|
/*
|
||||||
|
* We have three pin mux functions that must exist. We must be able to enable
|
||||||
|
* uart0, for initial output and i2c0 to read the main EEPROM. We then have a
|
||||||
|
* main pinmux function that can be overridden to enable all other pinmux that
|
||||||
|
* is required on the board.
|
||||||
|
*/
|
||||||
|
void enable_uart0_pin_mux(void);
|
||||||
|
void enable_i2c0_pin_mux(void);
|
||||||
|
void enable_board_pin_mux(struct am335x_baseboard_id *header);
|
||||||
|
#endif
|
|
@ -18,6 +18,7 @@
|
||||||
#include <asm/arch/hardware.h>
|
#include <asm/arch/hardware.h>
|
||||||
#include <asm/io.h>
|
#include <asm/io.h>
|
||||||
#include <i2c.h>
|
#include <i2c.h>
|
||||||
|
#include "board.h"
|
||||||
|
|
||||||
#define MUX_CFG(value, offset) \
|
#define MUX_CFG(value, offset) \
|
||||||
__raw_writel(value, (CTRL_BASE + offset));
|
__raw_writel(value, (CTRL_BASE + offset));
|
||||||
|
|
Loading…
Reference in New Issue