Merge branch 'master' of /home/wd/git/u-boot/custodians
* 'master' of /home/wd/git/u-boot/custodians: Tegra2: mmc: Factor out mmc_wait_inhibit functionality Tegra2: mmc: Add data transfer completion timeout Tegra2: mmc: Support DMA restarts at buffer boundaries Tegra2: mmc: define register field values in tegra2_mmc.h MMC: PL180: Fix infinite loop with VExpress extended fifo implementation
This commit is contained in:
commit
e4ed004b65
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@ -111,7 +111,6 @@ static int do_command(struct mmc *dev, struct mmc_cmd *cmd)
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static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize)
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static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize)
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{
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{
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u32 *tempbuff = dest;
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u32 *tempbuff = dest;
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int i;
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u64 xfercount = blkcount * blksize;
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u64 xfercount = blkcount * blksize;
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struct mmc_host *host = dev->priv;
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struct mmc_host *host = dev->priv;
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u32 status, status_err;
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u32 status, status_err;
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@ -121,31 +120,6 @@ static int read_bytes(struct mmc *dev, u32 *dest, u32 blkcount, u32 blksize)
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status = readl(&host->base->status);
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status = readl(&host->base->status);
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status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
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status_err = status & (SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT |
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SDI_STA_RXOVERR);
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SDI_STA_RXOVERR);
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while (!status_err &&
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(xfercount >= SDI_FIFO_BURST_SIZE * sizeof(u32))) {
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if (status & SDI_STA_RXFIFOBR) {
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for (i = 0; i < SDI_FIFO_BURST_SIZE; i++)
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*(tempbuff + i) = readl(&host->base->fifo);
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tempbuff += SDI_FIFO_BURST_SIZE;
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xfercount -= SDI_FIFO_BURST_SIZE * sizeof(u32);
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}
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status = readl(&host->base->status);
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status_err = status &
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(SDI_STA_DCRCFAIL | SDI_STA_DTIMEOUT | SDI_STA_RXOVERR);
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}
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if (status & SDI_STA_DTIMEOUT) {
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printf("Read data timed out, xfercount: %llu, status: 0x%08X\n",
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xfercount, status);
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return -ETIMEDOUT;
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} else if (status & SDI_STA_DCRCFAIL) {
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printf("Read data blk CRC error: 0x%x\n", status);
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return -EILSEQ;
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} else if (status & SDI_STA_RXOVERR) {
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printf("Read data RX overflow error\n");
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return -EIO;
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}
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while ((!status_err) && (xfercount >= sizeof(u32))) {
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while ((!status_err) && (xfercount >= sizeof(u32))) {
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if (status & SDI_STA_RXDAVL) {
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if (status & SDI_STA_RXDAVL) {
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*(tempbuff) = readl(&host->base->fifo);
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*(tempbuff) = readl(&host->base->fifo);
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@ -81,7 +81,8 @@ static void mmc_prepare_data(struct mmc_host *host, struct mmc_data *data)
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* 11 = Selects 64-bit Address ADMA2
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* 11 = Selects 64-bit Address ADMA2
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*/
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*/
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ctrl = readb(&host->reg->hostctl);
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ctrl = readb(&host->reg->hostctl);
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ctrl &= ~(3 << 3); /* SDMA */
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ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
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ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
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writeb(ctrl, &host->reg->hostctl);
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writeb(ctrl, &host->reg->hostctl);
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/* We do not handle DMA boundaries, so set it to max (512 KiB) */
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/* We do not handle DMA boundaries, so set it to max (512 KiB) */
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@ -103,43 +104,36 @@ static void mmc_set_transfer_mode(struct mmc_host *host, struct mmc_data *data)
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* ENBLKCNT[1] : Block Count Enable
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* ENBLKCNT[1] : Block Count Enable
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* ENDMA[0] : DMA Enable
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* ENDMA[0] : DMA Enable
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*/
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*/
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mode = (1 << 1) | (1 << 0);
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mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
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TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
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if (data->blocks > 1)
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if (data->blocks > 1)
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mode |= (1 << 5);
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mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
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if (data->flags & MMC_DATA_READ)
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if (data->flags & MMC_DATA_READ)
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mode |= (1 << 4);
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mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
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writew(mode, &host->reg->trnmod);
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writew(mode, &host->reg->trnmod);
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}
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}
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static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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static int mmc_wait_inhibit(struct mmc_host *host,
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struct mmc_data *data)
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struct mmc_cmd *cmd,
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struct mmc_data *data,
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unsigned int timeout)
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{
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{
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struct mmc_host *host = (struct mmc_host *)mmc->priv;
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int flags, i;
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unsigned int timeout;
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unsigned int mask;
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unsigned int retry = 0x100000;
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debug(" mmc_send_cmd called\n");
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/* Wait max 10 ms */
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timeout = 10;
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/*
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/*
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* PRNSTS
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* PRNSTS
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* CMDINHDAT[1] : Command Inhibit (DAT)
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* CMDINHDAT[1] : Command Inhibit (DAT)
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* CMDINHCMD[0] : Command Inhibit (CMD)
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* CMDINHCMD[0] : Command Inhibit (CMD)
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*/
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*/
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mask = (1 << 0);
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unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
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if ((data != NULL) || (cmd->resp_type & MMC_RSP_BUSY))
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mask |= (1 << 1);
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/*
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/*
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* We shouldn't wait for data inhibit for stop commands, even
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* We shouldn't wait for data inhibit for stop commands, even
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* though they might use busy signaling
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* though they might use busy signaling
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*/
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*/
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if (data)
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if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
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mask &= ~(1 << 1);
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mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
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while (readl(&host->reg->prnsts) & mask) {
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while (readl(&host->reg->prnsts) & mask) {
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if (timeout == 0) {
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if (timeout == 0) {
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@ -150,6 +144,24 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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udelay(1000);
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udelay(1000);
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}
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}
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return 0;
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}
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static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct mmc_host *host = (struct mmc_host *)mmc->priv;
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int flags, i;
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int result;
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unsigned int mask;
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unsigned int retry = 0x100000;
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debug(" mmc_send_cmd called\n");
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result = mmc_wait_inhibit(host, cmd, data, 10 /* ms */);
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if (result < 0)
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return result;
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if (data)
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if (data)
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mmc_prepare_data(host, data);
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mmc_prepare_data(host, data);
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@ -175,20 +187,20 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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* 11 = Length 48 Check busy after response
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* 11 = Length 48 Check busy after response
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*/
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*/
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if (!(cmd->resp_type & MMC_RSP_PRESENT))
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if (!(cmd->resp_type & MMC_RSP_PRESENT))
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flags = 0;
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flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
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else if (cmd->resp_type & MMC_RSP_136)
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else if (cmd->resp_type & MMC_RSP_136)
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flags = (1 << 0);
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flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
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else if (cmd->resp_type & MMC_RSP_BUSY)
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else if (cmd->resp_type & MMC_RSP_BUSY)
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flags = (3 << 0);
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flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
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else
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else
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flags = (2 << 0);
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flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
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if (cmd->resp_type & MMC_RSP_CRC)
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if (cmd->resp_type & MMC_RSP_CRC)
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flags |= (1 << 3);
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flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
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if (cmd->resp_type & MMC_RSP_OPCODE)
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if (cmd->resp_type & MMC_RSP_OPCODE)
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flags |= (1 << 4);
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flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
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if (data)
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if (data)
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flags |= (1 << 5);
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flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
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debug("cmd: %d\n", cmd->cmdidx);
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debug("cmd: %d\n", cmd->cmdidx);
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@ -197,7 +209,7 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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for (i = 0; i < retry; i++) {
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for (i = 0; i < retry; i++) {
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mask = readl(&host->reg->norintsts);
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mask = readl(&host->reg->norintsts);
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/* Command Complete */
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/* Command Complete */
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if (mask & (1 << 0)) {
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if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
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if (!data)
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if (!data)
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writel(mask, &host->reg->norintsts);
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writel(mask, &host->reg->norintsts);
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break;
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break;
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@ -209,11 +221,11 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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return TIMEOUT;
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return TIMEOUT;
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}
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}
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if (mask & (1 << 16)) {
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if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
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/* Timeout Error */
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/* Timeout Error */
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debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
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debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
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return TIMEOUT;
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return TIMEOUT;
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} else if (mask & (1 << 15)) {
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} else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
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/* Error Interrupt */
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/* Error Interrupt */
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debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
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debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
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return -1;
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return -1;
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@ -256,23 +268,44 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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}
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}
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if (data) {
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if (data) {
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unsigned long start = get_timer(0);
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while (1) {
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while (1) {
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mask = readl(&host->reg->norintsts);
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mask = readl(&host->reg->norintsts);
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if (mask & (1 << 15)) {
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if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
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/* Error Interrupt */
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/* Error Interrupt */
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writel(mask, &host->reg->norintsts);
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writel(mask, &host->reg->norintsts);
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printf("%s: error during transfer: 0x%08x\n",
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printf("%s: error during transfer: 0x%08x\n",
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__func__, mask);
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__func__, mask);
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return -1;
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return -1;
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} else if (mask & (1 << 3)) {
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} else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
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/* DMA Interrupt */
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/*
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* DMA Interrupt, restart the transfer where
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* it was interrupted.
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*/
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unsigned int address = readl(&host->reg->sysad);
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debug("DMA end\n");
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debug("DMA end\n");
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break;
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writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
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} else if (mask & (1 << 1)) {
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&host->reg->norintsts);
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writel(address, &host->reg->sysad);
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} else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
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/* Transfer Complete */
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/* Transfer Complete */
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debug("r/w is done\n");
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debug("r/w is done\n");
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break;
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break;
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} else if (get_timer(start) > 2000UL) {
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writel(mask, &host->reg->norintsts);
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printf("%s: MMC Timeout\n"
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" Interrupt status 0x%08x\n"
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" Interrupt status enable 0x%08x\n"
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" Interrupt signal enable 0x%08x\n"
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" Present status 0x%08x\n",
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__func__, mask,
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readl(&host->reg->norintstsen),
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readl(&host->reg->norintsigen),
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readl(&host->reg->prnsts));
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return -1;
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}
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}
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}
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}
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writel(mask, &host->reg->norintsts);
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writel(mask, &host->reg->norintsts);
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@ -310,12 +343,14 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
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* ENINTCLK[0] : Internal Clock Enable
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* ENINTCLK[0] : Internal Clock Enable
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*/
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*/
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div >>= 1;
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div >>= 1;
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clk = (div << 8) | (1 << 0);
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clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
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TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
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writew(clk, &host->reg->clkcon);
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writew(clk, &host->reg->clkcon);
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/* Wait max 10 ms */
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/* Wait max 10 ms */
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timeout = 10;
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timeout = 10;
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while (!(readw(&host->reg->clkcon) & (1 << 1))) {
|
while (!(readw(&host->reg->clkcon) &
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TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
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if (timeout == 0) {
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if (timeout == 0) {
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printf("%s: timeout error\n", __func__);
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printf("%s: timeout error\n", __func__);
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return;
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return;
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@ -324,7 +359,7 @@ static void mmc_change_clock(struct mmc_host *host, uint clock)
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udelay(1000);
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udelay(1000);
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}
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}
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clk |= (1 << 2);
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clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
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writew(clk, &host->reg->clkcon);
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writew(clk, &host->reg->clkcon);
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|
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debug("mmc_change_clock: clkcon = %08X\n", clk);
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debug("mmc_change_clock: clkcon = %08X\n", clk);
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@ -375,7 +410,7 @@ static void mmc_reset(struct mmc_host *host)
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* 1 = reset
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* 1 = reset
|
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* 0 = work
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* 0 = work
|
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*/
|
*/
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writeb((1 << 0), &host->reg->swrst);
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writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &host->reg->swrst);
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|
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host->clock = 0;
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host->clock = 0;
|
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||||||
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@ -383,7 +418,7 @@ static void mmc_reset(struct mmc_host *host)
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timeout = 100;
|
timeout = 100;
|
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|
|
||||||
/* hw clears the bit when it's done */
|
/* hw clears the bit when it's done */
|
||||||
while (readb(&host->reg->swrst) & (1 << 0)) {
|
while (readb(&host->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
|
||||||
if (timeout == 0) {
|
if (timeout == 0) {
|
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printf("%s: timeout error\n", __func__);
|
printf("%s: timeout error\n", __func__);
|
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return;
|
return;
|
||||||
|
@ -413,12 +448,17 @@ static int mmc_core_init(struct mmc *mmc)
|
||||||
* NORMAL Interrupt Status Enable Register init
|
* NORMAL Interrupt Status Enable Register init
|
||||||
* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
|
* [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
|
||||||
* [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
|
* [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
|
||||||
|
* [3] ENSTADMAINT : DMA boundary interrupt
|
||||||
* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
|
* [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
|
||||||
* [0] ENSTACMDCMPLT : Command Complete Status Enable
|
* [0] ENSTACMDCMPLT : Command Complete Status Enable
|
||||||
*/
|
*/
|
||||||
mask = readl(&host->reg->norintstsen);
|
mask = readl(&host->reg->norintstsen);
|
||||||
mask &= ~(0xffff);
|
mask &= ~(0xffff);
|
||||||
mask |= (1 << 5) | (1 << 4) | (1 << 1) | (1 << 0);
|
mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
|
||||||
|
TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
|
||||||
|
TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
|
||||||
|
TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
|
||||||
|
TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
|
||||||
writel(mask, &host->reg->norintstsen);
|
writel(mask, &host->reg->norintstsen);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -427,7 +467,7 @@ static int mmc_core_init(struct mmc *mmc)
|
||||||
*/
|
*/
|
||||||
mask = readl(&host->reg->norintsigen);
|
mask = readl(&host->reg->norintsigen);
|
||||||
mask &= ~(0xffff);
|
mask &= ~(0xffff);
|
||||||
mask |= (1 << 1);
|
mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
|
||||||
writel(mask, &host->reg->norintsigen);
|
writel(mask, &host->reg->norintsigen);
|
||||||
|
|
||||||
return 0;
|
return 0;
|
||||||
|
|
|
@ -68,6 +68,55 @@ struct tegra2_mmc {
|
||||||
unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */
|
unsigned char res6[0x100]; /* RESERVED, offset 100h-1FFh */
|
||||||
};
|
};
|
||||||
|
|
||||||
|
#define TEGRA_MMC_HOSTCTL_DMASEL_MASK (3 << 3)
|
||||||
|
#define TEGRA_MMC_HOSTCTL_DMASEL_SDMA (0 << 3)
|
||||||
|
#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT (2 << 3)
|
||||||
|
#define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT (3 << 3)
|
||||||
|
|
||||||
|
#define TEGRA_MMC_TRNMOD_DMA_ENABLE (1 << 0)
|
||||||
|
#define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE (1 << 1)
|
||||||
|
#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE (0 << 4)
|
||||||
|
#define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ (1 << 4)
|
||||||
|
#define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT (1 << 5)
|
||||||
|
|
||||||
|
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK (3 << 0)
|
||||||
|
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE (0 << 0)
|
||||||
|
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136 (1 << 0)
|
||||||
|
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48 (2 << 0)
|
||||||
|
#define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY (3 << 0)
|
||||||
|
|
||||||
|
#define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK (1 << 3)
|
||||||
|
#define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK (1 << 4)
|
||||||
|
#define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER (1 << 5)
|
||||||
|
|
||||||
|
#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD (1 << 0)
|
||||||
|
#define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT (1 << 1)
|
||||||
|
|
||||||
|
#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE (1 << 0)
|
||||||
|
#define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE (1 << 1)
|
||||||
|
#define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE (1 << 2)
|
||||||
|
|
||||||
|
#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT 8
|
||||||
|
#define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK (0xff << 8)
|
||||||
|
|
||||||
|
#define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL (1 << 0)
|
||||||
|
#define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE (1 << 1)
|
||||||
|
#define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE (1 << 2)
|
||||||
|
|
||||||
|
#define TEGRA_MMC_NORINTSTS_CMD_COMPLETE (1 << 0)
|
||||||
|
#define TEGRA_MMC_NORINTSTS_XFER_COMPLETE (1 << 1)
|
||||||
|
#define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT (1 << 3)
|
||||||
|
#define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT (1 << 15)
|
||||||
|
#define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT (1 << 16)
|
||||||
|
|
||||||
|
#define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE (1 << 0)
|
||||||
|
#define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE (1 << 1)
|
||||||
|
#define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT (1 << 3)
|
||||||
|
#define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY (1 << 4)
|
||||||
|
#define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY (1 << 5)
|
||||||
|
|
||||||
|
#define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE (1 << 1)
|
||||||
|
|
||||||
struct mmc_host {
|
struct mmc_host {
|
||||||
struct tegra2_mmc *reg;
|
struct tegra2_mmc *reg;
|
||||||
unsigned int version; /* SDHCI spec. version */
|
unsigned int version; /* SDHCI spec. version */
|
||||||
|
|
Loading…
Reference in New Issue