powerpc/t4240qds: fix offset of serdes when checking reference clock
T4240 has 4 serdes, each serdes has 4k memory space, two PLLs. We use PLL1CR0 to check the serdes reference clock. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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@ -2905,6 +2905,8 @@ struct ccsr_sfp_regs {
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#endif
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#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
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#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
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#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
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#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
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#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
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#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
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#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000
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@ -3090,6 +3092,10 @@ struct ccsr_sfp_regs {
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
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#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
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#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
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#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
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#define CONFIG_SYS_MPC85xx_USB1_ADDR \
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(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
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#define CONFIG_SYS_MPC85xx_USB2_ADDR \
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@ -644,9 +644,10 @@ unsigned long get_board_ddr_clk(void)
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int misc_init_r(void)
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{
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u8 sw;
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serdes_corenet_t *srds_regs =
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(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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void *srds_base = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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serdes_corenet_t *srds_regs;
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u32 actual[MAX_SERDES];
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u32 pllcr0, expected;
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unsigned int i;
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sw = QIXIS_READ(brdcfg[2]);
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@ -669,8 +670,9 @@ int misc_init_r(void)
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}
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for (i = 0; i < MAX_SERDES; i++) {
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u32 pllcr0 = srds_regs->bank[i].pllcr0;
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u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
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srds_regs = srds_base + i * 0x1000;
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pllcr0 = srds_regs->bank[0].pllcr0;
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expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
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if (expected != actual[i]) {
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printf("Warning: SERDES%u expects reference clock %sMHz, but actual is %sMHz\n",
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i + 1, serdes_clock_to_string(expected),
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