Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
* 'master' of git://git.denx.de/u-boot-nand-flash: NAND: davinci: choose correct 1-bit h/w ECC reg
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commit
e5a0717176
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@ -176,12 +176,22 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
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#ifdef CONFIG_SYS_NAND_HW_ECC
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#ifdef CONFIG_SYS_NAND_HW_ECC
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static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
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{
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u_int32_t ecc = 0;
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ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
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CONFIG_SYS_NAND_CS - 2]));
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return ecc;
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}
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static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
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static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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{
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u_int32_t val;
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u_int32_t val;
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(void)__raw_readl(&(davinci_emif_regs->nandfecc[
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/* reading the ECC result register resets the ECC calculation */
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CONFIG_SYS_NAND_CS - 2]));
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nand_davinci_readecc(mtd);
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val = __raw_readl(&davinci_emif_regs->nandfcr);
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val = __raw_readl(&davinci_emif_regs->nandfcr);
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val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
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val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
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@ -189,22 +199,12 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
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__raw_writel(val, &davinci_emif_regs->nandfcr);
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__raw_writel(val, &davinci_emif_regs->nandfcr);
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}
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}
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static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
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{
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u_int32_t ecc = 0;
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ecc = __raw_readl(&(davinci_emif_regs->nandfecc[region - 1]));
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return ecc;
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}
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static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
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static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
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u_char *ecc_code)
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u_char *ecc_code)
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{
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{
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u_int32_t tmp;
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u_int32_t tmp;
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const int region = 1;
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tmp = nand_davinci_readecc(mtd, region);
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tmp = nand_davinci_readecc(mtd);
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/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
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/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
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* and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
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* and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
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