mpc512x: use common code for clock setting for all mpc512x boards
Only define enabled clocks in the config file and enable the clocks in common code. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com> Cc: Wolfgang Denk <wd@denx.de>
This commit is contained in:
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676c66918a
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e5f538649c
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@ -180,6 +180,15 @@ void cpu_init_f (volatile immap_t * im)
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* during FLASH chip identification etc.
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* during FLASH chip identification etc.
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*/
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*/
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setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
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setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
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/*
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* Enable clocks
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*/
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out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
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out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
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#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
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setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
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#endif
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}
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}
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int cpu_init_r (void)
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int cpu_init_r (void)
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@ -35,39 +35,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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/* Clocks in use */
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_NFC_EN | \
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CLOCK_SCCR1_PATA_EN | \
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CLOCK_SCCR1_PCI_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN)
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int board_early_init_f(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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/*
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* Enable clocks
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*/
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out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
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out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
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#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
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setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
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#endif
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return 0;
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}
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phys_size_t initdram (int board_type)
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phys_size_t initdram (int board_type)
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{
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{
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return fixed_sdram(NULL, NULL, 0);
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return fixed_sdram(NULL, NULL, 0);
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@ -33,20 +33,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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/* Clocks in use */
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_NFC_EN | \
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CLOCK_SCCR1_PCI_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_I2C_EN)
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int eeprom_write_enable(unsigned dev_addr, int state)
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int eeprom_write_enable(unsigned dev_addr, int state)
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{
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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@ -74,15 +60,6 @@ int board_early_init_f(void)
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CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
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CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
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sync_law(&im->sysconf.lpbaw);
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sync_law(&im->sysconf.lpbaw);
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/*
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* Enable clocks
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*/
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out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
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out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
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#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
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setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
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#endif
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/*
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/*
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* Configure MSCAN clocks
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* Configure MSCAN clocks
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*/
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*/
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@ -38,25 +38,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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/* Clocks in use */
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_NFC_EN | \
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CLOCK_SCCR1_PATA_EN | \
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CLOCK_SCCR1_PCI_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN | \
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CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_USB1_EN | \
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CLOCK_SCCR2_USB2_EN)
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void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
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void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
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/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
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/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
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@ -83,8 +64,6 @@ void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
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int board_early_init_f(void)
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int board_early_init_f(void)
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{
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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/*
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/*
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* Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
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* Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
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*
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*
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@ -102,16 +81,6 @@ int board_early_init_f(void)
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out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
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out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
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}
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}
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#endif
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#endif
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/*
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* Enable clocks
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*/
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out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN);
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out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN);
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#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
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setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
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#endif
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return 0;
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return 0;
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}
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}
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@ -44,37 +44,6 @@ DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[];
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extern flash_info_t flash_info[];
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ulong flash_get_size (phys_addr_t base, int banknum);
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ulong flash_get_size (phys_addr_t base, int banknum);
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/* Clocks in use */
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_NFC_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN)
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int board_early_init_f(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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/*
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* Enable clocks
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*/
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out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
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out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
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#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
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setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
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#endif
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return 0;
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}
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sdram_conf_t mddrc_config[] = {
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sdram_conf_t mddrc_config[] = {
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{
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{
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(512 << 20), /* 512 MB RAM configuration */
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(512 << 20), /* 512 MB RAM configuration */
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@ -64,7 +64,6 @@
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#define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */
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#define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SYS_IMMR 0x80000000
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#define CONFIG_SYS_IMMR 0x80000000
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@ -648,4 +647,21 @@
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#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
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#define FSL_ATA_CTRL_DMA_WRITE 0x02000000
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#define FSL_ATA_CTRL_IORDY_EN 0x01000000
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#define FSL_ATA_CTRL_IORDY_EN 0x01000000
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/* Clocks in use */
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_NFC_EN | \
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CLOCK_SCCR1_PATA_EN | \
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CLOCK_SCCR1_PCI_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN)
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#endif /* __CONFIG_H */
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#endif /* __CONFIG_H */
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@ -242,6 +242,23 @@
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#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
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#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE
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#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
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#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR
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/*
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* Clocks in use
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*/
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_NFC_EN | \
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CLOCK_SCCR1_PCI_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_I2C_EN)
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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/* Use the HUSH parser */
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/* Use the HUSH parser */
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_HUSH_PARSER
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#ifdef CONFIG_SYS_HUSH_PARSER
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#ifdef CONFIG_SYS_HUSH_PARSER
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#endif
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#endif
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/*
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* Clocks in use
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*/
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_NFC_EN | \
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CLOCK_SCCR1_PATA_EN | \
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CLOCK_SCCR1_PCI_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN | \
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CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_USB1_EN | \
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CLOCK_SCCR2_USB2_EN)
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/*
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/*
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* PCI
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* PCI
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*/
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*/
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#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
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#define CONFIG_SYS_MPC512X_CLKIN 33333333 /* in Hz */
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R
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#define CONFIG_MISC_INIT_R
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#define CONFIG_SYS_IMMR 0x80000000
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#define CONFIG_SYS_IMMR 0x80000000
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#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC6_RX_SIZE
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#define CONSOLE_FIFO_RX_SIZE FIFOC_PSC6_RX_SIZE
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#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR
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#define CONSOLE_FIFO_RX_ADDR FIFOC_PSC6_RX_ADDR
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/*
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* Clocks in use
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*/
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#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
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CLOCK_SCCR1_LPC_EN | \
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CLOCK_SCCR1_NFC_EN | \
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CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
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CLOCK_SCCR1_PSCFIFO_EN | \
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CLOCK_SCCR1_DDR_EN | \
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CLOCK_SCCR1_FEC_EN | \
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CLOCK_SCCR1_TPR_EN)
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#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
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CLOCK_SCCR2_SPDIF_EN | \
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CLOCK_SCCR2_DIU_EN | \
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CLOCK_SCCR2_I2C_EN)
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/*
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/*
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* Used PSC UART devices
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* Used PSC UART devices
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*/
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*/
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