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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

This commit is contained in:
Tom Rini 2014-01-06 14:07:08 -05:00
parent 895ec893a9 8c618dd66a
commit e7be18225f
18 changed files with 59 additions and 12 deletions
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8
README
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@ -423,6 +423,11 @@ The following options need to be configured:
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
This value denotes start offset of DSP CCSR space. This value denotes start offset of DSP CCSR space.
CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
Single Source Clock is clocking mode present in some of FSL SoC's.
In this mode, a single differential clock is used to supply
clocks to the sysclock, ddrclock and usbclock.
- Generic CPU options: - Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
@ -3267,6 +3272,9 @@ FIT uImage format:
Defines the size and behavior of the NAND that SPL uses Defines the size and behavior of the NAND that SPL uses
to read U-Boot to read U-Boot
CONFIG_SPL_NAND_BOOT
Add support NAND boot
CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_U_BOOT_OFFS
Location in NAND to read U-Boot from Location in NAND to read U-Boot from

25
arch/powerpc/cpu/mpc85xx/speed.c
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@ -74,12 +74,33 @@ void get_sys_info(sys_info_t *sys_info)
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ; unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
uint mem_pll_rat; uint mem_pll_rat;
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
uint single_src;
#endif
sys_info->freq_systembus = sysclk; sys_info->freq_systembus = sysclk;
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
/*
* DDR_REFCLK_SEL rcw bit is used to determine if DDR PLLS
* are driven by separate DDR Refclock or single source
* differential clock.
*/
single_src = (in_be32(&gur->rcwsr[5]) >>
FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT) &
FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK;
/*
* For single source clocking, both ddrclock and syclock
* are driven by differential sysclock.
*/
if (single_src == FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK) {
printf("Single Source Clock Configuration\n");
sys_info->freq_ddrbus = CONFIG_SYS_CLK_FREQ;
} else
#endif
#ifdef CONFIG_DDR_CLK_FREQ #ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ; sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
#else #else
sys_info->freq_ddrbus = sysclk; sys_info->freq_ddrbus = sysclk;
#endif #endif
sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;

3
arch/powerpc/include/asm/config_mpc85xx.h
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@ -711,6 +711,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_FM_PLAT_CLK_DIV 1 #define CONFIG_FM_PLAT_CLK_DIV 1
#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
#define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
@ -745,7 +746,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_SYS_NUM_FM1_10GEC 2
#endif #endif
#define CONFIG_SYS_FSL_NUM_USB_CTRLS 2 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_PME_PLAT_CLK_DIV 1 #define CONFIG_PME_PLAT_CLK_DIV 1
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV

3
arch/powerpc/include/asm/immap_85xx.h
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@ -1774,6 +1774,9 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2 0x00040000
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1 0x00020000
#define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2 0x00010000
#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK 0x00000011
#define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK 1
#else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 17

2
board/freescale/b4860qds/b4_rcw.cfg
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@ -2,6 +2,6 @@
aa55aa55 010e0100 aa55aa55 010e0100
# serdes protocol 0x2A_0x98 # serdes protocol 0x2A_0x98
140e0018 0f001218 00000000 00000000 140e0018 0f001218 00000000 00000000
54980000 9000a000 f8025000 a9000000 54980000 9000a000 e8104000 a9000000
01000000 00000000 00000000 0001b1f8 01000000 00000000 00000000 0001b1f8
00000000 14000020 00000000 00000011 00000000 14000020 00000000 00000011

2
board/freescale/bsc9131rdb/tlb.c
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@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1), 0, 0, BOOKE_PAGESZ_4K, 1),
#ifdef CONFIG_SPL_NAND_MINIMAL #ifdef CONFIG_SPL_NAND_BOOT
SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_4K, 1), 0, 10, BOOKE_PAGESZ_4K, 1),

2
board/freescale/bsc9132qds/tlb.c
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@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1), 0, 0, BOOKE_PAGESZ_4K, 1),
#ifdef CONFIG_SPL_NAND_MINIMAL #ifdef CONFIG_SPL_NAND_BOOT
SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_4K, 1), 0, 10, BOOKE_PAGESZ_4K, 1),

2
board/freescale/p1010rdb/tlb.c
View File

@ -30,7 +30,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1), 0, 0, BOOKE_PAGESZ_4K, 1),
#ifdef CONFIG_SPL_NAND_MINIMAL #ifdef CONFIG_SPL_NAND_BOOT
SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_4K, 1), 0, 10, BOOKE_PAGESZ_4K, 1),

2
board/freescale/t1040qds/t1040_pbi.cfg
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@ -3,7 +3,7 @@
09010000 00200400 09010000 00200400
09138000 00000000 09138000 00000000
091380c0 00000100 091380c0 00000100
#Configure CPC1 as 512KB SRAM #Configure CPC1 as 256KB SRAM
09010100 00000000 09010100 00000000
09010104 fffc0007 09010104 fffc0007
09010f00 08000000 09010f00 08000000

5
board/freescale/t1040qds/t1040qds.c
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@ -239,3 +239,8 @@ void qixis_dump_switch(void)
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1])); printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
} }
} }
int board_need_mem_reset(void)
{
return 1;
}

1
boards.cfg
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@ -965,6 +965,7 @@ Active powerpc mpc85xx - freescale t4qds
Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4160QDS_SPIFLASH T4240QDS:PPC_T4160,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun@freescale.com> Active powerpc mpc85xx - freescale t4qds T4240EMU T4240EMU:PPC_T4240 York Sun <yorksun@freescale.com>
Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 - Active powerpc mpc85xx - freescale t4qds T4240QDS T4240QDS:PPC_T4240 -
Active powerpc mpc85xx - freescale t4qds T4240QDS_NAND T4240QDS:PPC_T4240,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SDCARD T4240QDS:PPC_T4240,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SPIFLASH T4240QDS:PPC_T4240,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 -
Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 - Active powerpc mpc85xx - freescale t4qds T4240QDS_SRIO_PCIE_BOOT T4240QDS:PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 -

2
include/configs/B4860QDS.h
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@ -289,6 +289,8 @@ unsigned long get_board_ddr_clk(void);
/* NAND Flash on IFC */ /* NAND Flash on IFC */
#define CONFIG_NAND_FSL_IFC #define CONFIG_NAND_FSL_IFC
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_BASE 0xff800000 #define CONFIG_SYS_NAND_BASE 0xff800000
#ifdef CONFIG_PHYS_64BIT #ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) #define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)

2
include/configs/BSC9131RDB.h
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@ -29,7 +29,7 @@
#define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_MINIMAL #define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"

2
include/configs/BSC9132QDS.h
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@ -38,7 +38,7 @@
#define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_MINIMAL #define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"

3
include/configs/CMS700.h
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@ -149,6 +149,9 @@
#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
#define CONFIG_SYS_NAND_QUIET 1 #define CONFIG_SYS_NAND_QUIET 1
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
#define CONFIG_SYS_NAND_MAX_ECCPOS 48
/* /*
* For booting Linux, the board info and command line data * For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is * have to be in the first 8 MB of memory, since this is

2
include/configs/P1010RDB.h
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@ -37,7 +37,7 @@
#define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_INIT_MINIMAL
#define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_MINIMAL #define CONFIG_SPL_NAND_BOOT
#define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_FLUSH_IMAGE
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"

2
include/configs/P1022DS.h
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@ -75,6 +75,8 @@
#endif #endif
#define CONFIG_NAND_FSL_ELBC #define CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_NAND_MAX_ECCPOS 56
#define CONFIG_SYS_NAND_MAX_OOBFREE 5
#ifdef CONFIG_NAND #ifdef CONFIG_NAND
#define CONFIG_SPL #define CONFIG_SPL

3
include/configs/T1040QDS.h
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@ -233,6 +233,7 @@ unsigned long get_board_ddr_clk(void);
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_RST_FORCE_MEM 0x01
#define CONFIG_SYS_CSPR3_EXT (0xf) #define CONFIG_SYS_CSPR3_EXT (0xf)
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
@ -248,7 +249,7 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f)) FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
FTIM2_GPCM_TCH(0x0) | \ FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f)) FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS3_FTIM3 0x0 #define CONFIG_SYS_CS3_FTIM3 0x0