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x86: qemu: Enable I/O APIC chip select on PIIX3 

The PIIX3 chipset does not integrate an I/O APIC, instead it supports
connecting to an external I/O APIC which needs to be enabled manually.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2015-07-22 01:21:11 -07:00 committed by Simon Glass
parent 53832bb8d6
commit e7cd070da6
2 changed files with 11 additions and 2 deletions
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7
arch/x86/cpu/qemu/pci.c
View File

@ -50,7 +50,7 @@ void board_pci_setup_hose(struct pci_controller *hose)
int board_pci_post_scan(struct pci_controller *hose)
{
int ret = 0;
u16 device;
u16 device, xbcs;
int pam, i;
pci_dev_t vga;
ulong start;
@ -82,6 +82,11 @@ int board_pci_post_scan(struct pci_controller *hose)
*/
x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
/* Enable I/O APIC */
xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
xbcs |= APIC_EN;
x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
}
/*

6
arch/x86/include/asm/arch-qemu/qemu.h
View File

@ -13,10 +13,14 @@
#define PAM_NUM 7
#define PAM_RW 0x33
/* X-Bus Chip Select Register */
#define XBCS 0x4e
#define APIC_EN (1 << 8)
/* IDE Timing Register */
#define IDE0_TIM 0x40
#define IDE1_TIM 0x42
#define IDE_DECODE_EN 0x8000
#define IDE_DECODE_EN (1 << 15)
/* I/O Ports */
#define CMOS_ADDR_PORT 0x70