x86: qemu: Enable I/O APIC chip select on PIIX3
The PIIX3 chipset does not integrate an I/O APIC, instead it supports connecting to an external I/O APIC which needs to be enabled manually. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
parent
53832bb8d6
commit
e7cd070da6
|
@ -50,7 +50,7 @@ void board_pci_setup_hose(struct pci_controller *hose)
|
||||||
int board_pci_post_scan(struct pci_controller *hose)
|
int board_pci_post_scan(struct pci_controller *hose)
|
||||||
{
|
{
|
||||||
int ret = 0;
|
int ret = 0;
|
||||||
u16 device;
|
u16 device, xbcs;
|
||||||
int pam, i;
|
int pam, i;
|
||||||
pci_dev_t vga;
|
pci_dev_t vga;
|
||||||
ulong start;
|
ulong start;
|
||||||
|
@ -82,6 +82,11 @@ int board_pci_post_scan(struct pci_controller *hose)
|
||||||
*/
|
*/
|
||||||
x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
|
x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN);
|
||||||
x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
|
x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN);
|
||||||
|
|
||||||
|
/* Enable I/O APIC */
|
||||||
|
xbcs = x86_pci_read_config16(PIIX_ISA, XBCS);
|
||||||
|
xbcs |= APIC_EN;
|
||||||
|
x86_pci_write_config16(PIIX_ISA, XBCS, xbcs);
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -13,10 +13,14 @@
|
||||||
#define PAM_NUM 7
|
#define PAM_NUM 7
|
||||||
#define PAM_RW 0x33
|
#define PAM_RW 0x33
|
||||||
|
|
||||||
|
/* X-Bus Chip Select Register */
|
||||||
|
#define XBCS 0x4e
|
||||||
|
#define APIC_EN (1 << 8)
|
||||||
|
|
||||||
/* IDE Timing Register */
|
/* IDE Timing Register */
|
||||||
#define IDE0_TIM 0x40
|
#define IDE0_TIM 0x40
|
||||||
#define IDE1_TIM 0x42
|
#define IDE1_TIM 0x42
|
||||||
#define IDE_DECODE_EN 0x8000
|
#define IDE_DECODE_EN (1 << 15)
|
||||||
|
|
||||||
/* I/O Ports */
|
/* I/O Ports */
|
||||||
#define CMOS_ADDR_PORT 0x70
|
#define CMOS_ADDR_PORT 0x70
|
||||||
|
|
Loading…
Reference in New Issue