ARM: uniphier: add PSCI support for UniPhier ARMv7 SoCs
Currently, only the CPU_ON function is supported. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada
parent
ee9bc77f3a
commit
e8a9293295
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@ -6,6 +6,8 @@ config SYS_CONFIG_NAME
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config ARCH_UNIPHIER_32BIT
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bool
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select CPU_V7
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select CPU_V7_HAS_NONSEC
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select ARMV7_NONSEC
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config ARCH_UNIPHIER_64BIT
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bool
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@ -8,6 +8,7 @@ obj-$(CONFIG_DEBUG_LL) += debug_ll.o
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else
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obj-y += late_lowlevel_init.o
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obj-y += cache-uniphier.o
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obj-$(CONFIG_ARMV7_PSCI) += psci.o psci_smp.o
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endif
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obj-y += timer.o
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@ -12,6 +12,9 @@
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/* SCU Control Register */
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#define SCU_CTRL 0x00
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#define SCU_ENABLE (1 << 0)
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#define SCU_STANDBY_ENABLE (1 << 5)
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/* SCU Configuration Register */
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#define SCU_CONF 0x04
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/* SCU CPU Power Status Register */
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@ -0,0 +1,153 @@
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/psci.h>
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#include <linux/sizes.h>
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#include <asm/processor.h>
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#include <asm/psci.h>
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#include <asm/secure.h>
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#include "../debug.h"
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#include "../soc-info.h"
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#include "arm-mpcore.h"
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#include "cache-uniphier.h"
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#define UNIPHIER_SMPCTRL_ROM_RSV2 0x59801208
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void uniphier_smp_trampoline(void);
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void uniphier_smp_trampoline_end(void);
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u32 uniphier_smp_booted[CONFIG_ARMV7_PSCI_NR_CPUS];
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static int uniphier_get_nr_cpus(void)
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{
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switch (uniphier_get_soc_type()) {
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case SOC_UNIPHIER_SLD3:
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case SOC_UNIPHIER_PRO4:
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case SOC_UNIPHIER_PRO5:
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return 2;
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case SOC_UNIPHIER_PXS2:
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case SOC_UNIPHIER_LD6B:
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return 4;
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default:
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return 1;
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}
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}
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static void uniphier_smp_kick_all_cpus(void)
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{
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const u32 target_ways = BIT(0);
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size_t trmp_size;
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u32 trmp_src = (unsigned long)uniphier_smp_trampoline;
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u32 trmp_src_end = (unsigned long)uniphier_smp_trampoline_end;
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u32 trmp_dest, trmp_dest_end;
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int nr_cpus, i;
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int timeout = 1000;
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nr_cpus = uniphier_get_nr_cpus();
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if (nr_cpus == 1)
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return;
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for (i = 0; i < nr_cpus; i++) /* lock ways for all CPUs */
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uniphier_cache_set_active_ways(i, 0);
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uniphier_cache_inv_way(target_ways);
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uniphier_cache_enable();
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/* copy trampoline code */
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uniphier_cache_prefetch_range(trmp_src, trmp_src_end, target_ways);
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trmp_size = trmp_src_end - trmp_src;
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trmp_dest = trmp_src & (SZ_64K - 1);
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trmp_dest += SZ_1M - SZ_64K * 2;
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trmp_dest_end = trmp_dest + trmp_size;
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uniphier_cache_touch_range(trmp_dest, trmp_dest_end, target_ways);
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writel(trmp_dest, UNIPHIER_SMPCTRL_ROM_RSV2);
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asm("dsb ishst\n" /* Ensure the write to ROM_RSV2 is visible */
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"sev"); /* Bring up all secondary CPUs from Boot ROM into U-Boot */
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while (--timeout) {
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int all_booted = 1;
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for (i = 1; i < nr_cpus; i++)
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if (!uniphier_smp_booted[i])
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all_booted = 0;
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if (all_booted)
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break;
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udelay(1);
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/* barrier here because uniphier_smp_booted[] may be updated */
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cpu_relax();
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}
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if (!timeout)
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printf("warning: some of secondary CPUs may not boot\n");
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uniphier_cache_disable();
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}
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void psci_board_init(void)
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{
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unsigned long scu_base;
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u32 scu_ctrl, tmp;
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (scu_base));
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scu_ctrl = readl(scu_base + 0x30);
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if (!(scu_ctrl & 1))
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writel(scu_ctrl | 0x1, scu_base + 0x30);
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scu_ctrl = readl(scu_base + SCU_CTRL);
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scu_ctrl |= SCU_ENABLE | SCU_STANDBY_ENABLE;
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writel(scu_ctrl, scu_base + SCU_CTRL);
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tmp = readl(scu_base + SCU_SNSAC);
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tmp |= 0xfff;
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writel(tmp, scu_base + SCU_SNSAC);
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uniphier_smp_kick_all_cpus();
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}
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void psci_arch_init(void)
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{
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u32 actlr;
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asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
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actlr |= 0x41; /* set SMP and FW bits */
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asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
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}
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u32 uniphier_psci_holding_pen_release __secure_data = 0xffffffff;
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int __secure psci_cpu_on(u32 function_id, u32 cpuid, u32 entry_point)
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{
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u32 cpu = cpuid & 0xff;
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debug_puts("[U-Boot PSCI] psci_cpu_on: cpuid=");
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debug_puth(cpuid);
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debug_puts(", entry_point=");
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debug_puth(entry_point);
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debug_puts("\n");
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psci_save_target_pc(cpu, entry_point);
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/* We assume D-cache is off, so do not call flush_dcache() here */
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uniphier_psci_holding_pen_release = cpu;
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/* Send an event to wake up the secondary CPU. */
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asm("dsb ishst\n"
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"sev");
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return PSCI_RET_SUCCESS;
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}
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@ -0,0 +1,40 @@
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/linkage.h>
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#include <asm/system.h>
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.section ._secure.text, "ax"
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ENTRY(uniphier_smp_trampoline)
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ldr r0, 0f
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mrc p15, 0, r1, c1, c0, 0 @ SCTLR (System Control Register)
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orr r1, r1, #CR_I @ Enable ICache
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bic r1, r1, #(CR_C | CR_M) @ Disable MMU and Dcache
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mcr p15, 0, r1, c1, c0, 0
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bx r0
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0: .word uniphier_secondary_startup
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.globl uniphier_smp_trampoline_end
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uniphier_smp_trampoline_end:
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ENDPROC(uniphier_smp_trampoline)
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LENTRY(uniphier_secondary_startup)
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mrc p15, 0, r1, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
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and r1, r1, #0xff
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ldr r2, =uniphier_smp_booted
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mov r0, #1
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str r0, [r2, r1, lsl #2]
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ldr r2, =uniphier_psci_holding_pen_release
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pen: ldr r0, [r2]
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cmp r0, r1
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beq psci_cpu_entry
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wfe
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b pen
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ENDPROC(uniphier_secondary_startup)
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@ -0,0 +1,68 @@
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DEBUG_H__
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#define __DEBUG_H__
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#include <linux/io.h>
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#include <linux/serial_reg.h>
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#define DEBUG_UART_BASE 0x54006800
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#define UART_SHIFT 2
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#define UNIPHIER_UART_TX 0
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#define UNIPHIER_UART_LSR (5 * 4)
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/* All functions are inline so that they can be called from .secure section. */
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#ifdef DEBUG
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static inline void debug_putc(int c)
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{
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void __iomem *base = (void __iomem *)DEBUG_UART_BASE;
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while (!(readl(base + UNIPHIER_UART_LSR) & UART_LSR_THRE))
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;
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writel(c, base + UNIPHIER_UART_TX);
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}
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static inline void debug_puts(const char *s)
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{
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while (*s) {
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if (*s == '\n')
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debug_putc('\r');
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debug_putc(*s++);
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}
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}
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static inline void debug_puth(unsigned long val)
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{
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int i;
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unsigned char c;
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for (i = 8; i--; ) {
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c = ((val >> (i * 4)) & 0xf);
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c += (c >= 10) ? 'a' - 10 : '0';
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debug_putc(c);
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}
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}
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#else
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static inline void debug_putc(int c)
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{
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}
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static inline void debug_puts(const char *s)
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{
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}
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static inline void debug_puth(unsigned long val)
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{
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}
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#endif
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#endif /* __DEBUG_H__ */
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@ -1,7 +1,8 @@
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/*
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* UniPhier SBC (System Bus Controller) registers
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*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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* Copyright (C) 2011-2014 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -75,7 +76,6 @@
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#define SBCTRL74 (SBCTRL_BASE + 0x170)
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#define PC0CTRL 0x598000c0
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#define ROM_BOOT_ROMRSV2 0x59801208
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#ifndef __ASSEMBLY__
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#include <linux/io.h>
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@ -1,5 +1,7 @@
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/*
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* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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* Copyright (C) 2012-2015 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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@ -9,6 +11,9 @@
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#ifndef __CONFIG_UNIPHIER_COMMON_H__
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#define __CONFIG_UNIPHIER_COMMON_H__
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#define CONFIG_ARMV7_PSCI
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#define CONFIG_ARMV7_PSCI_NR_CPUS 4
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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#define CONFIG_SMC911X
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