Merge git://git.denx.de/u-boot-marvell
This commit is contained in:
Tom Rini
commit
e8d124fae0
14
Makefile
14
Makefile
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|
@ -901,7 +901,7 @@ MKIMAGEFLAGS_u-boot.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
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-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
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MKIMAGEFLAGS_u-boot-spl.kwb = -n $(srctree)/$(CONFIG_SYS_KWD_CONFIG:"%"=%) \
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-T kwbimage -a $(CONFIG_SPL_TEXT_BASE) -e $(CONFIG_SPL_TEXT_BASE)
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-T kwbimage -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE)
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||||
MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
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-R $(srctree)/$(CONFIG_SYS_FSL_PBL_PBI:"%"=%) -T pblimage
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@ -909,8 +909,18 @@ MKIMAGEFLAGS_u-boot.pbl = -n $(srctree)/$(CONFIG_SYS_FSL_PBL_RCW:"%"=%) \
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u-boot.img u-boot.kwb u-boot.pbl: u-boot.bin FORCE
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$(call if_changed,mkimage)
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u-boot-spl.kwb: u-boot.img spl/u-boot-spl.bin FORCE
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# If the kwboot xmodem protocol is used, to boot U-Boot on the MVEBU
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# SoC's, the SPL U-Boot returns to the BootROM after it completes
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# the SDRAM setup. The BootROM expects no U-Boot header in the main
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# U-Boot image. So we need to combine SPL and u-boot.bin instead of
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# u-boot.img in this case.
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ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
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u-boot-spl.kwb: u-boot-dtb.bin spl/u-boot-spl.bin FORCE
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$(call if_changed,mkimage)
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else
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u-boot-spl.kwb: u-boot-dtb.img spl/u-boot-spl.bin FORCE
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$(call if_changed,mkimage)
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endif
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MKIMAGEFLAGS_u-boot-dtb.img = $(MKIMAGEFLAGS_u-boot.img)
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@ -105,20 +105,14 @@ config KIRKWOOD
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bool "Marvell Kirkwood"
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select CPU_ARM926EJS
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config TARGET_DB_88F6820_GP
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bool "Support DB-88F6820-GP"
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_DB_MV784MP_GP
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bool "Support db-mv784mp-gp"
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select CPU_V7
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select SUPPORT_SPL
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config TARGET_MAXBCM
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bool "Support maxbcm"
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config ARCH_MVEBU
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bool "Marvell MVEBU family (Armada XP/38x)"
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select CPU_V7
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select SUPPORT_SPL
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select OF_CONTROL
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select OF_SEPARATE
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select DM
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select DM_SERIAL
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config TARGET_DEVKIT3250
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bool "Support devkit3250"
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@ -686,6 +680,8 @@ source "arch/arm/mach-keystone/Kconfig"
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source "arch/arm/mach-kirkwood/Kconfig"
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source "arch/arm/mach-mvebu/Kconfig"
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source "arch/arm/cpu/armv7/mx7/Kconfig"
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source "arch/arm/cpu/armv7/mx6/Kconfig"
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@ -41,6 +41,11 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \
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tegra210-p2371-0000.dtb \
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tegra210-p2371-2180.dtb \
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tegra210-p2571.dtb
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dtb-$(CONFIG_ARCH_MVEBU) += \
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armada-388-gp.dtb \
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armada-xp-gp.dtb
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dtb-$(CONFIG_ARCH_UNIPHIER) += \
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uniphier-ph1-ld4-ref.dtb \
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uniphier-ph1-ld6b-ref.dtb \
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@ -0,0 +1,333 @@
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/*
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* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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||||
* Ben Dooks <ben.dooks@codethink.co.uk>
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||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
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||||
* This file contains the definitions that are common to the Armada
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* 370 and Armada XP SoC.
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*/
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/include/ "skeleton64.dtsi"
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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/ {
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model = "Marvell Armada 370 and XP SoC";
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compatible = "marvell,armada-370-xp";
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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||||
compatible = "marvell,sheeva-v7";
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device_type = "cpu";
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||||
reg = <0>;
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||||
};
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};
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pmu {
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||||
compatible = "arm,cortex-a9-pmu";
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interrupts-extended = <&mpic 3>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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interrupt-parent = <&mpic>;
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pcie-mem-aperture = <0xf8000000 0x7e00000>;
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pcie-io-aperture = <0xffe00000 0x100000>;
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devbus-bootcs {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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||||
status = "disabled";
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||||
};
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devbus-cs0 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs1 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs2 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus-cs3 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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internal-regs {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
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|
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rtc@10300 {
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compatible = "marvell,orion-rtc";
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reg = <0x10300 0x20>;
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interrupts = <50>;
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};
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spi0: spi@10600 {
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reg = <0x10600 0x28>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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interrupts = <30>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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|
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spi1: spi@10680 {
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reg = <0x10680 0x28>;
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <1>;
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interrupts = <92>;
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clocks = <&coreclk 0>;
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status = "disabled";
|
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};
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i2c0: i2c@11000 {
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compatible = "marvell,mv64xxx-i2c";
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#address-cells = <1>;
|
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#size-cells = <0>;
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interrupts = <31>;
|
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
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i2c1: i2c@11100 {
|
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compatible = "marvell,mv64xxx-i2c";
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#address-cells = <1>;
|
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#size-cells = <0>;
|
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interrupts = <32>;
|
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timeout-ms = <1000>;
|
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clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@12000 {
|
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compatible = "snps,dw-apb-uart";
|
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reg = <0x12000 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <41>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@12100 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12100 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <42>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pin-ctrl@18000 {
|
||||
reg = <0x18000 0x38>;
|
||||
};
|
||||
|
||||
coredivclk: corediv-clock@18740 {
|
||||
compatible = "marvell,armada-370-corediv-clock";
|
||||
reg = <0x18740 0xc>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&mainpll>;
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
|
||||
mbusc: mbus-controller@20000 {
|
||||
compatible = "marvell,mbus-controller";
|
||||
reg = <0x20000 0x100>, <0x20180 0x20>,
|
||||
<0x20250 0x8>;
|
||||
};
|
||||
|
||||
mpic: interrupt-controller@20a00 {
|
||||
compatible = "marvell,mpic";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
};
|
||||
|
||||
coherency-fabric@20200 {
|
||||
compatible = "marvell,coherency-fabric";
|
||||
reg = <0x20200 0xb0>, <0x21010 0x1c>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
reg = <0x20300 0x30>, <0x21040 0x30>;
|
||||
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
reg = <0x20300 0x34>, <0x20704 0x4>;
|
||||
};
|
||||
|
||||
pmsu@22000 {
|
||||
compatible = "marvell,armada-370-pmsu";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x50000 0x500>;
|
||||
interrupts = <45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@51000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x51000 0x500>;
|
||||
interrupts = <46>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eth0: ethernet@70000 {
|
||||
reg = <0x70000 0x4000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&gateclk 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0x72004 0x4>;
|
||||
clocks = <&gateclk 4>;
|
||||
};
|
||||
|
||||
eth1: ethernet@74000 {
|
||||
reg = <0x74000 0x4000>;
|
||||
interrupts = <10>;
|
||||
clocks = <&gateclk 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata@a0000 {
|
||||
compatible = "marvell,armada-370-sata";
|
||||
reg = <0xa0000 0x5000>;
|
||||
interrupts = <55>;
|
||||
clocks = <&gateclk 15>, <&gateclk 30>;
|
||||
clock-names = "0", "1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
compatible = "marvell,armada370-nand";
|
||||
reg = <0xd0000 0x54>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <113>;
|
||||
clocks = <&coredivclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mvsdio@d4000 {
|
||||
compatible = "marvell,orion-sdio";
|
||||
reg = <0xd4000 0x200>;
|
||||
interrupts = <54>;
|
||||
clocks = <&gateclk 17>;
|
||||
bus-width = <4>;
|
||||
cap-sdio-irq;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
/* 2 GHz fixed main PLL */
|
||||
mainpll: mainpll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <2000000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada 380 SoC.
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "armada-38x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 380 family SoC";
|
||||
compatible = "marvell,armada380";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-380-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6810-pinctrl";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-370-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
|
||||
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
|
||||
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
|
||||
|
||||
/* x1 port */
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada 385 SoC.
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "armada-38x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 385 family SoC";
|
||||
compatible = "marvell,armada385", "marvell,armada380";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-380-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6820-pinctrl";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-370-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
|
||||
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
|
||||
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
|
||||
|
||||
/*
|
||||
* This port can be either x4 or x1. When
|
||||
* configured in x4 by the bootloader, then
|
||||
* pcie@4,0 is not available.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* x1 port only available when pcie@1,0 is
|
||||
* configured as a x1 port
|
||||
*/
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,413 @@
|
|||
/*
|
||||
* Device Tree file for Marvell Armada 385 development board
|
||||
* (RD-88F6820-GP)
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-388.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 385 GP";
|
||||
compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000>; /* 2 GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
spi@10600 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
/*
|
||||
* The EEPROM located at adresse 54 is needed
|
||||
* for the boot - DO NOT ERASE IT -
|
||||
*/
|
||||
|
||||
expander0: pca9555@20 {
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pca0_pins>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x20>;
|
||||
};
|
||||
|
||||
expander1: pca9555@21 {
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x21>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
serial@12000 {
|
||||
/*
|
||||
* Exported on the micro USB connector CON16
|
||||
* through an FTDI
|
||||
*/
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* GE1 CON15 */
|
||||
ethernet@30000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ge1_rgmii_pins>;
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
/* CON4 */
|
||||
usb@58000 {
|
||||
vcc-supply = <®_usb2_0_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* GE0 CON1 */
|
||||
ethernet@70000 {
|
||||
pinctrl-names = "default";
|
||||
/*
|
||||
* The Reference Clock 0 is used to provide a
|
||||
* clock to the PHY
|
||||
*/
|
||||
pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
|
||||
mdio@72004 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sata@a8000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sata0: sata-port@0 {
|
||||
reg = <0>;
|
||||
target-supply = <®_5v_sata0>;
|
||||
};
|
||||
|
||||
sata1: sata-port@1 {
|
||||
reg = <1>;
|
||||
target-supply = <®_5v_sata1>;
|
||||
};
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sata2: sata-port@0 {
|
||||
reg = <0>;
|
||||
target-supply = <®_5v_sata2>;
|
||||
};
|
||||
|
||||
sata3: sata-port@1 {
|
||||
reg = <1>;
|
||||
target-supply = <®_5v_sata3>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@d8000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhci_pins>;
|
||||
cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
|
||||
no-1-8-v;
|
||||
wp-inverted;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON5 */
|
||||
usb3@f0000 {
|
||||
vcc-supply = <®_usb2_1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON7 */
|
||||
usb3@f8000 {
|
||||
vcc-supply = <®_usb3_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
/*
|
||||
* One PCIe units is accessible through
|
||||
* standard PCIe slot on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* The two other PCIe units are accessible
|
||||
* through mini PCIe slot on the board.
|
||||
*/
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@3,0 {
|
||||
/* Port 2, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-fan {
|
||||
compatible = "gpio-fan";
|
||||
gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
|
||||
gpio-fan,speed-map = < 0 0
|
||||
3000 1>;
|
||||
};
|
||||
};
|
||||
|
||||
reg_usb3_vbus: usb3-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb3-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_usb2_0_vbus: v5-vbus0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-vbus0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_usb2_1_vbus: v5-vbus1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-vbus1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_usb2_1_vbus: v5-vbus1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-vbus1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_sata0: pwr-sata0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata0";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
|
||||
};
|
||||
|
||||
reg_5v_sata0: v5-sata0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata0>;
|
||||
};
|
||||
|
||||
reg_12v_sata0: v12-sata0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata0>;
|
||||
};
|
||||
|
||||
reg_sata1: pwr-sata1 {
|
||||
regulator-name = "pwr_en_sata1";
|
||||
compatible = "regulator-fixed";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_5v_sata1: v5-sata1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata1>;
|
||||
};
|
||||
|
||||
reg_12v_sata1: v12-sata1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata1";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata1>;
|
||||
};
|
||||
|
||||
reg_sata2: pwr-sata2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata2";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_5v_sata2: v5-sata2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata2";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata2>;
|
||||
};
|
||||
|
||||
reg_12v_sata2: v12-sata2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata2";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata2>;
|
||||
};
|
||||
|
||||
reg_sata3: pwr-sata3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata3";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_5v_sata3: v5-sata3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata3";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata3>;
|
||||
};
|
||||
|
||||
reg_12v_sata3: v12-sata3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata3";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata3>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pca0_pins: pca0_pins {
|
||||
marvell,pins = "mpp18";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada 388 SoC.
|
||||
*
|
||||
* Copyright (C) 2015 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*
|
||||
* The main difference with the Armada 385 is that the 388 can handle two more
|
||||
* SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl
|
||||
* property and the name of the SoC, and add the second SATA host which control
|
||||
* the 2 other ports.
|
||||
*/
|
||||
|
||||
#include "armada-385.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 388 family SoC";
|
||||
compatible = "marvell,armada388", "marvell,armada385",
|
||||
"marvell,armada380";
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6828-pinctrl";
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xe0000 0x2000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,600 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada 38x family of SoCs.
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 38x family SoC";
|
||||
compatible = "marvell,armada380";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts-extended = <&mpic 3>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "marvell,armada380-mbus", "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
controller = <&mbusc>;
|
||||
interrupt-parent = <&gic>;
|
||||
pcie-mem-aperture = <0xe0000000 0x8000000>;
|
||||
pcie-io-aperture = <0xe8000000 0x100000>;
|
||||
|
||||
bootrom {
|
||||
compatible = "marvell,bootrom";
|
||||
reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
|
||||
};
|
||||
|
||||
devbus-bootcs {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs0 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs1 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs2 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs3 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
|
||||
|
||||
L2: cache-controller@8000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x8000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
scu@c000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0xc000 0x58>;
|
||||
};
|
||||
|
||||
timer@c600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xc600 0x20>;
|
||||
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
|
||||
clocks = <&coreclk 2>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@d000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0xd000 0x1000>,
|
||||
<0xc100 0x100>;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-380-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <0x10600 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-380-spi",
|
||||
"marvell,orion-spi";
|
||||
reg = <0x10680 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11100 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11100 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12000 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@12100 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12100 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@18000 {
|
||||
reg = <0x18000 0x20>;
|
||||
|
||||
ge0_rgmii_pins: ge-rgmii-pins-0 {
|
||||
marvell,pins = "mpp6", "mpp7", "mpp8",
|
||||
"mpp9", "mpp10", "mpp11",
|
||||
"mpp12", "mpp13", "mpp14",
|
||||
"mpp15", "mpp16", "mpp17";
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
|
||||
ge1_rgmii_pins: ge-rgmii-pins-1 {
|
||||
marvell,pins = "mpp21", "mpp27", "mpp28",
|
||||
"mpp29", "mpp30", "mpp31",
|
||||
"mpp32", "mpp37", "mpp38",
|
||||
"mpp39", "mpp40", "mpp41";
|
||||
marvell,function = "ge1";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c-pins-0 {
|
||||
marvell,pins = "mpp2", "mpp3";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
|
||||
mdio_pins: mdio-pins {
|
||||
marvell,pins = "mpp4", "mpp5";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
|
||||
ref_clk0_pins: ref-clk-pins-0 {
|
||||
marvell,pins = "mpp45";
|
||||
marvell,function = "ref";
|
||||
};
|
||||
|
||||
ref_clk1_pins: ref-clk-pins-1 {
|
||||
marvell,pins = "mpp46";
|
||||
marvell,function = "ref";
|
||||
};
|
||||
|
||||
spi0_pins: spi-pins-0 {
|
||||
marvell,pins = "mpp22", "mpp23", "mpp24",
|
||||
"mpp25";
|
||||
marvell,function = "spi0";
|
||||
};
|
||||
|
||||
spi1_pins: spi-pins-1 {
|
||||
marvell,pins = "mpp56", "mpp57", "mpp58",
|
||||
"mpp59";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
uart0_pins: uart-pins-0 {
|
||||
marvell,pins = "mpp0", "mpp1";
|
||||
marvell,function = "ua0";
|
||||
};
|
||||
|
||||
uart1_pins: uart-pins-1 {
|
||||
marvell,pins = "mpp19", "mpp20";
|
||||
marvell,function = "ua1";
|
||||
};
|
||||
|
||||
sdhci_pins: sdhci-pins {
|
||||
marvell,pins = "mpp48", "mpp49", "mpp50",
|
||||
"mpp52", "mpp53", "mpp54",
|
||||
"mpp55", "mpp57", "mpp58",
|
||||
"mpp59";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
|
||||
sata0_pins: sata-pins-0 {
|
||||
marvell,pins = "mpp20";
|
||||
marvell,function = "sata0";
|
||||
};
|
||||
|
||||
sata1_pins: sata-pins-1 {
|
||||
marvell,pins = "mpp19";
|
||||
marvell,function = "sata1";
|
||||
};
|
||||
|
||||
sata2_pins: sata-pins-2 {
|
||||
marvell,pins = "mpp47";
|
||||
marvell,function = "sata2";
|
||||
};
|
||||
|
||||
sata3_pins: sata-pins-3 {
|
||||
marvell,pins = "mpp44";
|
||||
marvell,function = "sata3";
|
||||
};
|
||||
};
|
||||
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <28>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
system-controller@18200 {
|
||||
compatible = "marvell,armada-380-system-controller",
|
||||
"marvell,armada-370-xp-system-controller";
|
||||
reg = <0x18200 0x100>;
|
||||
};
|
||||
|
||||
gateclk: clock-gating-control@18220 {
|
||||
compatible = "marvell,armada-380-gating-clock";
|
||||
reg = <0x18220 0x4>;
|
||||
clocks = <&coreclk 0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
coreclk: mvebu-sar@18600 {
|
||||
compatible = "marvell,armada-380-core-clock";
|
||||
reg = <0x18600 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mbusc: mbus-controller@20000 {
|
||||
compatible = "marvell,mbus-controller";
|
||||
reg = <0x20000 0x100>, <0x20180 0x20>;
|
||||
};
|
||||
|
||||
mpic: interrupt-controller@20a00 {
|
||||
compatible = "marvell,mpic";
|
||||
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "marvell,armada-380-timer",
|
||||
"marvell,armada-xp-timer";
|
||||
reg = <0x20300 0x30>, <0x21040 0x30>;
|
||||
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&mpic 5>,
|
||||
<&mpic 6>;
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
compatible = "marvell,armada-380-wdt";
|
||||
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
cpurst@20800 {
|
||||
compatible = "marvell,armada-370-cpu-reset";
|
||||
reg = <0x20800 0x10>;
|
||||
};
|
||||
|
||||
mpcore-soc-ctrl@20d20 {
|
||||
compatible = "marvell,armada-380-mpcore-soc-ctrl";
|
||||
reg = <0x20d20 0x6c>;
|
||||
};
|
||||
|
||||
coherency-fabric@21010 {
|
||||
compatible = "marvell,armada-380-coherency-fabric";
|
||||
reg = <0x21010 0x1c>;
|
||||
};
|
||||
|
||||
pmsu@22000 {
|
||||
compatible = "marvell,armada-380-pmsu";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
|
||||
eth1: ethernet@30000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x30000 0x4000>;
|
||||
interrupts-extended = <&mpic 10>;
|
||||
clocks = <&gateclk 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eth2: ethernet@34000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x34000 0x4000>;
|
||||
interrupts-extended = <&mpic 12>;
|
||||
clocks = <&gateclk 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@58000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x58000 0x500>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 18>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xor@60800 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60800 0x100
|
||||
0x60a00 0x100>;
|
||||
clocks = <&gateclk 22>;
|
||||
status = "okay";
|
||||
|
||||
xor00 {
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
xor@60900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60900 0x100
|
||||
0x60b00 0x100>;
|
||||
clocks = <&gateclk 28>;
|
||||
status = "okay";
|
||||
|
||||
xor10 {
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor11 {
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@70000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x70000 0x4000>;
|
||||
interrupts-extended = <&mpic 8>;
|
||||
clocks = <&gateclk 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio: mdio@72004 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0x72004 0x4>;
|
||||
clocks = <&gateclk 4>;
|
||||
};
|
||||
|
||||
rtc@a3800 {
|
||||
compatible = "marvell,armada-380-rtc";
|
||||
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
|
||||
reg-names = "rtc", "rtc-soc";
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sata@a8000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xa8000 0x2000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xe0000 0x2000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
coredivclk: clock@e4250 {
|
||||
compatible = "marvell,armada-380-corediv-clock";
|
||||
reg = <0xe4250 0xc>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&mainpll>;
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
|
||||
thermal@e8078 {
|
||||
compatible = "marvell,armada380-thermal";
|
||||
reg = <0xe4078 0x4>, <0xe4074 0x4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
flash@d0000 {
|
||||
compatible = "marvell,armada370-nand";
|
||||
reg = <0xd0000 0x54>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coredivclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@d8000 {
|
||||
compatible = "marvell,armada-380-sdhci";
|
||||
reg-names = "sdhci", "mbus", "conf-sdio3";
|
||||
reg = <0xd8000 0x1000>,
|
||||
<0xdc000 0x100>,
|
||||
<0x18454 0x4>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 17>;
|
||||
mrvl,clk-delay-cycles = <0x1F>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3@f0000 {
|
||||
compatible = "marvell,armada-380-xhci";
|
||||
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3@f8000 {
|
||||
compatible = "marvell,armada-380-xhci";
|
||||
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
/* 2 GHz fixed main PLL */
|
||||
mainpll: mainpll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000000>;
|
||||
};
|
||||
|
||||
/* 25 MHz reference crystal */
|
||||
refclk: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,245 @@
|
|||
/*
|
||||
* Device Tree file for Marvell Armada XP development board
|
||||
* (DB-MV784MP-GP)
|
||||
*
|
||||
* Copyright (C) 2013-2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Note: this Device Tree assumes that the bootloader has remapped the
|
||||
* internal registers to 0xf1000000 (instead of the default
|
||||
* 0xd0000000). The 0xf1000000 is the default used by the recent,
|
||||
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
|
||||
* boards were delivered with an older version of the bootloader that
|
||||
* left internal registers mapped at 0xd0000000. If you are in this
|
||||
* situation, you should either update your bootloader (preferred
|
||||
* solution) or the below Device Tree should be adjusted.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-xp-mv78460.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP Development Board DB-MV784MP-GP";
|
||||
compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
/*
|
||||
* 8 GB of plug-in RAM modules by default.The amount
|
||||
* of memory available can be changed by the
|
||||
* bootloader according the size of the module
|
||||
* actually plugged. However, memory between
|
||||
* 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
|
||||
* the address range used for I/O (internal registers,
|
||||
* MBus windows).
|
||||
*/
|
||||
reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
|
||||
<0x00000001 0x00000000 0x00000001 0x00000000>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
pm_pic {
|
||||
ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
|
||||
<&gpio0 17 GPIO_ACTIVE_LOW>,
|
||||
<&gpio0 18 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
|
||||
|
||||
devbus-bootcs {
|
||||
status = "okay";
|
||||
|
||||
/* Device Bus parameters are required */
|
||||
|
||||
/* Read parameters */
|
||||
devbus,bus-width = <16>;
|
||||
devbus,turn-off-ps = <60000>;
|
||||
devbus,badr-skew-ps = <0>;
|
||||
devbus,acc-first-ps = <124000>;
|
||||
devbus,acc-next-ps = <248000>;
|
||||
devbus,rd-setup-ps = <0>;
|
||||
devbus,rd-hold-ps = <0>;
|
||||
|
||||
/* Write parameters */
|
||||
devbus,sync-enable = <0>;
|
||||
devbus,wr-high-ps = <60000>;
|
||||
devbus,wr-low-ps = <60000>;
|
||||
devbus,ale-wr-ps = <60000>;
|
||||
|
||||
/* NOR 16 MiB */
|
||||
nor@0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x1000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* The 3 slots are physically present as
|
||||
* standard PCIe slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@9,0 {
|
||||
/* Port 2, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@10,0 {
|
||||
/* Port 3, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12100 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12200 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12300 {
|
||||
status = "okay";
|
||||
};
|
||||
pinctrl {
|
||||
pinctrl-0 = <&pic_pins>;
|
||||
pinctrl-names = "default";
|
||||
pic_pins: pic-pins-0 {
|
||||
marvell,pins = "mpp16", "mpp17",
|
||||
"mpp18";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
sata@a0000 {
|
||||
nr-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <16>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <17>;
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <18>;
|
||||
};
|
||||
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <19>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "qsgmii";
|
||||
};
|
||||
ethernet@74000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "qsgmii";
|
||||
};
|
||||
ethernet@30000 {
|
||||
status = "okay";
|
||||
phy = <&phy2>;
|
||||
phy-mode = "qsgmii";
|
||||
};
|
||||
ethernet@34000 {
|
||||
status = "okay";
|
||||
phy = <&phy3>;
|
||||
phy-mode = "qsgmii";
|
||||
};
|
||||
|
||||
/* Front-side USB slot */
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Back-side USB slot */
|
||||
usb@51000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13", "jedec,spi-nor";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,231 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78230 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
#include "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78230 SoC";
|
||||
compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-xp-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <0>;
|
||||
clocks = <&cpuclk 0>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <1>;
|
||||
clocks = <&cpuclk 1>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/*
|
||||
* MV78230 has 2 PCIe units Gen2.0: One unit can be
|
||||
* configured as x4 or quad x1 lanes. One unit is
|
||||
* x1 only.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <82>, <83>, <84>, <85>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <17>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "marvell,mv78230-pinctrl";
|
||||
};
|
||||
|
|
@ -0,0 +1,333 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78260 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
#include "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78260 SoC";
|
||||
compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-xp-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <0>;
|
||||
clocks = <&cpuclk 0>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <1>;
|
||||
clocks = <&cpuclk 1>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/*
|
||||
* MV78260 has 3 PCIe units Gen2.0: Two units can be
|
||||
* configured as x4 or quad x1 lanes. One unit is
|
||||
* x4 only.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
||||
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
||||
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
||||
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
||||
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
||||
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
||||
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@7,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x7 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 64>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@8,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
|
||||
reg = <0x4000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x8 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 65>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <82>, <83>, <84>, <85>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>, <90>;
|
||||
};
|
||||
|
||||
gpio2: gpio@18180 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18180 0x40>;
|
||||
ngpios = <3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <91>;
|
||||
};
|
||||
|
||||
eth3: ethernet@34000 {
|
||||
compatible = "marvell,armada-xp-neta";
|
||||
reg = <0x34000 0x4000>;
|
||||
interrupts = <14>;
|
||||
clocks = <&gateclk 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "marvell,mv78260-pinctrl";
|
||||
};
|
||||
|
|
@ -0,0 +1,371 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78460 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
#include "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78460 SoC";
|
||||
compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
};
|
||||
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-xp-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <0>;
|
||||
clocks = <&cpuclk 0>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <1>;
|
||||
clocks = <&cpuclk 1>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <2>;
|
||||
clocks = <&cpuclk 2>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <3>;
|
||||
clocks = <&cpuclk 3>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/*
|
||||
* MV78460 has 4 PCIe units Gen2.0: Two units can be
|
||||
* configured as x4 or quad x1 lanes. Two units are
|
||||
* x4/x1.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
||||
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
||||
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
||||
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
||||
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
||||
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
||||
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
|
||||
|
||||
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
|
||||
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@7,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x7 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 64>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@8,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
|
||||
reg = <0x4000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x8 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 65>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@10,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
|
||||
reg = <0x5000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
|
||||
0x81000000 0 0 0x81000000 0xa 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 103>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 27>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <82>, <83>, <84>, <85>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>, <90>;
|
||||
};
|
||||
|
||||
gpio2: gpio@18180 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18180 0x40>;
|
||||
ngpios = <3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <91>;
|
||||
};
|
||||
|
||||
eth3: ethernet@34000 {
|
||||
compatible = "marvell,armada-xp-neta";
|
||||
reg = <0x34000 0x4000>;
|
||||
interrupts = <14>;
|
||||
clocks = <&gateclk 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "marvell,mv78460-pinctrl";
|
||||
};
|
||||
|
|
@ -0,0 +1,320 @@
|
|||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
* Ben Dooks <ben.dooks@codethink.co.uk>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP SoC that are not
|
||||
* common to all Armada SoCs.
|
||||
*/
|
||||
|
||||
#include "armada-370-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP family SoC";
|
||||
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "marvell,armadaxp-mbus", "simple-bus";
|
||||
|
||||
bootrom {
|
||||
compatible = "marvell,bootrom";
|
||||
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
sdramc@1400 {
|
||||
compatible = "marvell,armada-xp-sdram-controller";
|
||||
reg = <0x1400 0x500>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "marvell,aurora-system-cache";
|
||||
reg = <0x08000 0x1000>;
|
||||
cache-id-part = <0x100>;
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
wt-override;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-xp-spi",
|
||||
"marvell,orion-spi";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-xp-spi",
|
||||
"marvell,orion-spi";
|
||||
};
|
||||
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x100>;
|
||||
};
|
||||
|
||||
i2c1: i2c@11100 {
|
||||
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11100 0x100>;
|
||||
};
|
||||
|
||||
uart2: serial@12200 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x12200 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <43>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@12300 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x12300 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <44>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
system-controller@18200 {
|
||||
compatible = "marvell,armada-370-xp-system-controller";
|
||||
reg = <0x18200 0x500>;
|
||||
};
|
||||
|
||||
gateclk: clock-gating-control@18220 {
|
||||
compatible = "marvell,armada-xp-gating-clock";
|
||||
reg = <0x18220 0x4>;
|
||||
clocks = <&coreclk 0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
coreclk: mvebu-sar@18230 {
|
||||
compatible = "marvell,armada-xp-core-clock";
|
||||
reg = <0x18230 0x08>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
thermal@182b0 {
|
||||
compatible = "marvell,armadaxp-thermal";
|
||||
reg = <0x182b0 0x4
|
||||
0x184d0 0x4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
cpuclk: clock-complex@18700 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "marvell,armada-xp-cpu-clock";
|
||||
reg = <0x18700 0x24>, <0x1c054 0x10>;
|
||||
clocks = <&coreclk 1>;
|
||||
};
|
||||
|
||||
interrupt-controller@20a00 {
|
||||
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "marvell,armada-xp-timer";
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
compatible = "marvell,armada-xp-wdt";
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
cpurst@20800 {
|
||||
compatible = "marvell,armada-370-cpu-reset";
|
||||
reg = <0x20800 0x20>;
|
||||
};
|
||||
|
||||
eth2: ethernet@30000 {
|
||||
compatible = "marvell,armada-xp-neta";
|
||||
reg = <0x30000 0x4000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&gateclk 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
clocks = <&gateclk 18>;
|
||||
};
|
||||
|
||||
usb@51000 {
|
||||
clocks = <&gateclk 19>;
|
||||
};
|
||||
|
||||
usb@52000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x52000 0x500>;
|
||||
interrupts = <47>;
|
||||
clocks = <&gateclk 20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xor@60900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60900 0x100
|
||||
0x60b00 0x100>;
|
||||
clocks = <&gateclk 22>;
|
||||
status = "okay";
|
||||
|
||||
xor10 {
|
||||
interrupts = <51>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor11 {
|
||||
interrupts = <52>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
compatible = "marvell,armada-xp-neta";
|
||||
};
|
||||
|
||||
ethernet@74000 {
|
||||
compatible = "marvell,armada-xp-neta";
|
||||
};
|
||||
|
||||
xor@f0900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0xF0900 0x100
|
||||
0xF0B00 0x100>;
|
||||
clocks = <&gateclk 28>;
|
||||
status = "okay";
|
||||
|
||||
xor00 {
|
||||
interrupts = <94>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <95>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
/* 25 MHz reference crystal */
|
||||
refclk: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
ge0_gmii_pins: ge0-gmii-pins {
|
||||
marvell,pins =
|
||||
"mpp0", "mpp1", "mpp2", "mpp3",
|
||||
"mpp4", "mpp5", "mpp6", "mpp7",
|
||||
"mpp8", "mpp9", "mpp10", "mpp11",
|
||||
"mpp12", "mpp13", "mpp14", "mpp15",
|
||||
"mpp16", "mpp17", "mpp18", "mpp19",
|
||||
"mpp20", "mpp21", "mpp22", "mpp23";
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
|
||||
ge0_rgmii_pins: ge0-rgmii-pins {
|
||||
marvell,pins =
|
||||
"mpp0", "mpp1", "mpp2", "mpp3",
|
||||
"mpp4", "mpp5", "mpp6", "mpp7",
|
||||
"mpp8", "mpp9", "mpp10", "mpp11";
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
|
||||
ge1_rgmii_pins: ge1-rgmii-pins {
|
||||
marvell,pins =
|
||||
"mpp12", "mpp13", "mpp14", "mpp15",
|
||||
"mpp16", "mpp17", "mpp18", "mpp19",
|
||||
"mpp20", "mpp21", "mpp22", "mpp23";
|
||||
marvell,function = "ge1";
|
||||
};
|
||||
|
||||
sdio_pins: sdio-pins {
|
||||
marvell,pins = "mpp30", "mpp31", "mpp32",
|
||||
"mpp33", "mpp34", "mpp35";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
|
||||
spi0_pins: spi0-pins {
|
||||
marvell,pins = "mpp36", "mpp37",
|
||||
"mpp38", "mpp39";
|
||||
marvell,function = "spi0";
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
marvell,pins = "mpp42", "mpp43";
|
||||
marvell,function = "uart2";
|
||||
};
|
||||
|
||||
uart3_pins: uart3-pins {
|
||||
marvell,pins = "mpp44", "mpp45";
|
||||
marvell,function = "uart3";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
if ARCH_MVEBU
|
||||
|
||||
choice
|
||||
prompt "Marvell MVEBU (Armada XP/38x) board select"
|
||||
optional
|
||||
|
||||
config TARGET_DB_88F6820_GP
|
||||
bool "Support DB-88F6820-GP"
|
||||
|
||||
config TARGET_DB_MV784MP_GP
|
||||
bool "Support db-mv784mp-gp"
|
||||
|
||||
config TARGET_MAXBCM
|
||||
bool "Support maxbcm"
|
||||
|
||||
endchoice
|
||||
|
||||
config SYS_SOC
|
||||
default "mvebu"
|
||||
|
||||
config MVEBU_BOOTROM_UARTBOOT
|
||||
bool "Use kwboot to boot via BootROM xmodem protocol"
|
||||
help
|
||||
This option provides support for booting via the Marvell
|
||||
xmodem protocol, used by the kwboot tool.
|
||||
|
||||
Please don't forget to configure the boot device in
|
||||
the board specific kwbimage.cfg file this way:
|
||||
BOOT_FROM uart
|
||||
|
||||
endif
|
||||
|
|
@ -27,6 +27,14 @@ static struct mbus_win windows[] = {
|
|||
CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_BOOTROM },
|
||||
};
|
||||
|
||||
void lowlevel_init(void)
|
||||
{
|
||||
/*
|
||||
* Dummy implementation, we only need LOWLEVEL_INIT
|
||||
* on Armada to configure CP15 in start.S / cpu_init_cp15()
|
||||
*/
|
||||
}
|
||||
|
||||
void reset_cpu(unsigned long ignored)
|
||||
{
|
||||
struct mvebu_system_registers *reg =
|
||||
|
|
@ -214,7 +222,10 @@ static void setup_usb_phys(void)
|
|||
|
||||
int arch_cpu_init(void)
|
||||
{
|
||||
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARMADA_38X)
|
||||
#if !defined(CONFIG_SPL_BUILD)
|
||||
struct pl310_regs *const pl310 =
|
||||
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
|
||||
|
||||
/*
|
||||
* Only with disabled MMU its possible to switch the base
|
||||
* register address on Armada 38x. Without this the SDRAM
|
||||
|
|
@ -234,18 +245,14 @@ int arch_cpu_init(void)
|
|||
* configured the internal register base to the value used
|
||||
* in the macros / defines in the U-Boot header (soc.h).
|
||||
*/
|
||||
if (mvebu_soc_family() == MVEBU_SOC_A38X) {
|
||||
struct pl310_regs *const pl310 =
|
||||
(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
|
||||
|
||||
/*
|
||||
* To fully release / unlock this area from cache, we need
|
||||
* to flush all caches and disable the L2 cache.
|
||||
*/
|
||||
icache_disable();
|
||||
dcache_disable();
|
||||
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
|
||||
}
|
||||
/*
|
||||
* To fully release / unlock this area from cache, we need
|
||||
* to flush all caches and disable the L2 cache.
|
||||
*/
|
||||
icache_disable();
|
||||
dcache_disable();
|
||||
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
|
||||
#endif
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -119,6 +119,8 @@ int mvebu_mbus_probe(struct mbus_win windows[], int count);
|
|||
int mvebu_soc_family(void);
|
||||
u32 mvebu_get_nand_clock(void);
|
||||
|
||||
void return_to_bootrom(void);
|
||||
|
||||
int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
/* SOC specific definations */
|
||||
#define INTREG_BASE 0xd0000000
|
||||
#define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
|
||||
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYS_MVEBU_DDR_A38X)
|
||||
#if defined(CONFIG_SPL_BUILD)
|
||||
/*
|
||||
* On A38x switching the regs base address without running from
|
||||
* SDRAM doesn't seem to work. So let the SPL still use the
|
||||
|
|
|
|||
|
|
@ -5,9 +5,25 @@
|
|||
#include <config.h>
|
||||
#include <linux/linkage.h>
|
||||
|
||||
#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
|
||||
ENTRY(save_boot_params)
|
||||
stmfd sp!, {r0 - r12, lr} /* @ save registers on stack */
|
||||
ldr r12, =CONFIG_SPL_BOOTROM_SAVE
|
||||
str sp, [r12]
|
||||
b save_boot_params_ret
|
||||
ENDPROC(save_boot_params)
|
||||
|
||||
ENTRY(return_to_bootrom)
|
||||
ldr r12, =CONFIG_SPL_BOOTROM_SAVE
|
||||
ldr sp, [r12]
|
||||
mov r0, #0x0 /* @ return value: 0x0 NO_ERR */
|
||||
ldmfd sp!, {r0 - r12, pc} /* @ restore regs and return */
|
||||
ENDPROC(return_to_bootrom)
|
||||
#else
|
||||
ENTRY(save_boot_params)
|
||||
b save_boot_params_ret
|
||||
ENDPROC(save_boot_params)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* cache_inv - invalidate Cache line
|
||||
|
|
|
|||
|
|
@ -31,11 +31,18 @@ u32 spl_boot_mode(void)
|
|||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
/* Set global data pointer */
|
||||
gd = &gdata;
|
||||
#ifndef CONFIG_MVEBU_BOOTROM_UARTBOOT
|
||||
/*
|
||||
* Only call arch_cpu_init() when not returning to the
|
||||
* Marvell BootROM, which is done when booting via
|
||||
* the xmodem protocol (kwboot tool). Otherwise the
|
||||
* internal register will get remapped and the BootROM
|
||||
* can't continue to run correctly.
|
||||
*/
|
||||
|
||||
/* Linux expects the internal registers to be at 0xf1000000 */
|
||||
arch_cpu_init();
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Pin muxing needs to be done before UART output, since
|
||||
|
|
@ -54,5 +61,18 @@ void board_init_f(ulong dummy)
|
|||
/* Setup DDR */
|
||||
ddr3_init();
|
||||
|
||||
board_init_r(NULL, 0);
|
||||
#ifdef CONFIG_MVEBU_BOOTROM_UARTBOOT
|
||||
/*
|
||||
* Return to the BootROM to continue the Marvell xmodem
|
||||
* UART boot protocol. As initiated by the kwboot tool.
|
||||
*
|
||||
* This can only be done by the BootROM and not by the
|
||||
* U-Boot SPL infrastructure, since the beginning of the
|
||||
* image is already read and interpreted by the BootROM.
|
||||
* SPL has no chance to receive this information. So we
|
||||
* need to return to the BootROM to enable this xmodem
|
||||
* UART download.
|
||||
*/
|
||||
return_to_bootrom();
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,9 +6,6 @@ config SYS_BOARD
|
|||
config SYS_VENDOR
|
||||
default "Marvell"
|
||||
|
||||
config SYS_SOC
|
||||
default "mvebu"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "db-88f6820-gp"
|
||||
|
||||
|
|
|
|||
|
|
@ -6,9 +6,6 @@ config SYS_BOARD
|
|||
config SYS_VENDOR
|
||||
default "Marvell"
|
||||
|
||||
config SYS_SOC
|
||||
default "mvebu"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "db-mv784mp-gp"
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,6 @@ if TARGET_MAXBCM
|
|||
config SYS_BOARD
|
||||
default "maxbcm"
|
||||
|
||||
config SYS_SOC
|
||||
default "mvebu"
|
||||
|
||||
config SYS_CONFIG_NAME
|
||||
default "maxbcm"
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,14 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_TARGET_DB_88F6820_GP=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="armada-388-gp"
|
||||
CONFIG_SPL=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
|
|
|
|||
|
|
@ -1,8 +1,15 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_TARGET_DB_MV784MP_GP=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
|
||||
CONFIG_SPL=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_USB=y
|
||||
# CONFIG_CMD_SETEXPR is not set
|
||||
CONFIG_NAND_PXA3XX=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_TARGET_MAXBCM=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="armada-xp-gp"
|
||||
CONFIG_SPL=y
|
||||
# CONFIG_CMD_IMLS is not set
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
|
|
|
|||
|
|
@ -120,4 +120,34 @@ config SPL_SIMPLE_BUS
|
|||
Supports the 'simple-bus' driver, which is used on some systems
|
||||
in SPL.
|
||||
|
||||
config OF_TRANSLATE
|
||||
bool "Translate addresses using fdt_translate_address"
|
||||
depends on DM && OF_CONTROL
|
||||
default y
|
||||
help
|
||||
If this option is enabled, the reg property will be translated
|
||||
using the fdt_translate_address() function. This is necessary
|
||||
on some platforms (e.g. MVEBU) using complex "ranges"
|
||||
properties in many nodes. As this translation is not handled
|
||||
correctly in the default simple_bus_translate() function.
|
||||
|
||||
If this option is not enabled, simple_bus_translate() will be
|
||||
used for the address translation. This function is faster and
|
||||
smaller in size than fdt_translate_address().
|
||||
|
||||
config SPL_OF_TRANSLATE
|
||||
bool "Translate addresses using fdt_translate_address"
|
||||
depends on SPL_DM && SPL_OF_CONTROL
|
||||
default n
|
||||
help
|
||||
If this option is enabled, the reg property will be translated
|
||||
using the fdt_translate_address() function. This is necessary
|
||||
on some platforms (e.g. MVEBU) using complex "ranges"
|
||||
properties in many nodes. As this translation is not handled
|
||||
correctly in the default simple_bus_translate() function.
|
||||
|
||||
If this option is not enabled, simple_bus_translate() will be
|
||||
used for the address translation. This function is faster and
|
||||
smaller in size than fdt_translate_address().
|
||||
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
#include <common.h>
|
||||
#include <fdtdec.h>
|
||||
#include <fdt_support.h>
|
||||
#include <malloc.h>
|
||||
#include <dm/device.h>
|
||||
#include <dm/device-internal.h>
|
||||
|
|
@ -585,6 +586,25 @@ fdt_addr_t dev_get_addr(struct udevice *dev)
|
|||
#if CONFIG_IS_ENABLED(OF_CONTROL)
|
||||
fdt_addr_t addr;
|
||||
|
||||
if (CONFIG_IS_ENABLED(OF_TRANSLATE)) {
|
||||
const fdt32_t *reg;
|
||||
|
||||
reg = fdt_getprop(gd->fdt_blob, dev->of_offset, "reg", NULL);
|
||||
if (!reg)
|
||||
return FDT_ADDR_T_NONE;
|
||||
|
||||
/*
|
||||
* Use the full-fledged translate function for complex
|
||||
* bus setups.
|
||||
*/
|
||||
return fdt_translate_address((void *)gd->fdt_blob,
|
||||
dev->of_offset, reg);
|
||||
}
|
||||
|
||||
/*
|
||||
* Use the "simple" translate function for less complex
|
||||
* bus setups.
|
||||
*/
|
||||
addr = fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
|
||||
dev->parent->of_offset,
|
||||
dev->of_offset, "reg",
|
||||
|
|
|
|||
|
|
@ -1,6 +1,41 @@
|
|||
/*
|
||||
* Marvell SD Host Controller Interface
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <malloc.h>
|
||||
#include <sdhci.h>
|
||||
#include <linux/mbus.h>
|
||||
|
||||
#define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4))
|
||||
#define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4))
|
||||
|
||||
static void sdhci_mvebu_mbus_config(void __iomem *base)
|
||||
{
|
||||
const struct mbus_dram_target_info *dram;
|
||||
int i;
|
||||
|
||||
dram = mvebu_mbus_dram_info();
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
writel(0, base + SDHCI_WINDOW_CTRL(i));
|
||||
writel(0, base + SDHCI_WINDOW_BASE(i));
|
||||
}
|
||||
|
||||
for (i = 0; i < dram->num_cs; i++) {
|
||||
const struct mbus_dram_window *cs = dram->cs + i;
|
||||
|
||||
/* Write size, attributes and target id to control register */
|
||||
writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
|
||||
(dram->mbus_dram_target_id << 4) | 1,
|
||||
base + SDHCI_WINDOW_CTRL(i));
|
||||
|
||||
/* Write base address to base register */
|
||||
writel(cs->base, base + SDHCI_WINDOW_BASE(i));
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
|
||||
static struct sdhci_ops mv_ops;
|
||||
|
|
@ -47,6 +82,12 @@ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
|
|||
mv_ops.write_b = mv_sdhci_writeb;
|
||||
host->ops = &mv_ops;
|
||||
#endif
|
||||
|
||||
if (CONFIG_IS_ENABLED(ARCH_MVEBU)) {
|
||||
/* Configure SDHCI MBUS mbus bridge windows */
|
||||
sdhci_mvebu_mbus_config((void __iomem *)regbase);
|
||||
}
|
||||
|
||||
if (quirks & SDHCI_QUIRK_REG32_RW)
|
||||
host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
|
||||
else
|
||||
|
|
|
|||
|
|
@ -52,6 +52,13 @@ config USB_EHCI
|
|||
|
||||
if USB_EHCI_HCD
|
||||
|
||||
config USB_EHCI_MARVELL
|
||||
bool "Support for MVEBU (AXP / A38x) on-chip EHCI USB controller"
|
||||
depends on ARCH_MVEBU
|
||||
default y
|
||||
---help---
|
||||
Enables support for the on-chip EHCI controller on MVEBU SoCs.
|
||||
|
||||
config USB_EHCI_MX6
|
||||
bool "Support for i.MX6 on-chip EHCI USB controller"
|
||||
depends on ARCH_MX6
|
||||
|
|
|
|||
|
|
@ -12,6 +12,7 @@
|
|||
#include "ehci.h"
|
||||
#include <linux/mbus.h>
|
||||
#include <asm/arch/cpu.h>
|
||||
#include <dm.h>
|
||||
|
||||
#if defined(CONFIG_KIRKWOOD)
|
||||
#include <asm/arch/soc.h>
|
||||
|
|
@ -28,24 +29,19 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
/*
|
||||
* USB 2.0 Bridge Address Decoding registers setup
|
||||
*/
|
||||
#ifdef CONFIG_ARMADA_XP
|
||||
#ifdef CONFIG_DM_USB
|
||||
|
||||
/*
|
||||
* Armada XP and Armada 38x have different base addresses for
|
||||
* the USB 2.0 EHCI host controller. So we need to provide
|
||||
* a mechnism to support both here.
|
||||
*/
|
||||
#define MVUSB0_BASE \
|
||||
(mvebu_soc_family() == MVEBU_SOC_A38X ? \
|
||||
MVEBU_USB20_BASE : MVEBU_AXP_USB_BASE)
|
||||
#define MVUSB_BASE(port) MVUSB0_BASE + ((port) << 12)
|
||||
struct ehci_mvebu_priv {
|
||||
struct ehci_ctrl ehci;
|
||||
fdt_addr_t hcd_base;
|
||||
};
|
||||
|
||||
/*
|
||||
* Once all the older Marvell SoC's (Orion, Kirkwood) are converted
|
||||
* to the common mvebu archticture including the mbus setup, this
|
||||
* will be the only function needed to configure the access windows
|
||||
*/
|
||||
static void usb_brg_adrdec_setup(int index)
|
||||
static void usb_brg_adrdec_setup(u32 base)
|
||||
{
|
||||
const struct mbus_dram_target_info *dram;
|
||||
int i;
|
||||
|
|
@ -53,8 +49,8 @@ static void usb_brg_adrdec_setup(int index)
|
|||
dram = mvebu_mbus_dram_info();
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
writel(0, MVUSB_BASE(index) + USB_WINDOW_CTRL(i));
|
||||
writel(0, MVUSB_BASE(index) + USB_WINDOW_BASE(i));
|
||||
writel(0, base + USB_WINDOW_CTRL(i));
|
||||
writel(0, base + USB_WINDOW_BASE(i));
|
||||
}
|
||||
|
||||
for (i = 0; i < dram->num_cs; i++) {
|
||||
|
|
@ -63,12 +59,69 @@ static void usb_brg_adrdec_setup(int index)
|
|||
/* Write size, attributes and target id to control register */
|
||||
writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
|
||||
(dram->mbus_dram_target_id << 4) | 1,
|
||||
MVUSB_BASE(index) + USB_WINDOW_CTRL(i));
|
||||
base + USB_WINDOW_CTRL(i));
|
||||
|
||||
/* Write base address to base register */
|
||||
writel(cs->base, MVUSB_BASE(index) + USB_WINDOW_BASE(i));
|
||||
writel(cs->base, base + USB_WINDOW_BASE(i));
|
||||
}
|
||||
}
|
||||
|
||||
static int ehci_mvebu_probe(struct udevice *dev)
|
||||
{
|
||||
struct ehci_mvebu_priv *priv = dev_get_priv(dev);
|
||||
struct ehci_hccr *hccr;
|
||||
struct ehci_hcor *hcor;
|
||||
|
||||
/*
|
||||
* Get the base address for EHCI controller from the device node
|
||||
*/
|
||||
priv->hcd_base = dev_get_addr(dev);
|
||||
if (priv->hcd_base == FDT_ADDR_T_NONE) {
|
||||
debug("Can't get the EHCI register base address\n");
|
||||
return -ENXIO;
|
||||
}
|
||||
|
||||
usb_brg_adrdec_setup(priv->hcd_base);
|
||||
|
||||
hccr = (struct ehci_hccr *)(priv->hcd_base + 0x100);
|
||||
hcor = (struct ehci_hcor *)
|
||||
((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
|
||||
|
||||
debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
|
||||
(u32)hccr, (u32)hcor,
|
||||
(u32)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
|
||||
|
||||
return ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST);
|
||||
}
|
||||
|
||||
static int ehci_mvebu_remove(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = ehci_deregister(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id ehci_usb_ids[] = {
|
||||
{ .compatible = "marvell,orion-ehci", },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(ehci_mvebu) = {
|
||||
.name = "ehci_mvebu",
|
||||
.id = UCLASS_USB,
|
||||
.of_match = ehci_usb_ids,
|
||||
.probe = ehci_mvebu_probe,
|
||||
.remove = ehci_mvebu_remove,
|
||||
.ops = &ehci_usb_ops,
|
||||
.platdata_auto_alloc_size = sizeof(struct usb_platdata),
|
||||
.priv_auto_alloc_size = sizeof(struct ehci_mvebu_priv),
|
||||
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
||||
};
|
||||
|
||||
#else
|
||||
#define MVUSB_BASE(port) MVUSB0_BASE
|
||||
|
||||
|
|
@ -112,7 +165,6 @@ static void usb_brg_adrdec_setup(int index)
|
|||
writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Create the appropriate control structures to manage
|
||||
|
|
@ -142,3 +194,5 @@ int ehci_hcd_stop(int index)
|
|||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_DM_USB */
|
||||
|
|
|
|||
|
|
@ -16,7 +16,9 @@
|
|||
|
||||
#define CONFIG_SYS_L2_PL310
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
#endif
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
||||
|
||||
|
|
@ -48,7 +50,6 @@
|
|||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_CMD_TFTPPUT
|
||||
#define CONFIG_CMD_TIME
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
|
|
@ -91,9 +92,6 @@
|
|||
#define CONFIG_SUPPORT_VFAT
|
||||
|
||||
/* USB/EHCI configuration */
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_EHCI_MARVELL
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
|
||||
/* Environment in SPI NOR flash */
|
||||
|
|
|
|||
|
|
@ -13,7 +13,9 @@
|
|||
#define CONFIG_ARMADA_XP /* SOC Family Name */
|
||||
#define CONFIG_DB_784MP_GP /* Board target name for DDR training */
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
#endif
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
||||
|
||||
|
|
@ -40,7 +42,6 @@
|
|||
#define CONFIG_CMD_SPI
|
||||
#define CONFIG_CMD_TFTPPUT
|
||||
#define CONFIG_CMD_TIME
|
||||
#define CONFIG_CMD_USB
|
||||
|
||||
/* I2C */
|
||||
#define CONFIG_SYS_I2C
|
||||
|
|
@ -50,9 +51,6 @@
|
|||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
|
||||
/* USB/EHCI configuration */
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_EHCI_MARVELL
|
||||
#define CONFIG_EHCI_IS_TDI
|
||||
#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,9 @@
|
|||
* High Level Configuration Options (easy to change)
|
||||
*/
|
||||
#define CONFIG_ARMADA_XP /* SOC Family Name */
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
|
||||
#endif
|
||||
#define CONFIG_SYS_GENERIC_BOARD
|
||||
#define CONFIG_DISPLAY_BOARDINFO_LATE
|
||||
|
||||
|
|
|
|||
|
|
@ -39,11 +39,17 @@
|
|||
/*
|
||||
* NS16550 Configuration
|
||||
*/
|
||||
#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM_SERIAL)
|
||||
#define CONFIG_DW_SERIAL
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NS16550
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
|
||||
#if !defined(CONFIG_DM_SERIAL)
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
|
||||
#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Serial Port configuration
|
||||
|
|
@ -128,7 +134,7 @@
|
|||
/*
|
||||
* Common USB/EHCI configuration
|
||||
*/
|
||||
#ifdef CONFIG_CMD_USB
|
||||
#if defined(CONFIG_CMD_USB) && !defined(CONFIG_DM)
|
||||
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
|
|
|||
|
|
@ -681,6 +681,9 @@ static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd,
|
|||
exit(EXIT_FAILURE);
|
||||
}
|
||||
|
||||
/* The MVEBU BootROM does not allow non word aligned payloads */
|
||||
sbuf->st_size = ALIGN_SUP(sbuf->st_size, 4);
|
||||
|
||||
version = image_get_version();
|
||||
switch (version) {
|
||||
/*
|
||||
|
|
|
|||
Loading…
Reference in New Issue