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Clean up the code according to codestyle: 

(1) remove some C++ comments.
(2) remove trailing white space.
(3) remove trailing empty line.
(4) Indentation by table.
(5) remove {} in one line condition.
(6) add space before '(' in function call.
Remove some weird printf () output.
Add necessary comments.
Modified Makefile to support building in a separate directory.
This commit is contained in:
roy zang 2006-12-01 11:47:36 +08:00 committed by Zang Tiefei
parent 6bd87c0aee
commit ee311214e0
13 changed files with 1687 additions and 1734 deletions
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2
Makefile
View File

@ -1722,7 +1722,7 @@ EVB64260_750CX_config: unconfig
@$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260
mpc7448hpc2_config: unconfig
@./mkconfig $(@:_config=) ppc 74xx_7xx mpc7448hpc2
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2
P3G4_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260

20
board/mpc7448hpc2/Makefile
View File

@ -23,26 +23,30 @@
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
LIB = $(obj)lib$(BOARD).a
OBJS = $(BOARD).o tsi108_init.o
COBJS := $(BOARD).o tsi108_init.o
SOBJS := asm_init.o
SOBJS = asm_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
.PHONY: distclean
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude .depend
sinclude ($obj).depend
#########################################################################

307
board/mpc7448hpc2/asm_init.S
View File

@ -1,4 +1,4 @@
/*****************************************************************************
/*
* (C) Copyright 2004-05; Tundra Semiconductor Corp.
*
* Added automatic detect of SDC settings
@ -19,9 +19,9 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
****************************************************************************/
*/
/*----------------------------------------------------------------------------
/*
* FILENAME: asm_init.s
*
* Originator: Alex Bounine
@ -29,7 +29,7 @@
* DESCRIPTION:
* Initialization code for the Tundra Tsi108 bridge chip
*
*---------------------------------------------------------------------------*/
*/
#include <config.h>
#include <version.h>
@ -40,7 +40,7 @@
#include <tsi108.h>
/*===========================================================================
/*
* Build Configuration Options
*/
@ -48,7 +48,7 @@
/* #define SDC_HARDCODED_INIT config SDRAM controller with hardcoded values */
/* #define SDC_AUTOPRECH_EN enable SDRAM auto precharge */
/* ===========================================================================
/*
* Hardcoded SDC settings
*/
@ -65,24 +65,24 @@
#endif /* SDC_HARDCODED_INIT */
/*---------------------------------------------------------------------------
/*
CPU Configuration:
CPU Address and Data Parity enables.
#define CPU_AP
#define CPU_DP
*/
===========================================================================
Macros
!!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
expected to work correctly for the CSR space within 32KB range.
LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
These macros are absolutely identical except their names. This difference
is provided intentionally for better readable code.
-------------------------------------------------------------------------*/
/*
* Macros
* !!! Attention !!! Macros LOAD_PTR, LOAD_U32 and LOAD_MEM defined below are
* expected to work correctly for the CSR space within 32KB range.
*
* LOAD_PTR and LOAD_U32 - load specified register with a 32 bit constant.
* These macros are absolutely identical except their names. This difference
* is provided intentionally for better readable code.
*/
#define LOAD_PTR(reg,const32) \
addis reg,r0,const32@h; ori reg,reg,const32@l
@ -90,8 +90,9 @@
#define LOAD_U32(reg,const32) \
addis reg,r0,const32@h; ori reg,reg,const32@l
/* LOADMEM initializes a register with the contents of a specified 32-bit memory
location, usually a CSR value.*/
/* LOADMEM initializes a register with the contents of a specified 32-bit
* memory location, usually a CSR value.
*/
#define LOAD_MEM(reg,addr32) \
addis reg,r0,addr32@ha; lwz reg,addr32@l(reg)
@ -99,40 +100,33 @@
#ifndef SDC_HARDCODED_INIT
sdc_clk_sync:
/* MHz: 0,0,183,100,133,167,200,233 */
.long 0,0, 6, 10, 8, 6, 5, 4 /* nSec */
.long 0, 0, 6, 10, 8, 6, 5, 4 /* nSec */
#endif
/*===========================================================================
board_asm_init() - early initialization function. Coded to be portable to
dual-CPU configuration.
Checks CPU number and performs board HW initialization if called for CPU0.
Registers used: r3,r4,r5,r6,r19,r29
===========================================================================
---------------------------------------------------------------------------
NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
and the rest of the board. Current implementation demonstrates two
possible ways to identify CPU number:
- for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
- for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
---------------------------------------------------------------------------*/
/*
* board_asm_init() - early initialization function. Coded to be portable to
* dual-CPU configuration.
* Checks CPU number and performs board HW initialization if called for CPU0.
* Registers used: r3,r4,r5,r6,r19,r29
*
* NOTE: For dual-CPU configuration only CPU0 is allowed to configure Tsi108
* and the rest of the board. Current implementation demonstrates two
* possible ways to identify CPU number:
* - for MPC74xx platform: uses MSSCR0[ID] bit as defined in UM.
* - for PPC750FX/GX boards: uses WHO_AM_I bit reported by Tsi108.
*/
.globl board_asm_init
board_asm_init:
mflr r19 /* Save LR to be able return later. */
bl icache_enable /* Enable icache to reduce reads from flash. */
/* Initialize pointer to Tsi108 register space
-------------------------------------------------------------------------*/
/* Initialize pointer to Tsi108 register space */
LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
ori r4,r29,TSI108_PB_REG_OFFSET
/*-------------------------------------------------------------------------
Check Processor Version Number */
/* Check Processor Version Number */
mfspr r3, PVR
rlwinm r3,r3,16,16,23 /* get ((Processor Version Number) & 0xFF00) */
@ -140,10 +134,10 @@ board_asm_init:
cmpli 0,0,r3,0x8000 /* MPC74xx */
bne cont_brd_init
/* ------------------------------------------
For MPC744x/5x enable extended BATs[4-7]
Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
to disable prefetch
/*
* For MPC744x/5x enable extended BATs[4-7]
* Sri: Set HIGH_BAT_EN and XBSEN, and SPD =1
* to disable prefetch
*/
mfspr r5, HID0
@ -167,11 +161,10 @@ board_asm_init:
isync
sync
#if(1) /* def CONFIG_DUAL_CPU
-------------------------------------------------------------------------
For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
/* def CONFIG_DUAL_CPU
* For MPC74xx processor, use MSSCR0[ID] bit to identify CPU number.
*/
#if(1)
mfspr r3,1014 /* read MSSCR0 */
rlwinm. r3,r3,27,31,31 /* get processor ID number */
mtspr SPRN_PIR,r3 /* Save CPU ID */
@ -182,33 +175,29 @@ board_asm_init:
cont_brd_init:
/* An alternative method of checking the processor number (in addition
to configuration using MSSCR0[ID] bit on MPC74xx).
Good for IBM PPC750FX/GX.
* to configuration using MSSCR0[ID] bit on MPC74xx).
* Good for IBM PPC750FX/GX.
*/
lwz r3,PB_BUS_MS_SELECT(r4) /* read PB_ID register */
rlwinm. r3,r3,24,31,31 /* get processor ID number */
bne init_done
#else
cont_brd_init:
#endif /* CONFIG_DUAL_CPU */
/* Initialize Tsi108 chip
---------------------------------------------------------------------------
*/
/* Initialize Tsi108 chip */
do_tsi108_init:
/*--------------------------------------------------------------------------
Adjust HLP/Flash parameters. By default after reset the HLP port is set
to support slow devices. Better performance can be achived when an optimal
parameters are used for specific EPROM device.
NOTE: This should be performed ASAP for the emulation platform because
it has 5MHz HLP clocking.
/*
* Adjust HLP/Flash parameters. By default after reset the HLP port is
* set to support slow devices. Better performance can be achived when
* an optimal parameters are used for specific EPROM device.
* NOTE: This should be performed ASAP for the emulation platform
* because it has 5MHz HLP clocking.
*/
#ifdef CONFIG_TSI108EMU
@ -221,28 +210,25 @@ do_tsi108_init:
sync
#endif
/* -------------------------------------------------------------------------
* Initialize PB interface.
*/
/* Initialize PB interface. */
ori r4,r29,TSI108_PB_REG_OFFSET
#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE)
/* Relocate (if required) Tsi108 registers. Set new value for PB_REG_BAR:
/* Relocate (if required) Tsi108 registers. Set new value for
* PB_REG_BAR:
* Note we are in the 32-bit address mode.
*/
LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* value for PB_REG_BAR: BA + EN*/
LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
stw r5,PB_REG_BAR(r4)
andis. r29,r5,0xFFFF
sync
ori r4,r29,TSI108_PB_REG_OFFSET
#endif
/* Set PB Slave configuration register */
/* LOAD_U32(r5,0x000024C7) value for PB_SCR: TEA enabled,AACK delay = 7 */
LOAD_U32(r5,0x00002481) /* value for PB_SCR: TEA enabled,AACK delay = 1 */
LOAD_U32(r5,0x00002481) /* PB_SCR: TEA enabled,AACK delay = 1 */
lwz r3, PB_RSR(r4) /* get PB bus mode */
xori r3,r3,0x0001 /* mask PB_BMODE: r3 -> (0 = 60X, 1 = MPX) */
rlwimi r5,r3,14,17,17 /* for MPX: set DTI_MODE bit */
@ -257,10 +243,7 @@ do_tsi108_init:
ori r3,r3,0x1000 /* add PBM_EN to clear (enabled by default) */
#endif
andc r5,r5,r3 /* Clear the masked bit fields */
/* ori r5,r5,0x0040 Set pipeline depth 4
ori r5,r5,0x0080 Set pipeline depth 8
ori r5,r5,0x0020 !!!avb Testing: set pipeline depth 2 */
ori r5,r5,0x0001
ori r5,r5,0x0001 /* Set pipeline depth */
stw r5,PB_ARB_CTRL(r4)
#if (0) /* currently using the default settings for PBM after reset */
@ -273,10 +256,10 @@ do_tsi108_init:
sync
#endif
/* Disable or enable PVT based on processor bus frequency
1. Read CG_PWRUP_STATUS register field bits 18,17,16
2. See if the value is < or > 133mhz (18:16 = 100)
3. If > enable PVT
/* Disable or enable PVT based on processor bus frequency
* 1. Read CG_PWRUP_STATUS register field bits 18,17,16
* 2. See if the value is < or > 133mhz (18:16 = 100)
* 3. If > enable PVT
*/
LOAD_U32(r3,0xC0002234)
@ -293,9 +276,7 @@ do_tsi108_init:
sync
#endif
/*---------------------------------------------------------------------------
Initialize SDRAM controller.
----------------------------------------------------------------------------*/
/* Initialize SDRAM controller. */
sdc_init:
@ -337,7 +318,8 @@ get_nsec:
#ifdef SDC_HARDCODED_INIT /* config sdram controller with hardcoded values */
/* First read the CG_PWRUP_STATUS register to get the
memory speed from bits 22,21,20 */
* memory speed from bits 22,21,20
*/
LOAD_U32(r3,0xC0002234)
lwz r3,0(r3)
@ -348,9 +330,9 @@ get_nsec:
cmpi 0,0,r3,0x0005
bne check_for_200mhz
/* set values for 166 Mhz memory speed */
/* Set refresh rate and timing parameters */
/* set values for 166 Mhz memory speed
* Set refresh rate and timing parameters
*/
LOAD_U32(r5,0x00000515)
stw r5,SD_REFRESH(r4)
LOAD_U32(r5,0x03073368)
@ -386,9 +368,9 @@ check_for_200mhz:
cmpi 0,0,r3,0x0006
bne set_default_values
/* set values for 200Mhz memory speed */
/* Set refresh rate and timing parameters */
/* set values for 200Mhz memory speed
* Set refresh rate and timing parameters
*/
LOAD_U32(r5,0x0000061a)
stw r5,SD_REFRESH(r4)
LOAD_U32(r5,0x03083348)
@ -449,11 +431,8 @@ set_default_values:
LOAD_U32(r5,VAL_SD_D1_BAR)
stw r5,SD_D1_BAR(r4)
sync
#else /* !SDC_HARDCODED_INIT */
bl tsi108_sdram_spd /* automatically detect SDC settings */
#endif /* SDC_HARDCODED_INIT */
sdc_init_done:
@ -481,43 +460,47 @@ sdc_init_done:
wait_init_complete:
lwz r5,SD_STATUS(r4)
andi. r5,r5,0x0001
beq wait_init_complete /* wait until SDRAM initialization is complete */
/* wait until SDRAM initialization is complete */
beq wait_init_complete
/*---------------------------------------------------------------------------
Map SDRAM into the processor bus address space
---------------------------------------------------------------------------*/
/* Map SDRAM into the processor bus address space */
ori r4,r29,TSI108_PB_REG_OFFSET
/* Setup BARs associated with direct path PB<->SDRAM */
/* PB_SDRAM_BAR1:
provides a direct path to the main system memory (cacheable SDRAM) */
* provides a direct path to the main system memory (cacheable SDRAM)
*/
LOAD_U32(r5, 0x00000011) /* BA=0,Size=512MB, ENable, No Addr.Translation */
/* BA=0,Size=512MB, ENable, No Addr.Translation */
LOAD_U32(r5, 0x00000011)
stw r5,PB_SDRAM_BAR1(r4)
sync
/* Make sure that PB_SDRAM_BAR1 decoder is set
(to allow following immediate read from SDRAM) */
* (to allow following immediate read from SDRAM)
*/
lwz r5,PB_SDRAM_BAR1(r4)
sync
/* PB_SDRAM_BAR2:
provides non-cacheable alias (via the direct path) to main system memory.
Size = 512MB, ENable, Addr.Translation - ON,
BA = 0x0_40000000, TA = 0x0_00000000 */
* provides non-cacheable alias (via the direct path) to main
* system memory.
* Size = 512MB, ENable, Addr.Translation - ON,
* BA = 0x0_40000000, TA = 0x0_00000000
*/
LOAD_U32(r5, 0x40010011)
stw r5,PB_SDRAM_BAR2(r4)
sync
/* Make sure that PB_SDRAM_BAR2 decoder is set
(to allow following immediate read from SDRAM) */
* (to allow following immediate read from SDRAM)
*/
lwz r5,PB_SDRAM_BAR2(r4)
sync
init_done:
/* All done. Restore LR and return. */
@ -525,11 +508,11 @@ init_done:
blr
#if (0)
/*===========================================================================
init_cpu1
This routine enables CPU1 on the dual-processor system.
===========================================================================*/
/*
* init_cpu1
* This routine enables CPU1 on the dual-processor system.
* Now there is only one processor in the system
*/
.global enable_cpu1
enable_cpu1:
@ -545,11 +528,10 @@ enable_cpu1:
blr
#endif
/*===========================================================================
enable_EI
Enable CPU core external interrupt
===========================================================================*/
/*
* enable_EI
* Enable CPU core external interrupt
*/
.global enable_EI
enable_EI:
@ -558,11 +540,10 @@ enable_EI:
mtmsr r3
blr
/*===========================================================================
disable_EI
Disable CPU core external interrupt
===========================================================================*/
/*
* disable_EI
* Disable CPU core external interrupt
*/
.global disable_EI
disable_EI:
@ -573,11 +554,7 @@ disable_EI:
blr
#ifdef ENABLE_SDRAM_ECC
/*===========================================================================
enable_ECC
enables SDRAM ECC
===========================================================================*/
/* enables SDRAM ECC */
.global enable_ECC
enable_ECC:
@ -587,17 +564,15 @@ enable_ECC:
stw r3,SD_ECC_CTRL(r4)
blr
/*===========================================================================
clear_ECC_err
Clears all pending SDRAM ECC errors
(normally after SDRAM scrubbing/initialization)
===========================================================================*/
/*
* clear_ECC_err
* Clears all pending SDRAM ECC errors
* (normally after SDRAM scrubbing/initialization)
*/
.global clear_ECC_err
clear_ECC_err:
ori r4,r29,TSI108_SD_REG_OFFSET
/* lwz r3,SD_INT_STATUS(r4) Read SDRAM ECC Control Register */
ori r3,r0,0x0030 /* ECC_UE_INT + ECC_CE_INT bits */
stw r3,SD_INT_STATUS(r4)
blr
@ -606,16 +581,13 @@ clear_ECC_err:
#ifndef SDC_HARDCODED_INIT
/********************************************************************
* SDRAM SPD Support
*/
/* SDRAM SPD Support */
#define SD_I2C_CTRL1 (0x400)
#define SD_I2C_CTRL2 (0x404)
#define SD_I2C_RD_DATA (0x408)
#define SD_I2C_WR_DATA (0x40C)
/*
/*
* SDRAM SPD Support Macros
*/
@ -652,24 +624,24 @@ clear_ECC_err:
*/
#define READ_SPD(byte_num) \
addis r3, 0, byte_num@l;\
or r3, r3, r10;\
ori r3, r3, 0x0A;\
stw r3, SD_I2C_CTRL1(r4);\
li r3, I2C_CNTRL2_START;\
stw r3, SD_I2C_CTRL2(r4);\
eieio;\
sync;\
li r3, 0x100;\
1: ;\
addic. r3, r3, -1;\
bne 1b;\
2: ;\
lwz r5, SD_I2C_CTRL2(r4);\
rlwinm. r3,r5,0,23,23;\
bne 2b;\
rlwinm. r3,r5,0,3,3;\
lwz r3, SD_I2C_RD_DATA(r4)
addis r3, 0, byte_num@l; \
or r3, r3, r10; \
ori r3, r3, 0x0A; \
stw r3, SD_I2C_CTRL1(r4); \
li r3, I2C_CNTRL2_START; \
stw r3, SD_I2C_CTRL2(r4); \
eieio; \
sync; \
li r3, 0x100; \
1:; \
addic. r3, r3, -1; \
bne 1b; \
2:; \
lwz r5, SD_I2C_CTRL2(r4); \
rlwinm. r3,r5,0,23,23; \
bne 2b; \
rlwinm. r3,r5,0,3,3; \
lwz r3,SD_I2C_RD_DATA(r4)
#define SPD_MIN_RFRSH (0x80)
#define SPD_MAX_RFRSH (0x85)
@ -682,14 +654,14 @@ refresh_rates: /* in nSec */
.long 62500 /* Extended 4x (0x84) */
.long 125000 /* Extended 8x (0x85) */
/*===========================================================================
/*
* tsi108_sdram_spd
*
* Inittializes SDRAM Controller using DDR2 DIMM Serial Presence Detect data
* Uses registers: r4 - SDC base address (not changed)
* r9 - SDC clocking period in nSec
* Changes registers: r3,r5,r6,r7,r8,r10,r11
*==========================================================================*/
*/
tsi108_sdram_spd:
@ -698,9 +670,7 @@ tsi108_sdram_spd:
do_first_dimm:
/**************************************
* Program Refresh Rate Register
*/
/* Program Refresh Rate Register */
READ_SPD(12) /* get Refresh Rate */
beq check_next_slot
@ -718,9 +688,7 @@ do_first_dimm:
stw r5,SD_REFRESH(r4) /* Set refresh rate */
sync
/**************************************
* Program SD Timing Register
*/
/* Program SD Timing Register */
li r7, 0 /* clear r7 prior parameter collection */
@ -768,7 +736,8 @@ set_tras:
READ_SPD(29) /* Get tRCD */
beq spd_read_fail
rlwinm r3,r3,30,2,31/* right shift tRCD by 2 bits as per DDR2 spec */
/* right shift tRCD by 2 bits as per DDR2 spec */
rlwinm r3,r3,30,2,31
divwu r6,r3,r9
mullw r8,r6,r9
subf. r8,r8,r3
@ -829,17 +798,14 @@ set_trfc:
stw r7,SD_TIMING(r4)
sync
/*=====================================================================
/*
* The following two registers are set on per-DIMM basis.
* The SD_REFRESH and SD_TIMING settings are common for both DIMMS
*=====================================================================
*/
do_each_dimm:
/*****************************************
* Program SDRAM DIMM Control Register
*/
/* Program SDRAM DIMM Control Register */
li r7, 0 /* clear r7 prior parameter collection */
@ -897,14 +863,12 @@ set_dimm_ctrl:
sync
/********************************************
* Program SDRAM DIMMx Base Address Register
*/
/* Program SDRAM DIMMx Base Address Register */
set_dimm_bar:
READ_SPD(5) /* get # of Ranks */
beq spd_read_fail
andi.r7,r3,0x7
andi. r7,r3,0x7
addi r7,r7,1
READ_SPD(31) /* Read DIMM rank density */
beq spd_read_fail
@ -952,4 +916,3 @@ err_hung: /* hang here for debugging */
b err_hung
#endif /* !SDC_HARDCODED_INIT */

138
board/mpc7448hpc2/mpc7448hpc2.c
View File

@ -33,39 +33,38 @@
#include <74xx_7xx.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
extern void ft_cpu_setup(void *blob, bd_t *bd);
extern void ft_cpu_setup (void *blob, bd_t *bd);
#endif
#undef DEBUG
extern void flush_data_cache(void);
extern void invalidate_l1_instruction_cache(void);
extern void tsi108_init_f(void);
extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
extern void tsi108_init_f (void);
int display_mem_map(void);
int display_mem_map (void);
void after_reloc(ulong dest_addr)
void after_reloc (ulong dest_addr)
{
DECLARE_GLOBAL_DATA_PTR;
/*
* Jump to the main U-Boot board init code
*/
board_init_r((gd_t *) gd, dest_addr);
board_init_r ((gd_t *) gd, dest_addr);
/* NOTREACHED */
}
/*
* Check Board Identity:
*
* report board type
*/
int checkboard(void)
int checkboard (void)
{
int l_type = 0;
printf("BOARD: %s\n", CFG_BOARD_NAME);
printf ("BOARD: %s\n", CFG_BOARD_NAME);
return (l_type);
}
@ -75,19 +74,19 @@ int checkboard(void)
* report calling processor number
*/
int read_pid(void)
int read_pid (void)
{
return 0; /* we are on single CPU platform for a while */
}
long int dram_size(int board_type)
long int dram_size (int board_type)
{
return 0x20000000; /* 256M bytes */
}
long int initdram(int board_type)
long int initdram (int board_type)
{
return dram_size(board_type);
return dram_size (board_type);
}
/* DRAM check routines copied from gw8260 */
@ -114,9 +113,9 @@ long int initdram(int board_type)
/* May cloober fr0. */
/* */
/*********************************************************************/
static void move64(unsigned long long *src, unsigned long long *dest)
static void move64 (unsigned long long *src, unsigned long long *dest)
{
asm("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
"stfd 0, 0(4)" /* *dest = fpr0 */
: : :"fr0"); /* Clobbers fr0 */
return;
@ -183,28 +182,28 @@ unsigned long long pattern[] = {
/* Assumes only one one SDRAM bank */
/* */
/*********************************************************************/
int mem_test_data(void)
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *)CFG_MEMTEST_START;
unsigned long long temp64;
int num_patterns = sizeof(pattern) / sizeof(pattern[0]);
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
for (i = 0; i < num_patterns; i++) {
move64(&(pattern[i]), pmem);
move64(pmem, &temp64);
move64 (&(pattern[i]), pmem);
move64 (pmem, &temp64);
/* hi = (temp64>>32) & 0xffffffff; */
/* lo = temp64 & 0xffffffff; */
/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
/* printf ("\ntemp64 = 0x%08x%08x", hi, lo); */
hi = (pattern[i] >> 32) & 0xffffffff;
lo = pattern[i] & 0xffffffff;
/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
/* printf ("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
if (temp64 != pattern[i]) {
printf("\n Data Test Failed, pattern 0x%08x%08x",
printf ("\n Data Test Failed, pattern 0x%08x%08x",
hi, lo);
return 1;
}
@ -236,7 +235,7 @@ int mem_test_data(void)
/* */
/* */
/*********************************************************************/
int mem_test_address(void)
int mem_test_address (void)
{
volatile unsigned int *pmem =
(volatile unsigned int *)CFG_MEMTEST_START;
@ -251,7 +250,7 @@ int mem_test_address(void)
/* verify each loaction */
for (i = 0; i < size; i++) {
if (pmem[i] != i) {
printf("\n Address Test Failed at 0x%x", i);
printf ("\n Address Test Failed at 0x%x", i);
return 1;
}
}
@ -287,7 +286,7 @@ int mem_test_address(void)
/* */
/* */
/*********************************************************************/
int mem_march(volatile unsigned long long *base,
int mem_march (volatile unsigned long long *base,
unsigned int size,
unsigned long long rmask,
unsigned long long wmask, short read, short write)
@ -299,14 +298,14 @@ int mem_march(volatile unsigned long long *base,
for (i = 0; i < size; i++) {
if (read != 0) {
/* temp = base[i]; */
move64((unsigned long long *)&(base[i]), &temp);
move64 ((unsigned long long *)&(base[i]), &temp);
if (rmask != temp) {
hitemp = (temp >> 32) & 0xffffffff;
lotemp = temp & 0xffffffff;
himask = (rmask >> 32) & 0xffffffff;
lomask = rmask & 0xffffffff;
printf("\n Walking one's test failed: \
printf ("\n Walking one's test failed: \
address = 0x%08x," "\n\texpected \
0x%08x%08x, found 0x%08x%08x", i << 3,\
himask, lomask, hitemp, lotemp);
@ -315,7 +314,7 @@ int mem_march(volatile unsigned long long *base,
}
if (write != 0) {
/* base[i] = wmask; */
move64(&wmask, (unsigned long long *)&(base[i]));
move64 (&wmask, (unsigned long long *)&(base[i]));
}
}
return 0;
@ -348,7 +347,7 @@ int mem_march(volatile unsigned long long *base,
/* */
/* */
/*********************************************************************/
int mem_test_walk(void)
int mem_test_walk (void)
{
unsigned long long mask;
volatile unsigned long long *pmem =
@ -359,32 +358,31 @@ int mem_test_walk(void)
mask = 0x01;
printf("Initial Pass");
mem_march(pmem, size, 0x0, 0x1, 0, 1);
printf ("Initial Pass");
mem_march (pmem, size, 0x0, 0x1, 0, 1);
printf("\b\b\b\b\b\b\b\b\b\b\b\b");
printf(" ");
printf(" ");
printf("\b\b\b\b\b\b\b\b\b\b\b\b");
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
printf (" ");
printf (" ");
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
for (i = 0; i < 63; i++) {
printf("Pass %2d", i + 2);
if (mem_march(pmem, size, mask, mask << 1, 1, 1) != 0) {
/*printf("mask: 0x%x, pass: %d, ", mask, i); */
printf ("Pass %2d", i + 2);
if (mem_march(pmem, size, mask, mask << 1, 1, 1) != 0)
/*printf ("mask: 0x%x, pass: %d, ", mask, i); */
return 1;
}
mask = mask << 1;
printf("\b\b\b\b\b\b\b");
printf ("\b\b\b\b\b\b\b");
}
printf("Last Pass");
printf ("Last Pass");
if (mem_march(pmem, size, 0, mask, 0, 1) != 0) {
/* printf("mask: 0x%x", mask); */
/* printf ("mask: 0x%x", mask); */
return 1;
}
printf("\b\b\b\b\b\b\b\b\b");
printf(" ");
printf("\b\b\b\b\b\b\b\b\b");
printf ("\b\b\b\b\b\b\b\b\b");
printf (" ");
printf ("\b\b\b\b\b\b\b\b\b");
return 0;
}
@ -412,60 +410,58 @@ int mem_test_walk(void)
/* */
/* */
/*********************************************************************/
int testdram(void)
int testdram (void)
{
char *s;
int rundata, runaddress, runwalk;
s = getenv("testdramdata");
s = getenv ("testdramdata");
rundata = (s && (*s == 'y')) ? 1 : 0;
s = getenv("testdramaddress");
s = getenv ("testdramaddress");
runaddress = (s && (*s == 'y')) ? 1 : 0;
s = getenv("testdramwalk");
s = getenv ("testdramwalk");
runwalk = (s && (*s == 'y')) ? 1 : 0;
/* rundata = 1; */
/* runaddress = 0; */
/* runwalk = 0; */
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf("Testing RAM from 0x%08x to 0x%08x ... \
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
printf ("Testing RAM from 0x%08x to 0x%08x ... \
(don't panic... that will take a moment !!!!)\n", \
CFG_MEMTEST_START, CFG_MEMTEST_END);
}
#ifdef CFG_DRAM_TEST_DATA
if (rundata == 1) {
printf("Test DATA ... ");
printf ("Test DATA ... ");
if (mem_test_data () == 1) {
printf("failed \n");
printf ("failed \n");
return 1;
} else
printf("ok \n");
printf ("ok \n");
}
#endif
#ifdef CFG_DRAM_TEST_ADDRESS
if (runaddress == 1) {
printf("Test ADDRESS ... ");
printf ("Test ADDRESS ... ");
if (mem_test_address () == 1) {
printf("failed \n");
printf ("failed \n");
return 1;
} else
printf("ok \n");
printf ("ok \n");
}
#endif
#ifdef CFG_DRAM_TEST_WALK
if (runwalk == 1) {
printf("Test WALKING ONEs ... ");
if (mem_test_walk() == 1) {
printf("failed \n");
printf ("Test WALKING ONEs ... ");
if (mem_test_walk () == 1) {
printf ("failed \n");
return 1;
} else
printf("ok \n");
printf ("ok \n");
}
#endif
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf("passed\n");
}
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
printf ("passed\n");
return 0;
}
@ -473,17 +469,17 @@ int testdram(void)
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
ft_board_setup (void *blob, bd_t *bd)
{
u32 *p;
int len;
ft_cpu_setup(blob, bd);
ft_cpu_setup (blob, bd);
p = ft_get_prop(blob, "/memory/reg", &len);
p = ft_get_prop (blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
*p++ = cpu_to_be32 (bd->bi_memstart);
*p = cpu_to_be32 (bd->bi_memsize);
}
}
#endif

279
board/mpc7448hpc2/tsi108_init.c
View File

@ -33,7 +33,7 @@
#include <asm/processor.h>
#include <tsi108.h>
extern void mpicInit(int verbose);
extern void mpicInit (int verbose);
/*
* Configuration Options
@ -118,11 +118,11 @@ static PLL_CTRL_SET pll0_config[8] = {
static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
/*
* get_board_bus_clk()
* get_board_bus_clk ()
*
* returns the bus clock in Hz.
*/
unsigned long get_board_bus_clk(void)
unsigned long get_board_bus_clk (void)
{
ulong i;
@ -134,37 +134,38 @@ unsigned long get_board_bus_clk(void)
}
/*
* board_early_init_f()
* board_early_init_f ()
*
* board-specific initialization executed from flash
*/
int board_early_init_f(void)
int board_early_init_f (void)
{
DECLARE_GLOBAL_DATA_PTR;
ulong i;
gd->mem_clk = 0;
i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
i = (i >> 20) & 0x07;
i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
CG_PWRUP_STATUS);
i = (i >> 20) & 0x07; /* value of SW4[4:7] */
switch (i) {
case 0:
printf("Using external clock\n");
case 0: /* external clock */
printf ("Using external clock\n");
break;
case 1:
case 1: /* system clock */
gd->mem_clk = gd->bus_clk;
break;
case 4:
case 5:
case 6:
case 4: /* 133 MHz */
case 5: /* 166 MHz */
case 6: /* 200 MHz */
gd->mem_clk = pb_clk_sel[i] * 1000000;
break;
default:
printf("Invalid DDR2 clock setting\n");
printf ("Invalid DDR2 clock setting\n");
return -1;
}
printf("BUS! %d MHz\n", get_board_bus_clk() / 1000000);
printf("MEM! %d MHz\n", gd->mem_clk / 1000000);
printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
return 0;
}
@ -173,7 +174,7 @@ int board_early_init_f(void)
* relocation. Contains code that cannot be executed from flash.
*/
int board_early_init_r(void)
int board_early_init_r (void)
{
ulong temp, i;
ulong reg_val;
@ -187,21 +188,21 @@ int board_early_init_r(void)
*reg_ptr++ = 0x00;
}
__asm__ __volatile__("eieio");
__asm__ __volatile__("sync");
__asm__ __volatile__ ("eieio");
__asm__ __volatile__ ("sync");
/* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
0x80000001);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/* Make sure that OCN_BAR2 decoder is set (to allow following immediate
* read from SDRAM)
*/
temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/*
* Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
@ -226,94 +227,94 @@ int board_early_init_r(void)
*reg_ptr++ = pb2ocn_lut1[i].upper;
}
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/* Base addresses for Cs0, CS1, CS2, CS3 */
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
0x00000000);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
0x00100000);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
0x00200000);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
0x00300000);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/* Masks for HLP banks */
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
0xFFF00000);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
0xFFF00000);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
0xFFF00000);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
0xFFF00000);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/* Set CTRL0 values for banks */
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
0x7FFC44C2);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
0x7FFC44C0);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
0x7FFC44C0);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
0x7FFC44C2);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/* Set banks to latched mode, enabled, and other default settings */
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
0x7C0F2000);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
0x7C0F2000);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
0x7C0F2000);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
0x7C0F2000);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/*
* Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
* value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
*/
out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
0xE0000011);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/* Make sure that OCN_BAR2 decoder is set (to allow following
* immediate read from SDRAM)
*/
temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/*
* SRI: At this point we have enabled the HLP banks. That means we can
@ -327,7 +328,7 @@ int board_early_init_r(void)
* Taiga Rev. 2.
*/
env_init();
env_init ();
#ifndef DISABLE_PBM
@ -336,12 +337,11 @@ int board_early_init_r(void)
* by PBM that are different from ones set after reset.
*/
temp = get_cpu_type();
temp = get_cpu_type ();
if ((CPU_750FX == temp) || (CPU_750GX == temp)) {
out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
if ((CPU_750FX == temp) || (CPU_750GX == temp))
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
0x00009955);
}
#endif /* DISABLE_PBM */
#ifdef CONFIG_PCI
@ -350,37 +350,37 @@ int board_early_init_r(void)
*/
/* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0_UPPER,
0);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
PCI_PFAB_BAR0_UPPER, 0);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
0xFB000001);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
temp =
in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
temp = in32(CFG_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
temp &= ~0xFF00; /* Clear the BUS_NUM field */
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
temp);
/* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
0);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/* This register is on the PCI side to interpret the address it receives
* and maps it as a IO address.
*/
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
0xFA000001);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/*
* Map PCI/X Memory Space
@ -438,22 +438,22 @@ int board_early_init_r(void)
reg_val = 0x00007100;
#endif
__asm__ __volatile__("eieio");
__asm__ __volatile__("sync");
__asm__ __volatile__ ("eieio");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
reg_val);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/* Set 64-bit PCI bus address for system memory
* ( 0 is the best choice for easy mapping)
*/
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
0x00000000);
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
0x00000000);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
#ifndef DISABLE_PBM
/*
@ -483,8 +483,8 @@ int board_early_init_r(void)
reg_val += 0x01000000;
}
__asm__ __volatile__("eieio");
__asm__ __volatile__("sync");
__asm__ __volatile__ ("eieio");
__asm__ __volatile__ ("sync");
/* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
@ -493,35 +493,35 @@ int board_early_init_r(void)
PCI_P2O_PAGE_SIZES);
reg_val &= ~0x00FF;
reg_val |= 0x0071;
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
reg_val);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/* Set 64-bit base PCI bus address for window (0x20000000) */
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
0x00000000);
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
0x20000000);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
#endif /* !DISABLE_PBM */
#ifdef ENABLE_PCI_CSR_BAR
/* open if required access to Tsi108 CSRs from the PCI/X bus */
/* enable BAR0 on the PCI/X bus */
reg_val =
in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
reg_val = in32(CFG_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
reg_val |= 0x02;
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
reg_val);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
0x00000000);
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
CFG_TSI108_CSR_BASE);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
#endif
@ -531,8 +531,8 @@ int board_early_init_r(void)
reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
reg_val |= 0x06;
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
__asm__ __volatile__ ("sync");
#endif /* CONFIG_PCI */
@ -545,18 +545,18 @@ int board_early_init_r(void)
* PB_INT[3] -> MCP (CPU1)
* Set interrupt controller outputs as Level_Sensitive/Active_Low
*/
out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
__asm__ __volatile__ ("sync");
/*
* Ensure that Machine Check exception is enabled
* We need it to support PCI Bus probing (configuration reads)
*/
reg_val = mfmsr();
reg_val = mfmsr ();
mtmsr(reg_val | MSR_ME);
return 0;
@ -567,7 +567,7 @@ int board_early_init_r(void)
* used in the misc_init_r function
*/
unsigned long get_l2cr(void)
unsigned long get_l2cr (void)
{
unsigned long l2controlreg;
asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
@ -581,46 +581,49 @@ unsigned long get_l2cr(void)
*
*/
int misc_init_r(void)
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
ulong i;
/* Ensure that Spread-Spectrum is disabled */
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
/* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
* Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
*/
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x002e0044); /* D = 0.25% */
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, 0x00000039); /* BWADJ */
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
0x002e0044); /* D = 0.25% */
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
0x00000039); /* BWADJ */
/* Initialize PLL0: CG_PB_CLKO */
/* Detect PB clock freq. */
i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
out32(CFG_TSI108_CSR_BASE +
out32 (CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
out32(CFG_TSI108_CSR_BASE +
out32 (CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
/* Wait and set SSEN for both PLL0 and 1 */
udelay(1000);
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x802e0044); /* D=0.25% */
out32(CFG_TSI108_CSR_BASE +
udelay (1000);
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
0x802e0044); /* D=0.25% */
out32 (CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
0x80000000 | pll0_config[i].ctrl0);
#endif /* CFG_CLK_SPREAD */
#ifdef CFG_L2
l2cache_enable();
l2cache_enable ();
#endif
printf("BUS: %d MHz\n", gd->bus_clk / 1000000);
printf("MEM: %d MHz\n", gd->mem_clk / 1000000);
printf ("BUS: %d MHz\n", gd->bus_clk / 1000000);
printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
/*
* All the information needed to print the cache details is avaiblable
@ -629,31 +632,31 @@ int misc_init_r(void)
* So this seems like a good place to print all this information
*/
printf("CACHE: ");
printf ("CACHE: ");
switch (get_cpu_type()) {
case CPU_7447A:
printf("L1 Instruction cache - 32KB 8-way");
(get_hid0() & (1 << 15)) ? printf(" ENABLED\n") :
printf(" DISABLED\n");
printf(" L1 Data cache - 32KB 8-way");
(get_hid0() & (1 << 14)) ? printf(" ENABLED\n") :
printf(" DISABLED\n");
printf(" Unified L2 cache - 512KB 8-way");
(get_l2cr() & (1 << 31)) ? printf(" ENABLED\n") :
printf(" DISABLED\n");
printf("\n");
printf ("L1 Instruction cache - 32KB 8-way");
(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("L1 Data cache - 32KB 8-way");
(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("Unified L2 cache - 512KB 8-way");
(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("\n");
break;
case CPU_7448:
printf("L1 Instruction cache - 32KB 8-way");
(get_hid0() & (1 << 15)) ? printf(" ENABLED\n") :
printf(" DISABLED\n");
printf(" L1 Data cache - 32KB 8-way");
(get_hid0() & (1 << 14)) ? printf(" ENABLED\n") :
printf(" DISABLED\n");
printf(" Unified L2 cache - 1MB 8-way");
(get_l2cr() & (1 << 31)) ? printf(" ENABLED\n") :
printf(" DISABLED\n");
printf ("L1 Instruction cache - 32KB 8-way");
(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("L1 Data cache - 32KB 8-way");
(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("Unified L2 cache - 1MB 8-way");
(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
break;
default:
break;

14
cpu/74xx_7xx/cpu.c
View File

@ -303,7 +303,7 @@ watchdog_reset(void)
#ifdef CONFIG_OF_FLAT_TREE
void
ft_cpu_setup(void *blob, bd_t *bd)
ft_cpu_setup (void *blob, bd_t *bd)
{
u32 *p;
ulong clock;
@ -311,18 +311,18 @@ ft_cpu_setup(void *blob, bd_t *bd)
clock = bd->bi_busfreq;
p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
p = ft_get_prop (blob, "/cpus/" OF_CPU "/bus-frequency", &len);
if (p != NULL)
*p = cpu_to_be32(clock);
*p = cpu_to_be32 (clock);
#if defined(CONFIG_TSI108_ETH)
p = ft_get_prop(blob, "/" OF_TSI "/ethernet@6200/address", &len);
memcpy(p, bd->bi_enetaddr, 6);
p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6200/address", &len);
memcpy (p, bd->bi_enetaddr, 6);
#endif
#if defined(CONFIG_HAS_ETH1)
p = ft_get_prop(blob, "/" OF_TSI "/ethernet@6600/address", &len);
memcpy(p, bd->bi_enet1addr, 6);
p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6600/address", &len);
memcpy (p, bd->bi_enet1addr, 6);
#endif
}
#endif

18
cpu/74xx_7xx/speed.c
View File

@ -31,7 +31,7 @@
DECLARE_GLOBAL_DATA_PTR;
extern unsigned long get_board_bus_clk(void);
extern unsigned long get_board_bus_clk (void);
static const int hid1_multipliers_x_10[] = {
25, /* 0000 - 2.5x */
@ -127,16 +127,17 @@ int get_clocks (void)
ulong clock = 0;
#ifdef CFG_CONFIG_BUS_CLK
gd->bus_clk = get_board_bus_clk();
gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */
#else
gd->bus_clk = CFG_BUS_CLK;
gd->bus_clk = CFG_BUS_CLK; /* bus clock is a fixed frequency */
#endif
/* calculate the clock frequency based upon the CPU type */
switch (get_cpu_type()) {
case CPU_7447A:
case CPU_7448:
clock = (gd->bus_clk / 10) * hid1_7447A_multipliers_x_10[(get_hid1 () >> 12) & 0x1F];
clock = (gd->bus_clk / 10) *
hid1_7447A_multipliers_x_10[(get_hid1 () >> 12) & 0x1F];
break;
case CPU_7455:
@ -146,12 +147,14 @@ int get_clocks (void)
* Make sure division is done before multiplication to prevent 32-bit
* arithmetic overflows which will cause a negative number
*/
clock = (gd->bus_clk / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF];
clock = (gd->bus_clk / 10) *
hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF];
break;
case CPU_750GX:
case CPU_750FX:
clock = gd->bus_clk * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
clock = gd->bus_clk *
hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
break;
case CPU_7450:
@ -168,7 +171,8 @@ int get_clocks (void)
* Make sure division is done before multiplication to prevent 32-bit
* arithmetic overflows which will cause a negative number
*/
clock = (gd->bus_clk / 10) * hid1_multipliers_x_10[get_hid1 () >> 28];
clock = (gd->bus_clk / 10) *
hid1_multipliers_x_10[get_hid1 () >> 28];
break;
case CPU_UNKNOWN:

8
doc/README.mpc7448hpc2
View File

@ -39,7 +39,6 @@ The mapping is:
0xff00_0000 0xff80_0000 FLASH (boot flash) 8M
0xff80_0000 0xffff_ffff FLASH (second half flash) 8M
Using Flash
-----------
@ -67,16 +66,13 @@ it into the secondary bank:
erase ff000000 ff080000
cp.b 10000 ff000000 80000
After copying the image into the second bank of flash, be sure to toggle
SW3[4] on board before resetting the board in order to set the
secondary bank as the boot-bank.
Board Switches
----------------------
Most switches on the board should not be changed. The most frequent
user-settable switches on the board are used to configure
the flash banks and determining the PCI frequency.
@ -111,7 +107,6 @@ SW2[1-6]: CPU core frequency
This table shows only a subset of available frequency options; see the CPU
hardware specifications for more information.
SW2[7-8]: Bus Protocol and CPU Reset Option
7
@ -124,7 +119,6 @@ SW2[7-8]: Bus Protocol and CPU Reset Option
SW2=0 TSI108 can cause CPU reset
SW2=1 TSI108 can not cause CPU reset
SW3[1-8] system options
123
@ -167,7 +161,6 @@ SW4[1-3]: System bus frequency
SW4=110 200 only for MPC7448
others reserved
SW4[4-6]: DDR2 SDRAM frequency
Bus Frequency (MHz)
@ -179,7 +172,6 @@ SW4[4-6]: DDR2 SDRAM frequency
SW4=110 200
others reserved
SW4[7-8]: PCI/PCI-X frequency control
7
-

201
drivers/tsi108_eth.c
View File

@ -46,7 +46,9 @@
#endif
#if TSI108_ETH_DEBUG > 0
#define debug_lev(lev, fmt, args...) if (lev <= TSI108_ETH_DEBUG) printf("%s %d: " fmt, __FUNCTION__, __LINE__, ##args)
#define debug_lev(lev, fmt, args...) \
if (lev <= TSI108_ETH_DEBUG) \
printf ("%s %d: " fmt, __FUNCTION__, __LINE__, ##args)
#else
#define debug_lev(lev, fmt, args...) do{}while(0)
#endif
@ -350,7 +352,7 @@
#define SPEC_STAT_PAGE_RCVD (1 << 12)
#define SPEC_STAT_RESOLVED (1 << 11) /* Speed and Duplex Resolved */
#define SPEC_STAT_LINK_UP (1 << 10)
#define SPEC_STAT_CABLE_LEN_MASK (7 << 7) /* Cable Length (100/1000 modes only) */
#define SPEC_STAT_CABLE_LEN_MASK (7 << 7)/* Cable Length (100/1000 modes only) */
#define SPEC_STAT_MDIX (1 << 6)
#define SPEC_STAT_POLARITY (1 << 1)
#define SPEC_STAT_JABBER (1 << 0)
@ -432,14 +434,14 @@ static struct dma_descriptor rx_descr_array[NUM_RX_DESC]
static struct dma_descriptor *rx_descr_current;
static int tsi108_eth_probe(struct eth_device *dev, bd_t * bis);
static int tsi108_eth_send(struct eth_device *dev,
static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis);
static int tsi108_eth_send (struct eth_device *dev,
volatile void *packet, int length);
static int tsi108_eth_recv(struct eth_device *dev);
static void tsi108_eth_halt(struct eth_device *dev);
static unsigned int read_phy(unsigned int base,
static int tsi108_eth_recv (struct eth_device *dev);
static void tsi108_eth_halt (struct eth_device *dev);
static unsigned int read_phy (unsigned int base,
unsigned int phy_addr, unsigned int phy_reg);
static void write_phy(unsigned int base,
static void write_phy (unsigned int base,
unsigned int phy_addr,
unsigned int phy_reg, unsigned int phy_data);
@ -447,15 +449,15 @@ static void write_phy(unsigned int base,
/*
* print phy debug infomation
*/
static void dump_phy_regs(unsigned int phy_addr)
static void dump_phy_regs (unsigned int phy_addr)
{
int i;
printf("PHY %d registers\n", phy_addr);
printf ("PHY %d registers\n", phy_addr);
for (i = 0; i <= 30; i++) {
printf("%2d 0x%04x\n", i, read_phy(ETH_BASE, phy_addr, i));
printf ("%2d 0x%04x\n", i, read_phy (ETH_BASE, phy_addr, i));
}
printf("\n");
printf ("\n");
}
#else
@ -466,27 +468,27 @@ static void dump_phy_regs(unsigned int phy_addr)
/*
* print debug infomation
*/
static void tx_diag_regs(unsigned int base)
static void tx_diag_regs (unsigned int base)
{
int i;
unsigned long dummy;
printf("TX diagnostics registers\n");
printf ("TX diagnostics registers\n");
reg_TX_DIAGNOSTIC_ADDR(base) = 0x00 | TX_DIAGNOSTIC_ADDR_AI;
udelay(1000);
udelay (1000);
dummy = reg_TX_DIAGNOSTIC_DATA(base);
for (i = 0x00; i <= 0x05; i++) {
udelay(1000);
printf("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
udelay (1000);
printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
}
reg_TX_DIAGNOSTIC_ADDR(base) = 0x40 | TX_DIAGNOSTIC_ADDR_AI;
udelay(1000);
udelay (1000);
dummy = reg_TX_DIAGNOSTIC_DATA(base);
for (i = 0x40; i <= 0x47; i++) {
udelay(1000);
printf("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
udelay (1000);
printf ("0x%02x 0x%08x\n", i, reg_TX_DIAGNOSTIC_DATA(base));
}
printf("\n");
printf ("\n");
}
#else
@ -497,27 +499,27 @@ static void tx_diag_regs(unsigned int base)
/*
* print debug infomation
*/
static void rx_diag_regs(unsigned int base)
static void rx_diag_regs (unsigned int base)
{
int i;
unsigned long dummy;
printf("RX diagnostics registers\n");
printf ("RX diagnostics registers\n");
reg_RX_DIAGNOSTIC_ADDR(base) = 0x00 | RX_DIAGNOSTIC_ADDR_AI;
udelay(1000);
udelay (1000);
dummy = reg_RX_DIAGNOSTIC_DATA(base);
for (i = 0x00; i <= 0x05; i++) {
udelay(1000);
printf("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
udelay (1000);
printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
}
reg_RX_DIAGNOSTIC_ADDR(base) = 0x40 | RX_DIAGNOSTIC_ADDR_AI;
udelay(1000);
udelay (1000);
dummy = reg_RX_DIAGNOSTIC_DATA(base);
for (i = 0x08; i <= 0x0a; i++) {
udelay(1000);
printf("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
udelay (1000);
printf ("0x%02x 0x%08x\n", i, reg_RX_DIAGNOSTIC_DATA(base));
}
printf("\n");
printf ("\n");
}
#else
@ -528,15 +530,15 @@ static void rx_diag_regs(unsigned int base)
/*
* print debug infomation
*/
static void debug_mii_regs(unsigned int base)
static void debug_mii_regs (unsigned int base)
{
printf("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base));
printf("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base));
printf("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base));
printf("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base));
printf("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base));
printf("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base));
printf("\n");
printf ("MII_MGMT_CONFIG 0x%08x\n", reg_MII_MGMT_CONFIG(base));
printf ("MII_MGMT_COMMAND 0x%08x\n", reg_MII_MGMT_COMMAND(base));
printf ("MII_MGMT_ADDRESS 0x%08x\n", reg_MII_MGMT_ADDRESS(base));
printf ("MII_MGMT_CONTROL 0x%08x\n", reg_MII_MGMT_CONTROL(base));
printf ("MII_MGMT_STATUS 0x%08x\n", reg_MII_MGMT_STATUS(base));
printf ("MII_MGMT_INDICATORS 0x%08x\n", reg_MII_MGMT_INDICATORS(base));
printf ("\n");
}
#else
@ -546,15 +548,15 @@ static void debug_mii_regs(unsigned int base)
/*
* Wait until the phy bus is non-busy
*/
static void phy_wait(unsigned int base, unsigned int condition)
static void phy_wait (unsigned int base, unsigned int condition)
{
int timeout;
timeout = 0;
while (reg_MII_MGMT_INDICATORS(base) & condition) {
udelay(10);
udelay (10);
if (++timeout > 10000) {
printf("ERROR: timeout waiting for phy bus (%d)\n",
printf ("ERROR: timeout waiting for phy bus (%d)\n",
condition);
break;
}
@ -564,12 +566,12 @@ static void phy_wait(unsigned int base, unsigned int condition)
/*
* read phy register
*/
static unsigned int read_phy(unsigned int base,
static unsigned int read_phy (unsigned int base,
unsigned int phy_addr, unsigned int phy_reg)
{
unsigned int value;
phy_wait(base, MII_MGMT_INDICATORS_BUSY);
phy_wait (base, MII_MGMT_INDICATORS_BUSY);
reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg;
@ -580,7 +582,7 @@ static unsigned int read_phy(unsigned int base,
reg_MII_MGMT_COMMAND(base) = MII_MGMT_COMMAND_READ_CYCLE;
/* wait for the read to complete */
phy_wait(base,
phy_wait (base,
MII_MGMT_INDICATORS_NOT_VALID | MII_MGMT_INDICATORS_BUSY);
value = reg_MII_MGMT_STATUS(base);
@ -593,11 +595,11 @@ static unsigned int read_phy(unsigned int base,
/*
* write phy register
*/
static void write_phy(unsigned int base,
static void write_phy (unsigned int base,
unsigned int phy_addr,
unsigned int phy_reg, unsigned int phy_data)
{
phy_wait(base, MII_MGMT_INDICATORS_BUSY);
phy_wait (base, MII_MGMT_INDICATORS_BUSY);
reg_MII_MGMT_ADDRESS(base) = (phy_addr << 8) | phy_reg;
@ -611,7 +613,7 @@ static void write_phy(unsigned int base,
/*
* configure the marvell 88e1111 phy
*/
static int marvell_88e_phy_config(struct eth_device *dev, int *speed,
static int marvell_88e_phy_config (struct eth_device *dev, int *speed,
int *duplex)
{
unsigned long base;
@ -630,40 +632,39 @@ static int marvell_88e_phy_config(struct eth_device *dev, int *speed,
phy_addr = (unsigned long)dev->priv;
/* Take the PHY out of reset. */
write_phy(ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET);
write_phy (ETH_BASE, phy_addr, PHY_CTRL_REG, PHY_CTRL_RESET);
/* Wait for the reset process to complete. */
udelay(10);
udelay (10);
timeout = 0;
while ((phy_status =
read_phy(ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) {
udelay(10);
read_phy (ETH_BASE, phy_addr, PHY_CTRL_REG)) & PHY_CTRL_RESET) {
udelay (10);
if (++timeout > 10000) {
printf("ERROR: timeout waiting for phy reset\n");
printf ("ERROR: timeout waiting for phy reset\n");
break;
}
}
/* TBI Configuration. */
write_phy(base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE |
write_phy (base, TBI_ADDR, TBI_CONTROL_2, TBI_CONTROL_2_G_MII_MODE |
TBI_CONTROL_2_RECEIVE_CLOCK_SELECT);
/* Wait for the link to be established. */
timeout = 0;
do {
udelay(20000);
phy_status = read_phy(ETH_BASE, phy_addr, PHY_STATUS_REG);
udelay (20000);
phy_status = read_phy (ETH_BASE, phy_addr, PHY_STATUS_REG);
if (++timeout > 100) {
debug_lev(1, "ERROR: unable to establish link!!!\n");
break;
}
} while ((phy_status & PHY_STAT_LINK_UP) == 0);
if ((phy_status & PHY_STAT_LINK_UP) == 0) {
if ((phy_status & PHY_STAT_LINK_UP) == 0)
return 0;
}
value = 0;
phy_spec_status = read_phy(ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
if (phy_spec_status & SPEC_STAT_RESOLVED) {
switch (phy_spec_status & SPEC_STAT_SPEED_MASK) {
case SPEED_1000:
@ -681,45 +682,41 @@ static int marvell_88e_phy_config(struct eth_device *dev, int *speed,
if (phy_spec_status & SPEC_STAT_FULL_DUP) {
phy_duplex = LINK_DUPLEX_FULL;
value |= PHY_CTRL_FULL_DUPLEX;
} else {
} else
phy_duplex = LINK_DUPLEX_HALF;
}
}
/* set TBI speed */
write_phy(base, TBI_ADDR, PHY_CTRL_REG, value);
write_phy(base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060);
write_phy (base, TBI_ADDR, PHY_CTRL_REG, value);
write_phy (base, TBI_ADDR, PHY_AN_ADV_REG, 0x0060);
#if TSI108_ETH_DEBUG > 0
printf("%s link is up", dev->name);
phy_spec_status = read_phy(ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
printf ("%s link is up", dev->name);
phy_spec_status = read_phy (ETH_BASE, phy_addr, MV1111_SPEC_STAT_REG);
if (phy_spec_status & SPEC_STAT_RESOLVED) {
switch (phy_speed) {
case LINK_SPEED_1000:
printf(", 1000 Mbps");
printf (", 1000 Mbps");
break;
case LINK_SPEED_100:
printf(", 100 Mbps");
printf (", 100 Mbps");
break;
case LINK_SPEED_10:
printf(", 10 Mbps");
printf (", 10 Mbps");
break;
}
if (phy_duplex == LINK_DUPLEX_FULL) {
printf(", Full duplex");
} else {
printf(", Half duplex");
if (phy_duplex == LINK_DUPLEX_FULL)
printf (", Full duplex");
else
printf (", Half duplex");
}
}
printf("\n");
printf ("\n");
#endif
dump_phy_regs(TBI_ADDR);
if (speed) {
dump_phy_regs (TBI_ADDR);
if (speed)
*speed = phy_speed;
}
if (duplex) {
if (duplex)
*duplex = phy_duplex;
}
return 1;
}
@ -729,7 +726,7 @@ static int marvell_88e_phy_config(struct eth_device *dev, int *speed,
*
* register the tsi108 ethernet controllers with the multi-ethernet system
*/
int tsi108_eth_initialize(bd_t * bis)
int tsi108_eth_initialize (bd_t * bis)
{
struct eth_device *dev;
int index;
@ -737,7 +734,7 @@ int tsi108_eth_initialize(bd_t * bis)
for (index = 0; index < CONFIG_TSI108_ETH_NUM_PORTS; index++) {
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
sprintf(dev->name, "TSI108_eth%d", index);
sprintf (dev->name, "TSI108_eth%d", index);
dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET);
dev->priv = (void *)(phy_address[index]);
@ -754,7 +751,7 @@ int tsi108_eth_initialize(bd_t * bis)
/*
* probe for and initialize a single ethernet interface
*/
static int tsi108_eth_probe(struct eth_device *dev, bd_t * bis)
static int tsi108_eth_probe (struct eth_device *dev, bd_t * bis)
{
unsigned long base;
unsigned long value;
@ -794,25 +791,23 @@ static int tsi108_eth_probe(struct eth_device *dev, bd_t * bis)
reg_STATION_ADDRESS_2(base) = (dev->enetaddr[1] << 24) |
(dev->enetaddr[0] << 16);
if (marvell_88e_phy_config(dev, &speed, &duplex) == 0) {
if (marvell_88e_phy_config(dev, &speed, &duplex) == 0)
return 0;
}
value =
MAC_CONFIG_2_PREAMBLE_LENGTH(7) | MAC_CONFIG_2_PAD_CRC |
MAC_CONFIG_2_CRC_ENABLE;
if (speed == LINK_SPEED_1000) {
if (speed == LINK_SPEED_1000)
value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_BYTE);
} else {
else {
value |= MAC_CONFIG_2_INTERFACE_MODE(INTERFACE_MODE_NIBBLE);
reg_PORT_CONTROL(base) |= PORT_CONTROL_SPD;
}
if (duplex == LINK_DUPLEX_FULL) {
value |= MAC_CONFIG_2_FULL_DUPLEX;
reg_PORT_CONTROL(base) &= ~PORT_CONTROL_BPT;
} else {
} else
reg_PORT_CONTROL(base) |= PORT_CONTROL_BPT;
}
reg_MAC_CONFIG_2(base) = value;
reg_RX_CONFIG(base) = RX_CONFIG_SE;
@ -875,7 +870,7 @@ static int tsi108_eth_probe(struct eth_device *dev, bd_t * bis)
/*
* send a packet
*/
static int tsi108_eth_send(struct eth_device *dev,
static int tsi108_eth_send (struct eth_device *dev,
volatile void *packet, int length)
{
unsigned long base;
@ -894,9 +889,8 @@ static int tsi108_eth_send(struct eth_device *dev,
(unsigned long)tx_descr +
sizeof(struct dma_descriptor));
if (timeout != 0) {
udelay(15);
}
if (timeout != 0)
udelay (15);
if (++timeout > 10000) {
tx_diag_regs(base);
debug_lev(1,
@ -908,7 +902,7 @@ static int tsi108_eth_send(struct eth_device *dev,
status = le32_to_cpu(tx_descr->config_status);
if ((status & DMA_DESCR_TX_OK) == 0) {
#ifdef TX_PRINT_ERRORS
printf("TX packet error: 0x%08x\n %s%s%s%s\n", status,
printf ("TX packet error: 0x%08x\n %s%s%s%s\n", status,
status & DMA_DESCR_TX_OK ? "tx error, " : "",
status & DMA_DESCR_TX_RETRY_LIMIT ?
"retry limit reached, " : "",
@ -918,7 +912,7 @@ static int tsi108_eth_send(struct eth_device *dev,
#endif
}
debug_lev(9, "sending packet %d\n", length);
debug_lev (9, "sending packet %d\n", length);
tx_descr->start_addr0 = cpu_to_le32((vuint32) packet);
tx_descr->start_addr1 = 0;
tx_descr->next_descr_addr0 = 0;
@ -946,7 +940,7 @@ static int tsi108_eth_send(struct eth_device *dev,
/*
* Check for received packets and send them up the protocal stack
*/
static int tsi108_eth_recv(struct eth_device *dev)
static int tsi108_eth_recv (struct eth_device *dev)
{
struct dma_descriptor *rx_descr;
unsigned long base;
@ -957,7 +951,7 @@ static int tsi108_eth_recv(struct eth_device *dev)
base = dev->iobase;
/* make sure we see the changes made by the DMA engine */
invalidate_dcache_range((unsigned long)rx_descr_array,
invalidate_dcache_range ((unsigned long)rx_descr_array,
(unsigned long)rx_descr_array +
sizeof(rx_descr_array));
@ -968,7 +962,7 @@ static int tsi108_eth_recv(struct eth_device *dev)
status = le32_to_cpu(rx_descr->config_status);
if (status & DMA_DESCR_RX_BAD_FRAME) {
#ifdef RX_PRINT_ERRORS
printf("RX packet error: 0x%08x\n %s%s%s%s%s%s\n",
printf ("RX packet error: 0x%08x\n %s%s%s%s%s%s\n",
status,
status & DMA_DESCR_RX_FRAME_IS_TYPE ? "too big, "
: "",
@ -989,25 +983,24 @@ static int tsi108_eth_recv(struct eth_device *dev)
/*** process packet ***/
buffer =
(volatile uchar
*)(le32_to_cpu(rx_descr->start_addr0));
NetReceive(buffer, length);
*)(le32_to_cpu (rx_descr->start_addr0));
NetReceive (buffer, length);
invalidate_dcache_range((unsigned long)buffer,
invalidate_dcache_range ((unsigned long)buffer,
(unsigned long)buffer +
RX_BUFFER_SIZE);
}
/* Give this buffer back to the DMA engine */
rx_descr->vlan_byte_count = 0;
rx_descr->config_status = cpu_to_le32((RX_BUFFER_SIZE << 16) |
rx_descr->config_status = cpu_to_le32 ((RX_BUFFER_SIZE << 16) |
DMA_DESCR_RX_OWNER);
/* move descriptor pointer forward */
rx_descr =
(struct dma_descriptor
*)(le32_to_cpu(rx_descr->next_descr_addr0));
if (rx_descr == 0) {
*)(le32_to_cpu (rx_descr->next_descr_addr0));
if (rx_descr == 0)
rx_descr = &rx_descr_array[0];
}
}
/* remember where we are for next time */
rx_descr_current = rx_descr;
@ -1026,7 +1019,7 @@ static int tsi108_eth_recv(struct eth_device *dev)
/*
* disable an ethernet interface
*/
static void tsi108_eth_halt(struct eth_device *dev)
static void tsi108_eth_halt (struct eth_device *dev)
{
unsigned long base;

46
drivers/tsi108_i2c.c
View File

@ -23,10 +23,9 @@
*/
#include <config.h>
#include <common.h>
#ifdef CONFIG_TSI108_I2C
#include <common.h>
#include <tsi108.h>
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
@ -35,7 +34,7 @@
#undef DEBUG_I2C
#ifdef DEBUG_I2C
#define DPRINT(x) printf(x)
#define DPRINT(x) printf (x)
#else
#define DPRINT(x)
#endif
@ -43,7 +42,7 @@
/* All functions assume that Tsi108 I2C block is the only master on the bus */
/* I2C read helper function */
static int i2c_read_byte(
static int i2c_read_byte (
uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */
uchar chip_addr,/* I2C device address on the bus */
uint byte_addr, /* Byte address within I2C device */
@ -55,19 +54,17 @@ static int i2c_read_byte(
u32 op_status = TSI108_I2C_TIMEOUT_ERR;
u32 chan_offset = TSI108_I2C_OFFSET;
DPRINT(("I2C read_byte() %d 0x%02x 0x%02x\n",
DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n",
i2c_chan, chip_addr, byte_addr));
if (0 != i2c_chan) {
if (0 != i2c_chan)
chan_offset = TSI108_I2C_SDRAM_OFFSET;
}
/* Check if I2C operation is in progress */
temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS |
I2C_CNTRL2_START))
) {
I2C_CNTRL2_START))) {
/* Set device address and operation (read = 0) */
temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) |
((chip_addr >> 3) & 0x0F);
@ -108,7 +105,7 @@ static int i2c_read_byte(
/* report HW error */
op_status = TSI108_I2C_IF_ERROR;
DPRINT(("I2C HW error reported: 0x%02x\n", temp));
DPRINT (("I2C HW error reported: 0x%02x\n", temp));
}
break;
@ -117,10 +114,10 @@ static int i2c_read_byte(
} else {
op_status = TSI108_I2C_IF_BUSY;
DPRINT(("I2C Transaction start failed: 0x%02x\n", temp));
DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
}
DPRINT(("I2C read_byte() status: 0x%02x\n", op_status));
DPRINT (("I2C read_byte() status: 0x%02x\n", op_status));
return op_status;
}
@ -141,7 +138,8 @@ static int i2c_read_byte(
* Returns: 0 on success, not 0 on failure
*/
int i2c_read(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len)
int i2c_read (uchar chip_addr, uint byte_addr, int alen,
uchar * buffer, int len)
{
u32 op_status = TSI108_I2C_PARAM_ERR;
u32 i2c_if = 0;
@ -159,20 +157,20 @@ int i2c_read(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len)
buffer++);
if (TSI108_I2C_SUCCESS != op_status) {
DPRINT(("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
break;
}
}
}
DPRINT(("I2C read() status: 0x%02x\n", op_status));
DPRINT (("I2C read() status: 0x%02x\n", op_status));
return op_status;
}
/* I2C write helper function */
static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */
static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */
uint byte_addr, /* Byte address within I2C device */
uchar * buffer /* pointer to data buffer */
)
@ -210,7 +208,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */
/* Wait until operation completed */
do {
// Read I2C operation status
/* Read I2C operation status */
temp =
*(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
I2C_CNTRL2);
@ -227,7 +225,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */
/* report detected HW error */
op_status = TSI108_I2C_IF_ERROR;
DPRINT(("I2C HW error reported: 0x%02x\n", temp));
DPRINT (("I2C HW error reported: 0x%02x\n", temp));
}
break;
@ -237,7 +235,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */
} else {
op_status = TSI108_I2C_IF_BUSY;
DPRINT(("I2C Transaction start failed: 0x%02x\n", temp));
DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
}
return op_status;
@ -256,7 +254,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */
* Returns: 0 on success, not 0 on failure
*/
int i2c_write(uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
int len)
{
u32 op_status = TSI108_I2C_PARAM_ERR;
@ -265,10 +263,10 @@ int i2c_write(uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
while (len--) {
op_status =
i2c_write_byte(chip_addr, byte_addr++, buffer++);
i2c_write_byte (chip_addr, byte_addr++, buffer++);
if (TSI108_I2C_SUCCESS != op_status) {
DPRINT(("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len));
DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len));
break;
}
@ -284,7 +282,7 @@ int i2c_write(uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
* Returns 0 if a chip responded, not 0 on failure.
*/
int i2c_probe(uchar chip)
int i2c_probe (uchar chip)
{
u32 tmp;
@ -293,7 +291,7 @@ int i2c_probe(uchar chip)
* The Tsi108 HW doesn't support sending just the chip address
* and checkong for an <ACK> back.
*/
return i2c_read(chip, 0, 1, (char *)&tmp, 1);
return i2c_read (chip, 0, 1, (char *)&tmp, 1);
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */

34
drivers/tsi108_pci.c
View File

@ -36,7 +36,7 @@
struct pci_controller local_hose;
void tsi108_clear_pci_error(void)
void tsi108_clear_pci_error (void)
{
u32 err_stat, err_addr, pci_stat;
@ -79,11 +79,11 @@ void tsi108_clear_pci_error(void)
return;
}
unsigned int __get_pci_config_dword(u32 addr)
unsigned int __get_pci_config_dword (u32 addr)
{
unsigned int retval;
__asm__ __volatile__(" lwbrx %0,0,%1\n"
__asm__ __volatile__ (" lwbrx %0,0,%1\n"
"1: eieio\n"
"2:\n"
".section .fixup,\"ax\"\n"
@ -97,53 +97,53 @@ unsigned int __get_pci_config_dword(u32 addr)
return (retval);
}
static int tsi108_read_config_dword(struct pci_controller *hose,
static int tsi108_read_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 * value)
{
dev &= (CFG_PCI_CFG_SIZE - 1);
dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc));
*value = __get_pci_config_dword(dev);
if (0xFFFFFFFF == *value)
tsi108_clear_pci_error();
tsi108_clear_pci_error ();
return 0;
}
static int tsi108_write_config_dword(struct pci_controller *hose,
static int tsi108_write_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value)
{
dev &= (CFG_PCI_CFG_SIZE - 1);
dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc));
out_le32((volatile unsigned *)dev, value);
out_le32 ((volatile unsigned *)dev, value);
return 0;
}
void pci_init_board(void)
void pci_init_board (void)
{
struct pci_controller *hose = (struct pci_controller *)&local_hose;
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0,
pci_set_region (hose->regions + 0,
CFG_PCI_MEMORY_BUS,
CFG_PCI_MEMORY_PHYS,
CFG_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
pci_set_region (hose->regions + 1,
CFG_PCI_MEM_BUS,
CFG_PCI_MEM_PHYS, CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region(hose->regions + 2,
pci_set_region (hose->regions + 2,
CFG_PCI_IO_BUS,
CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
hose->region_count = 3;
pci_set_ops(hose,
pci_set_ops (hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
tsi108_read_config_dword,
@ -151,22 +151,22 @@ void pci_init_board(void)
pci_hose_write_config_word_via_dword,
tsi108_write_config_dword);
pci_register_hose(hose);
pci_register_hose (hose);
hose->last_busno = pci_hose_scan(hose);
hose->last_busno = pci_hose_scan (hose);
debug("Done PCI initialization\n");
debug ("Done PCI initialization\n");
return;
}
#ifdef CONFIG_OF_FLAT_TREE
void
ft_pci_setup(void *blob, bd_t *bd)
ft_pci_setup (void *blob, bd_t *bd)
{
u32 *p;
int len;
p = (u32 *)ft_get_prop(blob, "/" OF_TSI "/pci@1000/bus-range", &len);
p = (u32 *)ft_get_prop (blob, "/" OF_TSI "/pci@1000/bus-range", &len);
if (p != NULL) {
p[0] = local_hose.first_busno;
p[1] = local_hose.last_busno;

36
include/configs/mpc7448hpc2.h
View File

@ -24,12 +24,11 @@
* MA 02111-1307 USA
*/
/****************************************************************
*
/*
* board specific configuration options for Freescale
* MPC7448HPC2 (High-Performance Computing II) (Taiga) board
*
****************************************************************/
*/
#ifndef __CONFIG_H
#define __CONFIG_H
@ -99,8 +98,8 @@
* for your console driver.
*
* what to do:
* If you have hacked a serial cable onto the second DUART channel, change the CFG_DUART port from 1
* to 0 below.
* If you have hacked a serial cable onto the second DUART channel,
* change the CFG_DUART port from 1 to 0 below.
*
*/
@ -118,7 +117,8 @@
#define CONFIG_ZERO_BOOTDELAY_CHECK
#undef CONFIG_BOOTARGS
/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
/* #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\"
* to mount root filesystem over NFS;echo" */
#if (CONFIG_BOOTDELAY >= 0)
#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
@ -199,7 +199,7 @@
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)/* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
@ -211,8 +211,8 @@
* CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
* Environment variable 'test_dram_data' must be
* set to 'y'.
* CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word is uniquely
* addressable. Environment variable
* CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word
* is uniquely addressable. Environment variable
* 'test_dram_address' must be set to 'y'.
* CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
* This test takes about 6 minutes to test 64 MB.
@ -246,12 +246,12 @@
* When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
* To an unused memory region. The stack will remain in cache until RAM
* is initialized
*/
*/
#undef CFG_INIT_RAM_LOCK
#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */
#define CFG_INIT_RAM_END 0x4000 /* larger space - we have SDRAM initialized */
#define CFG_INIT_RAM_END 0x4000/* larger space - we have SDRAM initialized */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
#define CFG_GBL_DATA_SIZE 128/* size in bytes reserved for init data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/*-----------------------------------------------------------------------
@ -286,9 +286,9 @@
/* Peripheral Device section */
/*******************************************************
/*
* Resources on the Tsi108
*******************************************************/
*/
#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */
#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
@ -297,9 +297,9 @@
#undef DISABLE_PBM
/*-----------------------------------------------------------------------
/*
* PCI stuff
*-----------------------------------------------------------------------
*
*/
#define CONFIG_PCI /* include pci support */
@ -321,7 +321,7 @@
/* PCI Memory Space */
#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS)
#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) //CFG_PCI_MEM32_BASE = 0xE0000000
#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) /* 0xE0000000 */
#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */
/* PCI I/O Space */
@ -398,7 +398,7 @@
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */
#define CFG_MAX_FLASH_BANKS 1/* Flash can be at one of two addresses */
#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}

4
include/tsi108.h
View File

@ -205,8 +205,8 @@
/* I2C_TX_DATA : Unused/Reserved bits Definition */
#define I2C_TX_DATA_RESERVED (0x00000000)
#define TSI108_I2C_OFFSET 0x7000 /* register block offset for general use I2C channel */
#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* register block offset for SPD I2C channel */
#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */
#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */
#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */