sysmo-bts
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u-boot
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Clean up the code according to codestyle: 

(1) remove some C++ comments.
(2) remove trailing white space.
(3) remove trailing empty line.
(4) Indentation by table.
(5) remove {} in one line condition.
(6) add space before '(' in function call.
Remove some weird printf () output.
Add necessary comments.
Modified Makefile to support building in a separate directory.
This commit is contained in:
roy zang 2006-12-01 11:47:36 +08:00 committed by Zang Tiefei
parent 6bd87c0aee
commit ee311214e0
13 changed files with 1687 additions and 1734 deletions
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2
Makefile
View File

@ -1722,7 +1722,7 @@ EVB64260_750CX_config: unconfig
@$(MKCONFIG) EVB64260 ppc 74xx_7xx evb64260
mpc7448hpc2_config: unconfig
@./mkconfig $(@:_config=) ppc 74xx_7xx mpc7448hpc2
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx mpc7448hpc2
P3G4_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc 74xx_7xx evb64260

20
board/mpc7448hpc2/Makefile
View File

@ -23,26 +23,30 @@
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
LIB = $(obj)lib$(BOARD).a
OBJS = $(BOARD).o tsi108_init.o
COBJS := $(BOARD).o tsi108_init.o
SOBJS := asm_init.o
SOBJS = asm_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
clean:
rm -f $(SOBJS) $(OBJS)
.PHONY: distclean
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude .depend
sinclude ($obj).depend
#########################################################################

1121
board/mpc7448hpc2/asm_init.S
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File diff suppressed because it is too large Load Diff

150
board/mpc7448hpc2/mpc7448hpc2.c
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@ -33,39 +33,38 @@
#include <74xx_7xx.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
extern void ft_cpu_setup(void *blob, bd_t *bd);
extern void ft_cpu_setup (void *blob, bd_t *bd);
#endif
#undef DEBUG
extern void flush_data_cache(void);
extern void invalidate_l1_instruction_cache(void);
extern void tsi108_init_f(void);
extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
extern void tsi108_init_f (void);
int display_mem_map(void);
int display_mem_map (void);
void after_reloc(ulong dest_addr)
void after_reloc (ulong dest_addr)
{
DECLARE_GLOBAL_DATA_PTR;
/*
* Jump to the main U-Boot board init code
*/
board_init_r((gd_t *) gd, dest_addr);
board_init_r ((gd_t *) gd, dest_addr);
/* NOTREACHED */
}
/*
* Check Board Identity:
*
* report board type
*/
int checkboard(void)
int checkboard (void)
{
int l_type = 0;
printf("BOARD: %s\n", CFG_BOARD_NAME);
printf ("BOARD: %s\n", CFG_BOARD_NAME);
return (l_type);
}
@ -75,19 +74,19 @@ int checkboard(void)
* report calling processor number
*/
int read_pid(void)
int read_pid (void)
{
return 0; /* we are on single CPU platform for a while */
}
long int dram_size(int board_type)
long int dram_size (int board_type)
{
return 0x20000000; /* 256M bytes */
}
long int initdram(int board_type)
long int initdram (int board_type)
{
return dram_size(board_type);
return dram_size (board_type);
}
/* DRAM check routines copied from gw8260 */
@ -114,11 +113,11 @@ long int initdram(int board_type)
/* May cloober fr0. */
/* */
/*********************************************************************/
static void move64(unsigned long long *src, unsigned long long *dest)
static void move64 (unsigned long long *src, unsigned long long *dest)
{
asm("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
"stfd 0, 0(4)" /* *dest = fpr0 */
: : :"fr0"); /* Clobbers fr0 */
asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
"stfd 0, 0(4)" /* *dest = fpr0 */
: : :"fr0"); /* Clobbers fr0 */
return;
}
@ -183,28 +182,28 @@ unsigned long long pattern[] = {
/* Assumes only one one SDRAM bank */
/* */
/*********************************************************************/
int mem_test_data(void)
int mem_test_data (void)
{
unsigned long long *pmem = (unsigned long long *)CFG_MEMTEST_START;
unsigned long long temp64;
int num_patterns = sizeof(pattern) / sizeof(pattern[0]);
int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
int i;
unsigned int hi, lo;
for (i = 0; i < num_patterns; i++) {
move64(&(pattern[i]), pmem);
move64(pmem, &temp64);
move64 (&(pattern[i]), pmem);
move64 (pmem, &temp64);
/* hi = (temp64>>32) & 0xffffffff; */
/* lo = temp64 & 0xffffffff; */
/* printf("\ntemp64 = 0x%08x%08x", hi, lo); */
/* hi = (temp64>>32) & 0xffffffff; */
/* lo = temp64 & 0xffffffff; */
/* printf ("\ntemp64 = 0x%08x%08x", hi, lo); */
hi = (pattern[i] >> 32) & 0xffffffff;
lo = pattern[i] & 0xffffffff;
/* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
/* printf ("\npattern[%d] = 0x%08x%08x", i, hi, lo); */
if (temp64 != pattern[i]) {
printf("\n Data Test Failed, pattern 0x%08x%08x",
printf ("\n Data Test Failed, pattern 0x%08x%08x",
hi, lo);
return 1;
}
@ -236,7 +235,7 @@ int mem_test_data(void)
/* */
/* */
/*********************************************************************/
int mem_test_address(void)
int mem_test_address (void)
{
volatile unsigned int *pmem =
(volatile unsigned int *)CFG_MEMTEST_START;
@ -251,13 +250,13 @@ int mem_test_address(void)
/* verify each loaction */
for (i = 0; i < size; i++) {
if (pmem[i] != i) {
printf("\n Address Test Failed at 0x%x", i);
printf ("\n Address Test Failed at 0x%x", i);
return 1;
}
}
return 0;
}
#endif /* CFG_DRAM_TEST_ADDRESS */
#endif /* CFG_DRAM_TEST_ADDRESS */
#if defined (CFG_DRAM_TEST_WALK)
/*********************************************************************/
@ -287,7 +286,7 @@ int mem_test_address(void)
/* */
/* */
/*********************************************************************/
int mem_march(volatile unsigned long long *base,
int mem_march (volatile unsigned long long *base,
unsigned int size,
unsigned long long rmask,
unsigned long long wmask, short read, short write)
@ -299,14 +298,14 @@ int mem_march(volatile unsigned long long *base,
for (i = 0; i < size; i++) {
if (read != 0) {
/* temp = base[i]; */
move64((unsigned long long *)&(base[i]), &temp);
move64 ((unsigned long long *)&(base[i]), &temp);
if (rmask != temp) {
hitemp = (temp >> 32) & 0xffffffff;
lotemp = temp & 0xffffffff;
himask = (rmask >> 32) & 0xffffffff;
lomask = rmask & 0xffffffff;
printf("\n Walking one's test failed: \
printf ("\n Walking one's test failed: \
address = 0x%08x," "\n\texpected \
0x%08x%08x, found 0x%08x%08x", i << 3,\
himask, lomask, hitemp, lotemp);
@ -315,12 +314,12 @@ int mem_march(volatile unsigned long long *base,
}
if (write != 0) {
/* base[i] = wmask; */
move64(&wmask, (unsigned long long *)&(base[i]));
move64 (&wmask, (unsigned long long *)&(base[i]));
}
}
return 0;
}
#endif /* CFG_DRAM_TEST_WALK */
#endif /* CFG_DRAM_TEST_WALK */
/*********************************************************************/
/* NAME: mem_test_walk() - a simple walking ones test */
@ -348,7 +347,7 @@ int mem_march(volatile unsigned long long *base,
/* */
/* */
/*********************************************************************/
int mem_test_walk(void)
int mem_test_walk (void)
{
unsigned long long mask;
volatile unsigned long long *pmem =
@ -359,32 +358,31 @@ int mem_test_walk(void)
mask = 0x01;
printf("Initial Pass");
mem_march(pmem, size, 0x0, 0x1, 0, 1);
printf ("Initial Pass");
mem_march (pmem, size, 0x0, 0x1, 0, 1);
printf("\b\b\b\b\b\b\b\b\b\b\b\b");
printf(" ");
printf(" ");
printf("\b\b\b\b\b\b\b\b\b\b\b\b");
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
printf (" ");
printf (" ");
printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
for (i = 0; i < 63; i++) {
printf("Pass %2d", i + 2);
if (mem_march(pmem, size, mask, mask << 1, 1, 1) != 0) {
/*printf("mask: 0x%x, pass: %d, ", mask, i); */
printf ("Pass %2d", i + 2);
if (mem_march(pmem, size, mask, mask << 1, 1, 1) != 0)
/*printf ("mask: 0x%x, pass: %d, ", mask, i); */
return 1;
}
mask = mask << 1;
printf("\b\b\b\b\b\b\b");
printf ("\b\b\b\b\b\b\b");
}
printf("Last Pass");
printf ("Last Pass");
if (mem_march(pmem, size, 0, mask, 0, 1) != 0) {
/* printf("mask: 0x%x", mask); */
/* printf ("mask: 0x%x", mask); */
return 1;
}
printf("\b\b\b\b\b\b\b\b\b");
printf(" ");
printf("\b\b\b\b\b\b\b\b\b");
printf ("\b\b\b\b\b\b\b\b\b");
printf (" ");
printf ("\b\b\b\b\b\b\b\b\b");
return 0;
}
@ -412,60 +410,58 @@ int mem_test_walk(void)
/* */
/* */
/*********************************************************************/
int testdram(void)
int testdram (void)
{
char *s;
int rundata, runaddress, runwalk;
s = getenv("testdramdata");
s = getenv ("testdramdata");
rundata = (s && (*s == 'y')) ? 1 : 0;
s = getenv("testdramaddress");
s = getenv ("testdramaddress");
runaddress = (s && (*s == 'y')) ? 1 : 0;
s = getenv("testdramwalk");
s = getenv ("testdramwalk");
runwalk = (s && (*s == 'y')) ? 1 : 0;
/* rundata = 1; */
/* runaddress = 0; */
/* runwalk = 0; */
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf("Testing RAM from 0x%08x to 0x%08x ... \
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
printf ("Testing RAM from 0x%08x to 0x%08x ... \
(don't panic... that will take a moment !!!!)\n", \
CFG_MEMTEST_START, CFG_MEMTEST_END);
}
#ifdef CFG_DRAM_TEST_DATA
if (rundata == 1) {
printf("Test DATA ... ");
printf ("Test DATA ... ");
if (mem_test_data () == 1) {
printf("failed \n");
printf ("failed \n");
return 1;
} else
printf("ok \n");
printf ("ok \n");
}
#endif
#ifdef CFG_DRAM_TEST_ADDRESS
if (runaddress == 1) {
printf("Test ADDRESS ... ");
printf ("Test ADDRESS ... ");
if (mem_test_address () == 1) {
printf("failed \n");
printf ("failed \n");
return 1;
} else
printf("ok \n");
printf ("ok \n");
}
#endif
#ifdef CFG_DRAM_TEST_WALK
if (runwalk == 1) {
printf("Test WALKING ONEs ... ");
if (mem_test_walk() == 1) {
printf("failed \n");
printf ("Test WALKING ONEs ... ");
if (mem_test_walk () == 1) {
printf ("failed \n");
return 1;
} else
printf("ok \n");
printf ("ok \n");
}
#endif
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
printf("passed\n");
}
if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
printf ("passed\n");
return 0;
}
@ -473,17 +469,17 @@ int testdram(void)
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
ft_board_setup(void *blob, bd_t *bd)
ft_board_setup (void *blob, bd_t *bd)
{
u32 *p;
int len;
ft_cpu_setup(blob, bd);
ft_cpu_setup (blob, bd);
p = ft_get_prop(blob, "/memory/reg", &len);
p = ft_get_prop (blob, "/memory/reg", &len);
if (p != NULL) {
*p++ = cpu_to_be32(bd->bi_memstart);
*p = cpu_to_be32(bd->bi_memsize);
*p++ = cpu_to_be32 (bd->bi_memstart);
*p = cpu_to_be32 (bd->bi_memsize);
}
}
#endif

369
board/mpc7448hpc2/tsi108_init.c
View File

@ -33,7 +33,7 @@
#include <asm/processor.h>
#include <tsi108.h>
extern void mpicInit(int verbose);
extern void mpicInit (int verbose);
/*
* Configuration Options
@ -118,11 +118,11 @@ static PLL_CTRL_SET pll0_config[8] = {
static int pb_clk_sel[8] = { 0, 0, 183, 100, 133, 167, 200, 233 };
/*
* get_board_bus_clk()
* get_board_bus_clk ()
*
* returns the bus clock in Hz.
*/
unsigned long get_board_bus_clk(void)
unsigned long get_board_bus_clk (void)
{
ulong i;
@ -134,37 +134,38 @@ unsigned long get_board_bus_clk(void)
}
/*
* board_early_init_f()
* board_early_init_f ()
*
* board-specific initialization executed from flash
*/
int board_early_init_f(void)
int board_early_init_f (void)
{
DECLARE_GLOBAL_DATA_PTR;
ulong i;
gd->mem_clk = 0;
i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
i = (i >> 20) & 0x07;
i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
CG_PWRUP_STATUS);
i = (i >> 20) & 0x07; /* value of SW4[4:7] */
switch (i) {
case 0:
printf("Using external clock\n");
case 0: /* external clock */
printf ("Using external clock\n");
break;
case 1:
case 1: /* system clock */
gd->mem_clk = gd->bus_clk;
break;
case 4:
case 5:
case 6:
case 4: /* 133 MHz */
case 5: /* 166 MHz */
case 6: /* 200 MHz */
gd->mem_clk = pb_clk_sel[i] * 1000000;
break;
default:
printf("Invalid DDR2 clock setting\n");
printf ("Invalid DDR2 clock setting\n");
return -1;
}
printf("BUS! %d MHz\n", get_board_bus_clk() / 1000000);
printf("MEM! %d MHz\n", gd->mem_clk / 1000000);
printf ("BUS: %d MHz\n", get_board_bus_clk() / 1000000);
printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
return 0;
}
@ -173,35 +174,35 @@ int board_early_init_f(void)
* relocation. Contains code that cannot be executed from flash.
*/
int board_early_init_r(void)
int board_early_init_r (void)
{
ulong temp, i;
ulong reg_val;
volatile ulong *reg_ptr;
reg_ptr =
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
for (i = 0; i < 32; i++) {
*reg_ptr++ = 0x00000201; /* SWAP ENABLED */
*reg_ptr++ = 0x00;
}
__asm__ __volatile__("eieio");
__asm__ __volatile__("sync");
__asm__ __volatile__ ("eieio");
__asm__ __volatile__ ("sync");
/* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
0x80000001);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
0x80000001);
__asm__ __volatile__ ("sync");
/* Make sure that OCN_BAR2 decoder is set (to allow following immediate
* read from SDRAM)
*/
temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/*
* Remap PB_OCN_BAR1 to accomodate PCI-bus aperture and EPROM into the
@ -219,101 +220,101 @@ int board_early_init_r(void)
* initialize pointer to LUT associated with PB_OCN_BAR1
*/
reg_ptr =
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
for (i = 0; i < 32; i++) {
*reg_ptr++ = pb2ocn_lut1[i].lower;
*reg_ptr++ = pb2ocn_lut1[i].upper;
}
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/* Base addresses for Cs0, CS1, CS2, CS3 */
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
0x00000000);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
0x00000000);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
0x00100000);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
0x00100000);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
0x00200000);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
0x00200000);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
0x00300000);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
0x00300000);
__asm__ __volatile__ ("sync");
/* Masks for HLP banks */
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
0xFFF00000);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
0xFFF00000);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
0xFFF00000);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
0xFFF00000);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
0xFFF00000);
__asm__ __volatile__ ("sync");
/* Set CTRL0 values for banks */
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
0x7FFC44C2);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
0x7FFC44C2);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
0x7FFC44C0);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
0x7FFC44C0);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
0x7FFC44C0);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
0x7FFC44C0);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
0x7FFC44C2);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
0x7FFC44C2);
__asm__ __volatile__ ("sync");
/* Set banks to latched mode, enabled, and other default settings */
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
0x7C0F2000);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
0x7C0F2000);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
0x7C0F2000);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
0x7C0F2000);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
0x7C0F2000);
__asm__ __volatile__ ("sync");
/*
* Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
* value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
*/
out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
0xE0000011);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
0xE0000011);
__asm__ __volatile__ ("sync");
/* Make sure that OCN_BAR2 decoder is set (to allow following
* immediate read from SDRAM)
*/
temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
__asm__ __volatile__("sync");
__asm__ __volatile__ ("sync");
/*
* SRI: At this point we have enabled the HLP banks. That means we can
@ -327,7 +328,7 @@ int board_early_init_r(void)
* Taiga Rev. 2.
*/
env_init();
env_init ();
#ifndef DISABLE_PBM
@ -336,12 +337,11 @@ int board_early_init_r(void)
* by PBM that are different from ones set after reset.
*/
temp = get_cpu_type();
temp = get_cpu_type ();
if ((CPU_750FX == temp) || (CPU_750GX == temp)) {
out32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
0x00009955);
}
if ((CPU_750FX == temp) || (CPU_750GX == temp))
out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
0x00009955);
#endif /* DISABLE_PBM */
#ifdef CONFIG_PCI
@ -350,37 +350,37 @@ int board_early_init_r(void)
*/
/* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0_UPPER,
0);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
PCI_PFAB_BAR0_UPPER, 0);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
0xFB000001);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
0xFB000001);
__asm__ __volatile__ ("sync");
/* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
temp =
in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
temp = in32(CFG_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
temp &= ~0xFF00; /* Clear the BUS_NUM field */
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
temp);
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
temp);
/* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
0);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
0);
__asm__ __volatile__ ("sync");
/* This register is on the PCI side to interpret the address it receives
* and maps it as a IO address.
*/
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
0xFA000001);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
0xFA000001);
__asm__ __volatile__ ("sync");
/*
* Map PCI/X Memory Space
@ -404,7 +404,7 @@ int board_early_init_r(void)
*/
reg_ptr =
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
#ifdef DISABLE_PBM
@ -438,22 +438,22 @@ int board_early_init_r(void)
reg_val = 0x00007100;
#endif
__asm__ __volatile__("eieio");
__asm__ __volatile__("sync");
__asm__ __volatile__ ("eieio");
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
reg_val);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
reg_val);
__asm__ __volatile__ ("sync");
/* Set 64-bit PCI bus address for system memory
* ( 0 is the best choice for easy mapping)
*/
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
0x00000000);
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
0x00000000);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
0x00000000);
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
0x00000000);
__asm__ __volatile__ ("sync");
#ifndef DISABLE_PBM
/*
@ -469,7 +469,7 @@ int board_early_init_r(void)
* set pointer to LUT associated with PCI P2O_BAR3
*/
reg_ptr =
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
reg_val = 0x00000004; /* Destination port = SDC */
@ -483,45 +483,45 @@ int board_early_init_r(void)
reg_val += 0x01000000;
}
__asm__ __volatile__("eieio");
__asm__ __volatile__("sync");
__asm__ __volatile__ ("eieio");
__asm__ __volatile__ ("sync");
/* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
reg_val =
in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
PCI_P2O_PAGE_SIZES);
reg_val &= ~0x00FF;
reg_val |= 0x0071;
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
reg_val);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
reg_val);
__asm__ __volatile__ ("sync");
/* Set 64-bit base PCI bus address for window (0x20000000) */
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
0x00000000);
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
0x20000000);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
0x00000000);
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
0x20000000);
__asm__ __volatile__ ("sync");
#endif /* !DISABLE_PBM */
#ifdef ENABLE_PCI_CSR_BAR
/* open if required access to Tsi108 CSRs from the PCI/X bus */
/* enable BAR0 on the PCI/X bus */
reg_val =
in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
reg_val = in32(CFG_TSI108_CSR_BASE +
TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
reg_val |= 0x02;
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
reg_val);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
reg_val);
__asm__ __volatile__ ("sync");
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
0x00000000);
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
CFG_TSI108_CSR_BASE);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
0x00000000);
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
CFG_TSI108_CSR_BASE);
__asm__ __volatile__ ("sync");
#endif
@ -531,32 +531,32 @@ int board_early_init_r(void)
reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
reg_val |= 0x06;
out32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
__asm__ __volatile__ ("sync");
#endif /* CONFIG_PCI */
/*
* Initialize MPIC outputs (interrupt pins):
* Interrupt routing on the Grendel Emul. Board:
* PB_INT[0] -> INT (CPU0)
* PB_INT[1] -> INT (CPU1)
* PB_INT[2] -> MCP (CPU0)
* PB_INT[3] -> MCP (CPU1)
* PB_INT[0] -> INT (CPU0)
* PB_INT[1] -> INT (CPU1)
* PB_INT[2] -> MCP (CPU0)
* PB_INT[3] -> MCP (CPU1)
* Set interrupt controller outputs as Level_Sensitive/Active_Low
*/
out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
out32(CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
__asm__ __volatile__("sync");
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
__asm__ __volatile__ ("sync");
/*
* Ensure that Machine Check exception is enabled
* We need it to support PCI Bus probing (configuration reads)
*/
reg_val = mfmsr();
reg_val = mfmsr ();
mtmsr(reg_val | MSR_ME);
return 0;
@ -567,7 +567,7 @@ int board_early_init_r(void)
* used in the misc_init_r function
*/
unsigned long get_l2cr(void)
unsigned long get_l2cr (void)
{
unsigned long l2controlreg;
asm volatile ("mfspr %0, 1017":"=r" (l2controlreg):);
@ -581,46 +581,49 @@ unsigned long get_l2cr(void)
*
*/
int misc_init_r(void)
int misc_init_r (void)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef CFG_CLK_SPREAD /* Initialize Spread-Spectrum Clock generation */
ulong i;
/* Ensure that Spread-Spectrum is disabled */
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
/* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
* Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
*/
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x002e0044); /* D = 0.25% */
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1, 0x00000039); /* BWADJ */
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
0x002e0044); /* D = 0.25% */
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
0x00000039); /* BWADJ */
/* Initialize PLL0: CG_PB_CLKO */
/* Detect PB clock freq. */
i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
i = (i >> 16) & 0x07; /* Get PB PLL multiplier */
out32(CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
out32(CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
out32 (CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
out32 (CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
/* Wait and set SSEN for both PLL0 and 1 */
udelay(1000);
out32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0x802e0044); /* D=0.25% */
out32(CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
0x80000000 | pll0_config[i].ctrl0);
udelay (1000);
out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
0x802e0044); /* D=0.25% */
out32 (CFG_TSI108_CSR_BASE +
TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
0x80000000 | pll0_config[i].ctrl0);
#endif /* CFG_CLK_SPREAD */
#ifdef CFG_L2
l2cache_enable();
l2cache_enable ();
#endif
printf("BUS: %d MHz\n", gd->bus_clk / 1000000);
printf("MEM: %d MHz\n", gd->mem_clk / 1000000);
printf ("BUS: %d MHz\n", gd->bus_clk / 1000000);
printf ("MEM: %d MHz\n", gd->mem_clk / 1000000);
/*
* All the information needed to print the cache details is avaiblable
@ -629,31 +632,31 @@ int misc_init_r(void)
* So this seems like a good place to print all this information
*/
printf("CACHE: ");
printf ("CACHE: ");
switch (get_cpu_type()) {
case CPU_7447A:
printf("L1 Instruction cache - 32KB 8-way");
(get_hid0() & (1 << 15)) ? printf(" ENABLED\n") :
printf(" DISABLED\n");
printf(" L1 Data cache - 32KB 8-way");
(get_hid0() & (1 << 14)) ? printf(" ENABLED\n") :
printf(" DISABLED\n");
printf(" Unified L2 cache - 512KB 8-way");
(get_l2cr() & (1 << 31)) ? printf(" ENABLED\n") :
printf(" DISABLED\n");
printf("\n");
printf ("L1 Instruction cache - 32KB 8-way");
(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("L1 Data cache - 32KB 8-way");
(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("Unified L2 cache - 512KB 8-way");
(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("\n");
break;
case CPU_7448:
printf("L1 Instruction cache - 32KB 8-way");
(get_hid0() & (1 << 15)) ? printf(" ENABLED\n") :
printf(" DISABLED\n");
printf(" L1 Data cache - 32KB 8-way");
(get_hid0() & (1 << 14)) ? printf(" ENABLED\n") :
printf(" DISABLED\n");
printf(" Unified L2 cache - 1MB 8-way");
(get_l2cr() & (1 << 31)) ? printf(" ENABLED\n") :
printf(" DISABLED\n");
printf ("L1 Instruction cache - 32KB 8-way");
(get_hid0 () & (1 << 15)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("L1 Data cache - 32KB 8-way");
(get_hid0 () & (1 << 14)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
printf ("Unified L2 cache - 1MB 8-way");
(get_l2cr () & (1 << 31)) ? printf (" ENABLED\n") :
printf (" DISABLED\n");
break;
default:
break;

14
cpu/74xx_7xx/cpu.c
View File

@ -303,7 +303,7 @@ watchdog_reset(void)
#ifdef CONFIG_OF_FLAT_TREE
void
ft_cpu_setup(void *blob, bd_t *bd)
ft_cpu_setup (void *blob, bd_t *bd)
{
u32 *p;
ulong clock;
@ -311,18 +311,18 @@ ft_cpu_setup(void *blob, bd_t *bd)
clock = bd->bi_busfreq;
p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
p = ft_get_prop (blob, "/cpus/" OF_CPU "/bus-frequency", &len);
if (p != NULL)
*p = cpu_to_be32(clock);
*p = cpu_to_be32 (clock);
#if defined(CONFIG_TSI108_ETH)
p = ft_get_prop(blob, "/" OF_TSI "/ethernet@6200/address", &len);
memcpy(p, bd->bi_enetaddr, 6);
p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6200/address", &len);
memcpy (p, bd->bi_enetaddr, 6);
#endif
#if defined(CONFIG_HAS_ETH1)
p = ft_get_prop(blob, "/" OF_TSI "/ethernet@6600/address", &len);
memcpy(p, bd->bi_enet1addr, 6);
p = ft_get_prop (blob, "/" OF_TSI "/ethernet@6600/address", &len);
memcpy (p, bd->bi_enet1addr, 6);
#endif
}
#endif

82
cpu/74xx_7xx/speed.c
View File

@ -31,7 +31,7 @@
DECLARE_GLOBAL_DATA_PTR;
extern unsigned long get_board_bus_clk(void);
extern unsigned long get_board_bus_clk (void);
static const int hid1_multipliers_x_10[] = {
25, /* 0000 - 2.5x */
@ -53,38 +53,38 @@ static const int hid1_multipliers_x_10[] = {
};
static const int hid1_7447A_multipliers_x_10[] = {
115, /* 00000 - 11.5x */
170, /* 00001 - 17x */
75, /* 00010 - 7.5x */
150, /* 00011 - 15x */
70, /* 00100 - 7x */
180, /* 00101 - 18x */
10, /* 00110 - bypass */
200, /* 00111 - 20x */
20, /* 01000 - 2x */
210, /* 01001 - 21x */
65, /* 01010 - 6.5x */
130, /* 01011 - 13x */
85, /* 01100 - 8.5x */
240, /* 01101 - 13x */
95, /* 01110 - 9.5x */
90, /* 01111 - 9x */
30, /* 10000 - 3x */
105, /* 10001 - 10.5x */
55, /* 10010 - 5.5x */
110, /* 10011 - 11x */
40, /* 10100 - 4x */
100, /* 10101 - 10x */
50, /* 10110 - 5x */
120, /* 10111 - 12x */
80, /* 11000 - 8x */
140, /* 11001 - 14x */
60, /* 11010 - 6x */
160, /* 11011 - 16x */
135, /* 11100 - 13.5x */
280, /* 11101 - 28x */
0, /* 11110 - off */
125 /* 11111 - 12.5x */
115, /* 00000 - 11.5x */
170, /* 00001 - 17x */
75, /* 00010 - 7.5x */
150, /* 00011 - 15x */
70, /* 00100 - 7x */
180, /* 00101 - 18x */
10, /* 00110 - bypass */
200, /* 00111 - 20x */
20, /* 01000 - 2x */
210, /* 01001 - 21x */
65, /* 01010 - 6.5x */
130, /* 01011 - 13x */
85, /* 01100 - 8.5x */
240, /* 01101 - 13x */
95, /* 01110 - 9.5x */
90, /* 01111 - 9x */
30, /* 10000 - 3x */
105, /* 10001 - 10.5x */
55, /* 10010 - 5.5x */
110, /* 10011 - 11x */
40, /* 10100 - 4x */
100, /* 10101 - 10x */
50, /* 10110 - 5x */
120, /* 10111 - 12x */
80, /* 11000 - 8x */
140, /* 11001 - 14x */
60, /* 11010 - 6x */
160, /* 11011 - 16x */
135, /* 11100 - 13.5x */
280, /* 11101 - 28x */
0, /* 11110 - off */
125 /* 11111 - 12.5x */
};
static const int hid1_fx_multipliers_x_10[] = {
@ -127,16 +127,17 @@ int get_clocks (void)
ulong clock = 0;
#ifdef CFG_CONFIG_BUS_CLK
gd->bus_clk = get_board_bus_clk();
gd->bus_clk = get_board_bus_clk (); /* bus clock is configurable */
#else
gd->bus_clk = CFG_BUS_CLK;
gd->bus_clk = CFG_BUS_CLK; /* bus clock is a fixed frequency */
#endif
/* calculate the clock frequency based upon the CPU type */
switch (get_cpu_type()) {
case CPU_7447A:
case CPU_7448:
clock = (gd->bus_clk / 10) * hid1_7447A_multipliers_x_10[(get_hid1 () >> 12) & 0x1F];
clock = (gd->bus_clk / 10) *
hid1_7447A_multipliers_x_10[(get_hid1 () >> 12) & 0x1F];
break;
case CPU_7455:
@ -146,12 +147,14 @@ int get_clocks (void)
* Make sure division is done before multiplication to prevent 32-bit
* arithmetic overflows which will cause a negative number
*/
clock = (gd->bus_clk / 10) * hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF];
clock = (gd->bus_clk / 10) *
hid1_multipliers_x_10[(get_hid1 () >> 13) & 0xF];
break;
case CPU_750GX:
case CPU_750FX:
clock = gd->bus_clk * hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
clock = gd->bus_clk *
hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
break;
case CPU_7450:
@ -168,7 +171,8 @@ int get_clocks (void)
* Make sure division is done before multiplication to prevent 32-bit
* arithmetic overflows which will cause a negative number
*/
clock = (gd->bus_clk / 10) * hid1_multipliers_x_10[get_hid1 () >> 28];
clock = (gd->bus_clk / 10) *
hid1_multipliers_x_10[get_hid1 () >> 28];
break;
case CPU_UNKNOWN:

186
doc/README.mpc7448hpc2
View File

@ -14,12 +14,12 @@ chassis.
Building U-Boot
------------------
The mpc7448hpc2 code base is known to compile using:
Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
Binutils 2.15, Gcc 3.4.3, Glibc 2.3.3
$ make mpc7448hpc2_config
Configuring for mpc7448hpc2 board...
$ make mpc7448hpc2_config
Configuring for mpc7448hpc2 board...
$ make
$ make
Memory Map
----------
@ -28,17 +28,16 @@ The memory map is setup for Linux to operate properly.
The mapping is:
Range Start Range End Definition Size
0x0000_0000 0x7fff_ffff DDR 2G
0xe000_0000 0xe7ff_ffff PCI Memory 128M
0xfa00_0000 0xfaff_ffff PCI IO 16M
0xfb00_0000 0xfbff_ffff PCI Config 16M
0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M
0xfe00_0000 0xfeff_ffff PromJet 16M
0xff00_0000 0xff80_0000 FLASH (boot flash) 8M
0xff80_0000 0xffff_ffff FLASH (second half flash) 8M
Range Start Range End Definition Size
0x0000_0000 0x7fff_ffff DDR 2G
0xe000_0000 0xe7ff_ffff PCI Memory 128M
0xfa00_0000 0xfaff_ffff PCI IO 16M
0xfb00_0000 0xfbff_ffff PCI Config 16M
0xfc00_0000 0xfc0f_ffff NVRAM/CADMUS 1M
0xfe00_0000 0xfeff_ffff PromJet 16M
0xff00_0000 0xff80_0000 FLASH (boot flash) 8M
0xff80_0000 0xffff_ffff FLASH (second half flash) 8M
Using Flash
-----------
@ -57,137 +56,130 @@ settings for updating flash are given below.
The u-boot commands for copying the boot-bank into the secondary bank are
as follows:
erase ff800000 ff880000
cp.b ff000000 ff800000 80000
erase ff800000 ff880000
cp.b ff000000 ff800000 80000
U-boot commands for downloading an image via tftp and flashing
it into the secondary bank:
tftp 10000 <u-boot.bin.image>
erase ff000000 ff080000
cp.b 10000 ff000000 80000
tftp 10000 <u-boot.bin.image>
erase ff000000 ff080000
cp.b 10000 ff000000 80000
After copying the image into the second bank of flash, be sure to toggle
SW3[4] on board before resetting the board in order to set the
secondary bank as the boot-bank.
Board Switches
----------------------
Most switches on the board should not be changed. The most frequent
user-settable switches on the board are used to configure
the flash banks and determining the PCI frequency.
SW1[1-5]: Processor core voltage
12345 Core Voltage
-----
SW1=01111 1.000V.
SW1=01101 1.100V.
SW1=01011 1.200V.
SW1=01001 1.300V only for MPC7447A.
12345 Core Voltage
-----
SW1=01111 1.000V.
SW1=01101 1.100V.
SW1=01011 1.200V.
SW1=01001 1.300V only for MPC7447A.
SW2[1-6]: CPU core frequency
CPU Core Frequency (MHz)
CPU Core Frequency (MHz)
Bus Frequency
123456 100 133 167 200 Ratio
123456 100 133 167 200 Ratio
------
SW2=101100 500 667 833 1000 5x
SW2=100100 550 733 917 1100 5.5x
SW2=110100 600 800 1000 1200 6x
SW2=010100 650 866 1083 1300 6.5x
SW2=001000 700 930 1167 1400 7x
SW2=000100 750 1000 1250 1500 7.5x
SW2=110000 800 1066 1333 1600 8x
SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A
SW2=011110 900 1200 1500 1800 9x
------
SW2=101100 500 667 833 1000 5x
SW2=100100 550 733 917 1100 5.5x
SW2=110100 600 800 1000 1200 6x
SW2=010100 650 866 1083 1300 6.5x
SW2=001000 700 930 1167 1400 7x
SW2=000100 750 1000 1250 1500 7.5x
SW2=110000 800 1066 1333 1600 8x
SW2=011000 850 1333 1417 1700 8.5x only for MPC7447A
SW2=011110 900 1200 1500 1800 9x
This table shows only a subset of available frequency options; see the CPU
hardware specifications for more information.
SW2[7-8]: Bus Protocol and CPU Reset Option
7
-
SW2=0 System bus uses MPX bus protocol
SW2=1 System bus uses 60x bus protocol
8
-
SW2=0 TSI108 can cause CPU reset
SW2=1 TSI108 can not cause CPU reset
7
-
SW2=0 System bus uses MPX bus protocol
SW2=1 System bus uses 60x bus protocol
8
-
SW2=0 TSI108 can cause CPU reset
SW2=1 TSI108 can not cause CPU reset
SW3[1-8] system options
123
---
SW3=xxx Connected to GPIO[0:2] on TSI108
123
---
SW3=xxx Connected to GPIO[0:2] on TSI108
4
-
SW3=0 CPU boots from low half of flash
SW3=1 CPU boots from high half of flash
4
-
SW3=0 CPU boots from low half of flash
SW3=1 CPU boots from high half of flash
5
-
SW3=0 SATA and slot2 connected to PCI bus
SW3=1 Only slot1 connected to PCI bus
5
-
SW3=0 SATA and slot2 connected to PCI bus
SW3=1 Only slot1 connected to PCI bus
6
-
SW3=0 USB connected to PCI bus
SW3=1 USB disconnected from PCI bus
6
-
SW3=0 USB connected to PCI bus
SW3=1 USB disconnected from PCI bus
7
-
SW3=0 Flash is write protected
SW3=1 Flash is NOT write protected
7
-
SW3=0 Flash is write protected
SW3=1 Flash is NOT write protected
8
-
SW3=0 CPU will boot from flash
SW3=1 CPU will boot from PromJet
8
-
SW3=0 CPU will boot from flash
SW3=1 CPU will boot from PromJet
SW4[1-3]: System bus frequency
Bus Frequency (MHz)
---
SW4=010 183
SW4=011 100
SW4=100 133
SW4=101 166 only for MPC7447A
SW4=110 200 only for MPC7448
others reserved
---
SW4=010 183
SW4=011 100
SW4=100 133
SW4=101 166 only for MPC7447A
SW4=110 200 only for MPC7448
others reserved
SW4[4-6]: DDR2 SDRAM frequency
Bus Frequency (MHz)
---
SW4=000 external clock
SW4=011 system clock
SW4=100 133
SW4=101 166
SW4=110 200
others reserved
---
SW4=000 external clock
SW4=011 system clock
SW4=100 133
SW4=101 166
SW4=110 200
others reserved
SW4[7-8]: PCI/PCI-X frequency control
7
-
SW4=0 PCI/PCI-X bus operates normally
SW4=1 PCI bus forced to PCI-33 mode
7
-
SW4=0 PCI/PCI-X bus operates normally
SW4=1 PCI bus forced to PCI-33 mode
8
-
SW4=0 PCI-X mode at 133 MHz allowed
SW4=1 PCI-X mode limited to 100 MHz
8
-
SW4=0 PCI-X mode at 133 MHz allowed
SW4=1 PCI-X mode limited to 100 MHz

767
drivers/tsi108_eth.c
View File

File diff suppressed because it is too large Load Diff

50
drivers/tsi108_i2c.c
View File

@ -23,19 +23,18 @@
*/
#include <config.h>
#include <common.h>
#ifdef CONFIG_TSI108_I2C
#include <common.h>
#include <tsi108.h>
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
#define I2C_DELAY 100000
#define I2C_DELAY 100000
#undef DEBUG_I2C
#ifdef DEBUG_I2C
#define DPRINT(x) printf(x)
#define DPRINT(x) printf (x)
#else
#define DPRINT(x)
#endif
@ -43,7 +42,7 @@
/* All functions assume that Tsi108 I2C block is the only master on the bus */
/* I2C read helper function */
static int i2c_read_byte(
static int i2c_read_byte (
uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */
uchar chip_addr,/* I2C device address on the bus */
uint byte_addr, /* Byte address within I2C device */
@ -55,19 +54,17 @@ static int i2c_read_byte(
u32 op_status = TSI108_I2C_TIMEOUT_ERR;
u32 chan_offset = TSI108_I2C_OFFSET;
DPRINT(("I2C read_byte() %d 0x%02x 0x%02x\n",
DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n",
i2c_chan, chip_addr, byte_addr));
if (0 != i2c_chan) {
if (0 != i2c_chan)
chan_offset = TSI108_I2C_SDRAM_OFFSET;
}
/* Check if I2C operation is in progress */
temp = *(u32 *) (CFG_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS |
I2C_CNTRL2_START))
) {
I2C_CNTRL2_START))) {
/* Set device address and operation (read = 0) */
temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) |
((chip_addr >> 3) & 0x0F);
@ -108,7 +105,7 @@ static int i2c_read_byte(
/* report HW error */
op_status = TSI108_I2C_IF_ERROR;
DPRINT(("I2C HW error reported: 0x%02x\n", temp));
DPRINT (("I2C HW error reported: 0x%02x\n", temp));
}
break;
@ -117,10 +114,10 @@ static int i2c_read_byte(
} else {
op_status = TSI108_I2C_IF_BUSY;
DPRINT(("I2C Transaction start failed: 0x%02x\n", temp));
DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
}
DPRINT(("I2C read_byte() status: 0x%02x\n", op_status));
DPRINT (("I2C read_byte() status: 0x%02x\n", op_status));
return op_status;
}
@ -141,7 +138,8 @@ static int i2c_read_byte(
* Returns: 0 on success, not 0 on failure
*/
int i2c_read(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len)
int i2c_read (uchar chip_addr, uint byte_addr, int alen,
uchar * buffer, int len)
{
u32 op_status = TSI108_I2C_PARAM_ERR;
u32 i2c_if = 0;
@ -159,20 +157,20 @@ int i2c_read(uchar chip_addr, uint byte_addr, int alen, uchar * buffer, int len)
buffer++);
if (TSI108_I2C_SUCCESS != op_status) {
DPRINT(("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
break;
}
}
}
DPRINT(("I2C read() status: 0x%02x\n", op_status));
DPRINT (("I2C read() status: 0x%02x\n", op_status));
return op_status;
}
/* I2C write helper function */
static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */
static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */
uint byte_addr, /* Byte address within I2C device */
uchar * buffer /* pointer to data buffer */
)
@ -210,7 +208,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */
/* Wait until operation completed */
do {
// Read I2C operation status
/* Read I2C operation status */
temp =
*(u32 *) (CFG_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
I2C_CNTRL2);
@ -227,7 +225,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */
/* report detected HW error */
op_status = TSI108_I2C_IF_ERROR;
DPRINT(("I2C HW error reported: 0x%02x\n", temp));
DPRINT (("I2C HW error reported: 0x%02x\n", temp));
}
break;
@ -237,7 +235,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */
} else {
op_status = TSI108_I2C_IF_BUSY;
DPRINT(("I2C Transaction start failed: 0x%02x\n", temp));
DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
}
return op_status;
@ -256,7 +254,7 @@ static int i2c_write_byte(uchar chip_addr,/* I2C device address on the bus */
* Returns: 0 on success, not 0 on failure
*/
int i2c_write(uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
int len)
{
u32 op_status = TSI108_I2C_PARAM_ERR;
@ -265,10 +263,10 @@ int i2c_write(uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
while (len--) {
op_status =
i2c_write_byte(chip_addr, byte_addr++, buffer++);
i2c_write_byte (chip_addr, byte_addr++, buffer++);
if (TSI108_I2C_SUCCESS != op_status) {
DPRINT(("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len));
DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len));
break;
}
@ -284,7 +282,7 @@ int i2c_write(uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
* Returns 0 if a chip responded, not 0 on failure.
*/
int i2c_probe(uchar chip)
int i2c_probe (uchar chip)
{
u32 tmp;
@ -293,8 +291,8 @@ int i2c_probe(uchar chip)
* The Tsi108 HW doesn't support sending just the chip address
* and checkong for an <ACK> back.
*/
return i2c_read(chip, 0, 1, (char *)&tmp, 1);
return i2c_read (chip, 0, 1, (char *)&tmp, 1);
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */
#endif /* (CONFIG_COMMANDS & CFG_CMD_I2C) */
#endif /* CONFIG_TSI108_I2C */

34
drivers/tsi108_pci.c
View File

@ -36,7 +36,7 @@
struct pci_controller local_hose;
void tsi108_clear_pci_error(void)
void tsi108_clear_pci_error (void)
{
u32 err_stat, err_addr, pci_stat;
@ -79,11 +79,11 @@ void tsi108_clear_pci_error(void)
return;
}
unsigned int __get_pci_config_dword(u32 addr)
unsigned int __get_pci_config_dword (u32 addr)
{
unsigned int retval;
__asm__ __volatile__(" lwbrx %0,0,%1\n"
__asm__ __volatile__ (" lwbrx %0,0,%1\n"
"1: eieio\n"
"2:\n"
".section .fixup,\"ax\"\n"
@ -97,53 +97,53 @@ unsigned int __get_pci_config_dword(u32 addr)
return (retval);
}
static int tsi108_read_config_dword(struct pci_controller *hose,
static int tsi108_read_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 * value)
{
dev &= (CFG_PCI_CFG_SIZE - 1);
dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc));
*value = __get_pci_config_dword(dev);
if (0xFFFFFFFF == *value)
tsi108_clear_pci_error();
tsi108_clear_pci_error ();
return 0;
}
static int tsi108_write_config_dword(struct pci_controller *hose,
static int tsi108_write_config_dword (struct pci_controller *hose,
pci_dev_t dev, int offset, u32 value)
{
dev &= (CFG_PCI_CFG_SIZE - 1);
dev |= (CFG_PCI_CFG_BASE | (offset & 0xfc));
out_le32((volatile unsigned *)dev, value);
out_le32 ((volatile unsigned *)dev, value);
return 0;
}
void pci_init_board(void)
void pci_init_board (void)
{
struct pci_controller *hose = (struct pci_controller *)&local_hose;
hose->first_busno = 0;
hose->last_busno = 0xff;
pci_set_region(hose->regions + 0,
pci_set_region (hose->regions + 0,
CFG_PCI_MEMORY_BUS,
CFG_PCI_MEMORY_PHYS,
CFG_PCI_MEMORY_SIZE, PCI_REGION_MEM | PCI_REGION_MEMORY);
/* PCI memory space */
pci_set_region(hose->regions + 1,
pci_set_region (hose->regions + 1,
CFG_PCI_MEM_BUS,
CFG_PCI_MEM_PHYS, CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
/* PCI I/O space */
pci_set_region(hose->regions + 2,
pci_set_region (hose->regions + 2,
CFG_PCI_IO_BUS,
CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
hose->region_count = 3;
pci_set_ops(hose,
pci_set_ops (hose,
pci_hose_read_config_byte_via_dword,
pci_hose_read_config_word_via_dword,
tsi108_read_config_dword,
@ -151,22 +151,22 @@ void pci_init_board(void)
pci_hose_write_config_word_via_dword,
tsi108_write_config_dword);
pci_register_hose(hose);
pci_register_hose (hose);
hose->last_busno = pci_hose_scan(hose);
hose->last_busno = pci_hose_scan (hose);
debug("Done PCI initialization\n");
debug ("Done PCI initialization\n");
return;
}
#ifdef CONFIG_OF_FLAT_TREE
void
ft_pci_setup(void *blob, bd_t *bd)
ft_pci_setup (void *blob, bd_t *bd)
{
u32 *p;
int len;
p = (u32 *)ft_get_prop(blob, "/" OF_TSI "/pci@1000/bus-range", &len);
p = (u32 *)ft_get_prop (blob, "/" OF_TSI "/pci@1000/bus-range", &len);
if (p != NULL) {
p[0] = local_hose.first_busno;
p[1] = local_hose.last_busno;

290
include/configs/mpc7448hpc2.h
View File

@ -24,12 +24,11 @@
* MA 02111-1307 USA
*/
/****************************************************************
*
/*
* board specific configuration options for Freescale
* MPC7448HPC2 (High-Performance Computing II) (Taiga) board
*
****************************************************************/
*/
#ifndef __CONFIG_H
#define __CONFIG_H
@ -45,11 +44,11 @@
#define CONFIG_750FX /* this option to enable init of extended BATs */
#define CONFIG_ALTIVEC /* undef to disable */
#define CFG_BOARD_NAME "MPC7448 HPC II"
#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II"
#define CFG_BOARD_NAME "MPC7448 HPC II"
#define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II"
#define CFG_OCN_CLK 133000000 /* 133 MHz */
#define CFG_CONFIG_BUS_CLK 133000000
#define CFG_OCN_CLK 133000000 /* 133 MHz */
#define CFG_CONFIG_BUS_CLK 133000000
#define CFG_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */
@ -63,10 +62,10 @@
/* Default MAC Addresses for on-chip GIGE Controller */
#define CONFIG_ETHADDR 00:06:D2:00:00:01
#define CONFIG_ETHADDR 00:06:D2:00:00:01
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR 00:06:D2:00:00:02
#define CONFIG_ETH1ADDR 00:06:D2:00:00:02
#define CONFIG_ENV_OVERWRITE
@ -75,12 +74,12 @@
* (easy to change)
*/
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
/*#define CFG_HUSH_PARSER */
#undef CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#define CFG_PROMPT_HUSH_PS2 "> "
/* Pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE 1
@ -99,29 +98,30 @@
* for your console driver.
*
* what to do:
* If you have hacked a serial cable onto the second DUART channel, change the CFG_DUART port from 1
* to 0 below.
* If you have hacked a serial cable onto the second DUART channel,
* change the CFG_DUART port from 1 to 0 below.
*
*/
#define CONFIG_CONS_INDEX 1
#define CONFIG_CONS_INDEX 1
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_REG_SIZE 1
#define CFG_NS16550_CLK CFG_OCN_CLK * 8
#define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808)
#define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08)
#define CFG_NS16550_COM1 (CFG_TSI108_CSR_RST_BASE+0x7808)
#define CFG_NS16550_COM2 (CFG_TSI108_CSR_RST_BASE+0x7C08)
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
#define CONFIG_ZERO_BOOTDELAY_CHECK
#undef CONFIG_BOOTARGS
/*#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
/* #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\"
* to mount root filesystem over NFS;echo" */
#if (CONFIG_BOOTDELAY >= 0)
#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
#define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
@ -130,34 +130,34 @@
#undef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_SERIAL "No. 1"
#define CONFIG_SERIAL "No. 1"
/* Networking Configuration */
#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */
#define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */
#define CONFIG_TSI108_ETH
#define CONFIG_TSI108_ETH_NUM_PORTS 2
#define CONFIG_TSI108_ETH_NUM_PORTS 2
#define CONFIG_NET_MULTI
#define CONFIG_IPADDR 172.27.234.48
#define CONFIG_SERVERIP 172.27.234.10
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_GATEWAYIP 172.27.255.254
#define CONFIG_IPADDR 172.27.234.48
#define CONFIG_SERVERIP 172.27.234.10
#define CONFIG_NETMASK 255.255.0.0
#define CONFIG_GATEWAYIP 172.27.255.254
#define CONFIG_BOOTFILE zImage.initrd.elf
#define CONFIG_LOADADDR 0x400000
#define CONFIG_BOOTFILE zImage.initrd.elf
#define CONFIG_LOADADDR 0x400000
/*-------------------------------------------------------------------------- */
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
#undef CONFIG_WATCHDOG /* watchdog disabled */
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_BOOTFILESIZE)
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
| CFG_CMD_ASKENV \
@ -178,59 +178,59 @@
/*set date in u-boot*/
#define CONFIG_RTC_M48T35A
#define CFG_NVRAM_BASE_ADDR 0xfc000000
#define CFG_NVRAM_SIZE 0x8000
#define CFG_NVRAM_BASE_ADDR 0xfc000000
#define CFG_NVRAM_SIZE 0x8000
/*
* Miscellaneous configurable options
*/
#define CONFIG_VERSION_VARIABLE 1
#define CONFIG_VERSION_VARIABLE 1
#define CONFIG_TSI108_I2C
#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */
#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
#else
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)/* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
/*
#define CFG_DRAM_TEST
* DRAM tests
* CFG_DRAM_TEST - enables the following tests.
* DRAM tests
* CFG_DRAM_TEST - enables the following tests.
*
* CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
* Environment variable 'test_dram_data' must be
* set to 'y'.
* CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word is uniquely
* addressable. Environment variable
* 'test_dram_address' must be set to 'y'.
* CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
* This test takes about 6 minutes to test 64 MB.
* Environment variable 'test_dram_walk' must be
* set to 'y'.
* CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
* Environment variable 'test_dram_data' must be
* set to 'y'.
* CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word
* is uniquely addressable. Environment variable
* 'test_dram_address' must be set to 'y'.
* CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
* This test takes about 6 minutes to test 64 MB.
* Environment variable 'test_dram_walk' must be
* set to 'y'.
*/
#undef CFG_DRAM_TEST
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
#if defined(CFG_DRAM_TEST)
#define CFG_DRAM_TEST_DATA
#define CFG_DRAM_TEST_ADDRESS
#define CFG_DRAM_TEST_WALK
#endif /* CFG_DRAM_TEST */
#endif /* CFG_DRAM_TEST */
#define CFG_LOAD_ADDR 0x00400000 /* default load address */
#define CFG_LOAD_ADDR 0x00400000 /* default load address */
#define CFG_HZ 1000 /* decr freq: 1ms ticks */
#define CFG_HZ 1000 /* decr freq: 1ms ticks */
/*
* Low Level Configuration Settings
@ -246,12 +246,12 @@
* When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
* To an unused memory region. The stack will remain in cache until RAM
* is initialized
*/
*/
#undef CFG_INIT_RAM_LOCK
#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */
#define CFG_INIT_RAM_END 0x4000 /* larger space - we have SDRAM initialized */
#define CFG_INIT_RAM_ADDR 0x07d00000 /* unused memory region */
#define CFG_INIT_RAM_END 0x4000/* larger space - we have SDRAM initialized */
#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
#define CFG_GBL_DATA_SIZE 128/* size in bytes reserved for init data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
/*-----------------------------------------------------------------------
@ -260,54 +260,54 @@
* Please note that CFG_SDRAM_BASE _must_ start at 0
*/
#define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */
#define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */
#define CFG_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */
#define CFG_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */
#define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */
#define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */
#define CFG_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */
#define CFG_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */
#define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
#define CFG_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
#define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
#define CFG_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
#define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */
#define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */
#define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */
#define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */
#define CFG_FLASH_BASE 0xff000000 /* Base Address of Flash device */
#define CFG_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */
#define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */
#define PCI0_IO_BASE_BOOTM 0xfd000000
#define PCI0_IO_BASE_BOOTM 0xfd000000
#define CFG_RESET_ADDRESS 0x3fffff00
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
#define CFG_RESET_ADDRESS 0x3fffff00
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE TEXT_BASE /* u-boot code base */
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
/* Peripheral Device section */
/*******************************************************
/*
* Resources on the Tsi108
*******************************************************/
*/
#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */
#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
#define CFG_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */
#define CFG_TSI108_CSR_BASE CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
#define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */
#undef DISABLE_PBM
/*-----------------------------------------------------------------------
/*
* PCI stuff
*-----------------------------------------------------------------------
*
*/
#define CONFIG_PCI /* include pci support */
#define CONFIG_TSI108_PCI /* include tsi108 pci support */
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
#define PCI_HOST_FORCE 1 /* configure as pci host */
#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
#define CONFIG_PCI_PNP /* do pci plug-and-play */
@ -315,20 +315,20 @@
/* PCI MEMORY MAP section */
/* PCI view of System Memory */
#define CFG_PCI_MEMORY_BUS 0x00000000
#define CFG_PCI_MEMORY_PHYS 0x00000000
#define CFG_PCI_MEMORY_SIZE 0x80000000
#define CFG_PCI_MEMORY_BUS 0x00000000
#define CFG_PCI_MEMORY_PHYS 0x00000000
#define CFG_PCI_MEMORY_SIZE 0x80000000
/* PCI Memory Space */
#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS)
#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) //CFG_PCI_MEM32_BASE = 0xE0000000
#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */
#define CFG_PCI_MEM_BUS (CFG_PCI_MEM_PHYS)
#define CFG_PCI_MEM_PHYS (CFG_PCI_MEM32_BASE) /* 0xE0000000 */
#define CFG_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */
/* PCI I/O Space */
#define CFG_PCI_IO_BUS 0x00000000
#define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */
#define CFG_PCI_IO_BUS 0x00000000
#define CFG_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */
#define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */
#define CFG_PCI_IO_SIZE 0x01000000 /* 16MB */
#define _IO_BASE 0x00000000 /* points to PCI I/O space */
@ -336,91 +336,91 @@
#define CFG_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */
#define CFG_PCI_CFG_SIZE 0x01000000 /* 16MB */
#define CFG_IBAT0U 0xFE0003FF
#define CFG_IBAT0L 0xFE000002
#define CFG_IBAT0U 0xFE0003FF
#define CFG_IBAT0L 0xFE000002
#define CFG_IBAT1U 0x00007FFF
#define CFG_IBAT1L 0x00000012
#define CFG_IBAT1U 0x00007FFF
#define CFG_IBAT1L 0x00000012
#define CFG_IBAT2U 0x80007FFF
#define CFG_IBAT2L 0x80000022
#define CFG_IBAT2U 0x80007FFF
#define CFG_IBAT2L 0x80000022
#define CFG_IBAT3U 0x00000000
#define CFG_IBAT3L 0x00000000
#define CFG_IBAT3U 0x00000000
#define CFG_IBAT3L 0x00000000
#define CFG_IBAT4U 0x00000000
#define CFG_IBAT4L 0x00000000
#define CFG_IBAT4U 0x00000000
#define CFG_IBAT4L 0x00000000
#define CFG_IBAT5U 0x00000000
#define CFG_IBAT5L 0x00000000
#define CFG_IBAT5U 0x00000000
#define CFG_IBAT5L 0x00000000
#define CFG_IBAT6U 0x00000000
#define CFG_IBAT6L 0x00000000
#define CFG_IBAT6U 0x00000000
#define CFG_IBAT6L 0x00000000
#define CFG_IBAT7U 0x00000000
#define CFG_IBAT7L 0x00000000
#define CFG_IBAT7U 0x00000000
#define CFG_IBAT7L 0x00000000
#define CFG_DBAT0U 0xE0003FFF
#define CFG_DBAT0L 0xE000002A
#define CFG_DBAT0U 0xE0003FFF
#define CFG_DBAT0L 0xE000002A
#define CFG_DBAT1U 0x00007FFF
#define CFG_DBAT1L 0x00000012
#define CFG_DBAT1U 0x00007FFF
#define CFG_DBAT1L 0x00000012
#define CFG_DBAT2U 0x00000000
#define CFG_DBAT2L 0x00000000
#define CFG_DBAT2U 0x00000000
#define CFG_DBAT2L 0x00000000
#define CFG_DBAT3U 0xC0000003
#define CFG_DBAT3L 0xC000002A
#define CFG_DBAT3U 0xC0000003
#define CFG_DBAT3L 0xC000002A
#define CFG_DBAT4U 0x00000000
#define CFG_DBAT4L 0x00000000
#define CFG_DBAT4U 0x00000000
#define CFG_DBAT4L 0x00000000
#define CFG_DBAT5U 0x00000000
#define CFG_DBAT5L 0x00000000
#define CFG_DBAT5U 0x00000000
#define CFG_DBAT5L 0x00000000
#define CFG_DBAT6U 0x00000000
#define CFG_DBAT6L 0x00000000
#define CFG_DBAT6U 0x00000000
#define CFG_DBAT6L 0x00000000
#define CFG_DBAT7U 0x00000000
#define CFG_DBAT7L 0x00000000
#define CFG_DBAT7U 0x00000000
#define CFG_DBAT7L 0x00000000
/* I2C addresses for the two DIMM SPD chips */
#define DIMM0_I2C_ADDR 0x51
#define DIMM1_I2C_ADDR 0x52
#define DIMM0_I2C_ADDR 0x51
#define DIMM1_I2C_ADDR 0x52
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
* FLASH organization
*/
#define CFG_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */
#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
#define CFG_MAX_FLASH_BANKS 1/* Flash can be at one of two addresses */
#define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI
#define CFG_FLASH_CFI_SWAP
#define PHYS_FLASH_SIZE 0x01000000
#define CFG_MAX_FLASH_SECT (128)
#define PHYS_FLASH_SIZE 0x01000000
#define CFG_MAX_FLASH_SECT (128)
#define CFG_ENV_IS_IN_NVRAM
#define CFG_ENV_ADDR 0xFC000000
#define CFG_ENV_ADDR 0xFC000000
#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */
#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */
#define CFG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */
/*-----------------------------------------------------------------------
* Cache Configuration
*/
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
/*-----------------------------------------------------------------------
@ -429,16 +429,16 @@
*/
#undef CFG_L2
#define L2_INIT 0
#define L2_ENABLE (L2_INIT | L2CR_L2E)
#define L2_INIT 0
#define L2_ENABLE (L2_INIT | L2CR_L2E)
/*
* Internal Definitions
*
* Boot Flags
*/
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_EXCEPTION_AFTER_RELOCATE
#define CFG_SERIAL_HANG_IN_EXCEPTION
#endif /* __CONFIG_H */
#endif /* __CONFIG_H */

248
include/tsi108.h
View File

@ -31,191 +31,191 @@
#ifndef _TSI108_H_
#define _TSI108_H_
#define TSI108_HLP_REG_OFFSET (0x0000)
#define TSI108_PCI_REG_OFFSET (0x1000)
#define TSI108_CLK_REG_OFFSET (0x2000)
#define TSI108_PB_REG_OFFSET (0x3000)
#define TSI108_SD_REG_OFFSET (0x4000)
#define TSI108_MPIC_REG_OFFSET (0x7400)
#define TSI108_HLP_REG_OFFSET (0x0000)
#define TSI108_PCI_REG_OFFSET (0x1000)
#define TSI108_CLK_REG_OFFSET (0x2000)
#define TSI108_PB_REG_OFFSET (0x3000)
#define TSI108_SD_REG_OFFSET (0x4000)
#define TSI108_MPIC_REG_OFFSET (0x7400)
#define PB_ID (0x000)
#define PB_RSR (0x004)
#define PB_BUS_MS_SELECT (0x008)
#define PB_ISR (0x00C)
#define PB_ARB_CTRL (0x018)
#define PB_PVT_CTRL2 (0x034)
#define PB_SCR (0x400)
#define PB_ERRCS (0x404)
#define PB_AERR (0x408)
#define PB_REG_BAR (0x410)
#define PB_OCN_BAR1 (0x414)
#define PB_OCN_BAR2 (0x418)
#define PB_SDRAM_BAR1 (0x41C)
#define PB_SDRAM_BAR2 (0x420)
#define PB_MCR (0xC00)
#define PB_MCMD (0xC04)
#define PB_ID (0x000)
#define PB_RSR (0x004)
#define PB_BUS_MS_SELECT (0x008)
#define PB_ISR (0x00C)
#define PB_ARB_CTRL (0x018)
#define PB_PVT_CTRL2 (0x034)
#define PB_SCR (0x400)
#define PB_ERRCS (0x404)
#define PB_AERR (0x408)
#define PB_REG_BAR (0x410)
#define PB_OCN_BAR1 (0x414)
#define PB_OCN_BAR2 (0x418)
#define PB_SDRAM_BAR1 (0x41C)
#define PB_SDRAM_BAR2 (0x420)
#define PB_MCR (0xC00)
#define PB_MCMD (0xC04)
#define HLP_B0_ADDR (0x000)
#define HLP_B1_ADDR (0x010)
#define HLP_B2_ADDR (0x020)
#define HLP_B3_ADDR (0x030)
#define HLP_B0_ADDR (0x000)
#define HLP_B1_ADDR (0x010)
#define HLP_B2_ADDR (0x020)
#define HLP_B3_ADDR (0x030)
#define HLP_B0_MASK (0x004)
#define HLP_B1_MASK (0x014)
#define HLP_B2_MASK (0x024)
#define HLP_B3_MASK (0x034)
#define HLP_B0_MASK (0x004)
#define HLP_B1_MASK (0x014)
#define HLP_B2_MASK (0x024)
#define HLP_B3_MASK (0x034)
#define HLP_B0_CTRL0 (0x008)
#define HLP_B1_CTRL0 (0x018)
#define HLP_B2_CTRL0 (0x028)
#define HLP_B3_CTRL0 (0x038)
#define HLP_B0_CTRL0 (0x008)
#define HLP_B1_CTRL0 (0x018)
#define HLP_B2_CTRL0 (0x028)
#define HLP_B3_CTRL0 (0x038)
#define HLP_B0_CTRL1 (0x00C)
#define HLP_B1_CTRL1 (0x01C)
#define HLP_B2_CTRL1 (0x02C)
#define HLP_B3_CTRL1 (0x03C)
#define HLP_B0_CTRL1 (0x00C)
#define HLP_B1_CTRL1 (0x01C)
#define HLP_B2_CTRL1 (0x02C)
#define HLP_B3_CTRL1 (0x03C)
#define PCI_CSR (0x004)
#define PCI_P2O_BAR0 (0x010)
#define PCI_P2O_BAR0_UPPER (0x014)
#define PCI_P2O_BAR2 (0x018)
#define PCI_P2O_BAR2_UPPER (0x01C)
#define PCI_P2O_BAR3 (0x020)
#define PCI_P2O_BAR3_UPPER (0x024)
#define PCI_CSR (0x004)
#define PCI_P2O_BAR0 (0x010)
#define PCI_P2O_BAR0_UPPER (0x014)
#define PCI_P2O_BAR2 (0x018)
#define PCI_P2O_BAR2_UPPER (0x01C)
#define PCI_P2O_BAR3 (0x020)
#define PCI_P2O_BAR3_UPPER (0x024)
#define PCI_MISC_CSR (0x040)
#define PCI_P2O_PAGE_SIZES (0x04C)
#define PCI_MISC_CSR (0x040)
#define PCI_P2O_PAGE_SIZES (0x04C)
#define PCI_PCIX_STAT (0x0F4)
#define PCI_PCIX_STAT (0x0F4)
#define PCI_IRP_STAT (0x184)
#define PCI_IRP_STAT (0x184)
#define PCI_PFAB_BAR0 (0x204)
#define PCI_PFAB_BAR0_UPPER (0x208)
#define PCI_PFAB_IO (0x20C)
#define PCI_PFAB_IO_UPPER (0x210)
#define PCI_PFAB_BAR0 (0x204)
#define PCI_PFAB_BAR0_UPPER (0x208)
#define PCI_PFAB_IO (0x20C)
#define PCI_PFAB_IO_UPPER (0x210)
#define PCI_PFAB_MEM32 (0x214)
#define PCI_PFAB_MEM32_REMAP (0x218)
#define PCI_PFAB_MEM32_MASK (0x21C)
#define PCI_PFAB_MEM32 (0x214)
#define PCI_PFAB_MEM32_REMAP (0x218)
#define PCI_PFAB_MEM32_MASK (0x21C)
#define CG_PLL0_CTRL0 (0x210)
#define CG_PLL0_CTRL1 (0x214)
#define CG_PLL1_CTRL0 (0x220)
#define CG_PLL1_CTRL1 (0x224)
#define CG_PWRUP_STATUS (0x234)
#define CG_PLL0_CTRL0 (0x210)
#define CG_PLL0_CTRL1 (0x214)
#define CG_PLL1_CTRL0 (0x220)
#define CG_PLL1_CTRL1 (0x224)
#define CG_PWRUP_STATUS (0x234)
#define MPIC_CSR(n) (0x30C + (n * 0x40))
#define SD_CTRL (0x000)
#define SD_STATUS (0x004)
#define SD_TIMING (0x008)
#define SD_REFRESH (0x00C)
#define SD_INT_STATUS (0x010)
#define SD_INT_ENABLE (0x014)
#define SD_INT_SET (0x018)
#define SD_D0_CTRL (0x020)
#define SD_D1_CTRL (0x024)
#define SD_D0_BAR (0x028)
#define SD_D1_BAR (0x02C)
#define SD_ECC_CTRL (0x040)
#define SD_DLL_STATUS (0x250)
#define SD_CTRL (0x000)
#define SD_STATUS (0x004)
#define SD_TIMING (0x008)
#define SD_REFRESH (0x00C)
#define SD_INT_STATUS (0x010)
#define SD_INT_ENABLE (0x014)
#define SD_INT_SET (0x018)
#define SD_D0_CTRL (0x020)
#define SD_D1_CTRL (0x024)
#define SD_D0_BAR (0x028)
#define SD_D1_BAR (0x02C)
#define SD_ECC_CTRL (0x040)
#define SD_DLL_STATUS (0x250)
#define TS_SD_CTRL_ENABLE (1 << 31)
#define TS_SD_CTRL_ENABLE (1 << 31)
#define PB_ERRCS_ES (1 << 1)
#define PB_ISR_PBS_RD_ERR (1 << 8)
#define PCI_IRP_STAT_P_CSR (1 << 23)
#define PB_ERRCS_ES (1 << 1)
#define PB_ISR_PBS_RD_ERR (1 << 8)
#define PCI_IRP_STAT_P_CSR (1 << 23)
/*
* I2C : Register address offset definitions
*/
#define I2C_CNTRL1 (0x00000000)
#define I2C_CNTRL2 (0x00000004)
#define I2C_RD_DATA (0x00000008)
#define I2C_TX_DATA (0x0000000c)
#define I2C_CNTRL1 (0x00000000)
#define I2C_CNTRL2 (0x00000004)
#define I2C_RD_DATA (0x00000008)
#define I2C_TX_DATA (0x0000000c)
/*
* I2C : Register Bit Masks and Reset Values
* definitions for every register
* definitions for every register
*/
/* I2C_CNTRL1 : Reset Value */
#define I2C_CNTRL1_RESET_VALUE (0x0000000a)
#define I2C_CNTRL1_RESET_VALUE (0x0000000a)
/* I2C_CNTRL1 : Register Bits Masks Definitions */
#define I2C_CNTRL1_DEVCODE (0x0000000f)
#define I2C_CNTRL1_PAGE (0x00000700)
#define I2C_CNTRL1_BYTADDR (0x00ff0000)
#define I2C_CNTRL1_I2CWRITE (0x01000000)
#define I2C_CNTRL1_DEVCODE (0x0000000f)
#define I2C_CNTRL1_PAGE (0x00000700)
#define I2C_CNTRL1_BYTADDR (0x00ff0000)
#define I2C_CNTRL1_I2CWRITE (0x01000000)
/* I2C_CNTRL1 : Read/Write Bit Mask Definition */
#define I2C_CNTRL1_RWMASK (0x01ff070f)
#define I2C_CNTRL1_RWMASK (0x01ff070f)
/* I2C_CNTRL1 : Unused/Reserved bits Definition */
#define I2C_CNTRL1_RESERVED (0xfe00f8f0)
#define I2C_CNTRL1_RESERVED (0xfe00f8f0)
/* I2C_CNTRL2 : Reset Value */
#define I2C_CNTRL2_RESET_VALUE (0x00000000)
#define I2C_CNTRL2_RESET_VALUE (0x00000000)
/* I2C_CNTRL2 : Register Bits Masks Definitions */
#define I2C_CNTRL2_SIZE (0x00000003)
#define I2C_CNTRL2_LANE (0x0000000c)
#define I2C_CNTRL2_MULTIBYTE (0x00000010)
#define I2C_CNTRL2_START (0x00000100)
#define I2C_CNTRL2_WR_STATUS (0x00010000)
#define I2C_CNTRL2_RD_STATUS (0x00020000)
#define I2C_CNTRL2_I2C_TO_ERR (0x04000000)
#define I2C_CNTRL2_I2C_CFGERR (0x08000000)
#define I2C_CNTRL2_I2C_CMPLT (0x10000000)
#define I2C_CNTRL2_SIZE (0x00000003)
#define I2C_CNTRL2_LANE (0x0000000c)
#define I2C_CNTRL2_MULTIBYTE (0x00000010)
#define I2C_CNTRL2_START (0x00000100)
#define I2C_CNTRL2_WR_STATUS (0x00010000)
#define I2C_CNTRL2_RD_STATUS (0x00020000)
#define I2C_CNTRL2_I2C_TO_ERR (0x04000000)
#define I2C_CNTRL2_I2C_CFGERR (0x08000000)
#define I2C_CNTRL2_I2C_CMPLT (0x10000000)
/* I2C_CNTRL2 : Read/Write Bit Mask Definition */
#define I2C_CNTRL2_RWMASK (0x0000011f)
#define I2C_CNTRL2_RWMASK (0x0000011f)
/* I2C_CNTRL2 : Unused/Reserved bits Definition */
#define I2C_CNTRL2_RESERVED (0xe3fcfee0)
#define I2C_CNTRL2_RESERVED (0xe3fcfee0)
/* I2C_RD_DATA : Reset Value */
#define I2C_RD_DATA_RESET_VALUE (0x00000000)
#define I2C_RD_DATA_RESET_VALUE (0x00000000)
/* I2C_RD_DATA : Register Bits Masks Definitions */
#define I2C_RD_DATA_RBYTE0 (0x000000ff)
#define I2C_RD_DATA_RBYTE1 (0x0000ff00)
#define I2C_RD_DATA_RBYTE2 (0x00ff0000)
#define I2C_RD_DATA_RBYTE3 (0xff000000)
#define I2C_RD_DATA_RBYTE0 (0x000000ff)
#define I2C_RD_DATA_RBYTE1 (0x0000ff00)
#define I2C_RD_DATA_RBYTE2 (0x00ff0000)
#define I2C_RD_DATA_RBYTE3 (0xff000000)
/* I2C_RD_DATA : Read/Write Bit Mask Definition */
#define I2C_RD_DATA_RWMASK (0x00000000)
#define I2C_RD_DATA_RWMASK (0x00000000)
/* I2C_RD_DATA : Unused/Reserved bits Definition */
#define I2C_RD_DATA_RESERVED (0x00000000)
#define I2C_RD_DATA_RESERVED (0x00000000)
/* I2C_TX_DATA : Reset Value */
#define I2C_TX_DATA_RESET_VALUE (0x00000000)
#define I2C_TX_DATA_RESET_VALUE (0x00000000)
/* I2C_TX_DATA : Register Bits Masks Definitions */
#define I2C_TX_DATA_TBYTE0 (0x000000ff)
#define I2C_TX_DATA_TBYTE1 (0x0000ff00)
#define I2C_TX_DATA_TBYTE2 (0x00ff0000)
#define I2C_TX_DATA_TBYTE3 (0xff000000)
#define I2C_TX_DATA_TBYTE0 (0x000000ff)
#define I2C_TX_DATA_TBYTE1 (0x0000ff00)
#define I2C_TX_DATA_TBYTE2 (0x00ff0000)
#define I2C_TX_DATA_TBYTE3 (0xff000000)
/* I2C_TX_DATA : Read/Write Bit Mask Definition */
#define I2C_TX_DATA_RWMASK (0xffffffff)
#define I2C_TX_DATA_RWMASK (0xffffffff)
/* I2C_TX_DATA : Unused/Reserved bits Definition */
#define I2C_TX_DATA_RESERVED (0x00000000)
#define I2C_TX_DATA_RESERVED (0x00000000)
#define TSI108_I2C_OFFSET 0x7000 /* register block offset for general use I2C channel */
#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* register block offset for SPD I2C channel */
#define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */
#define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */
#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */
#define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */
/* I2C status codes */
#define TSI108_I2C_SUCCESS 0
#define TSI108_I2C_PARAM_ERR 1
#define TSI108_I2C_TIMEOUT_ERR 2
#define TSI108_I2C_IF_BUSY 3
#define TSI108_I2C_IF_ERROR 4
#define TSI108_I2C_SUCCESS 0
#define TSI108_I2C_PARAM_ERR 1
#define TSI108_I2C_TIMEOUT_ERR 2
#define TSI108_I2C_IF_BUSY 3
#define TSI108_I2C_IF_ERROR 4
#endif /* _TSI108_H_ */