Additional fix for external IRQ config on Yellowstone & Yosemite
Patch by Stefan Roese, 03 Nov 2005
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@ -2,6 +2,9 @@
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Changes for U-Boot 1.1.4:
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Changes for U-Boot 1.1.4:
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======================================================================
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======================================================================
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* Additional fix for external IRQ config on Yellowstone & Yosemite
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Patch by Stefan Roese, 03 Nov 2005
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* Add support for Ocotea pass 3 with 440GX Rev. F
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* Add support for Ocotea pass 3 with 440GX Rev. F
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Patch by Stefan Roese, 01 Nov 2005
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Patch by Stefan Roese, 01 Nov 2005
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@ -55,25 +55,6 @@ int board_early_init_f(void)
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mtebc(pb5ap, 0x00000000);
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mtebc(pb5ap, 0x00000000);
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mtebc(pb5cr, 0x00000000);
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mtebc(pb5cr, 0x00000000);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
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mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
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mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
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mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000000); /* all non-critical */
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mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
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mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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/*--------------------------------------------------------------------
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/*--------------------------------------------------------------------
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* Setup the GPIO pins
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* Setup the GPIO pins
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*-------------------------------------------------------------------*/
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*-------------------------------------------------------------------*/
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@ -109,6 +90,25 @@ int board_early_init_f(void)
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out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
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out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
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#endif
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#endif
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
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mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
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mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
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mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000000); /* all non-critical */
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mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
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mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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/*--------------------------------------------------------------------
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/*--------------------------------------------------------------------
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* Setup other serial configuration
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* Setup other serial configuration
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*-------------------------------------------------------------------*/
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*-------------------------------------------------------------------*/
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@ -55,25 +55,6 @@ int board_early_init_f(void)
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mtebc(pb5ap, 0x00000000);
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mtebc(pb5ap, 0x00000000);
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mtebc(pb5cr, 0x00000000);
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mtebc(pb5cr, 0x00000000);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
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mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
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mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
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mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000000); /* all non-critical */
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mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
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mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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/*--------------------------------------------------------------------
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/*--------------------------------------------------------------------
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* Setup the GPIO pins
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* Setup the GPIO pins
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*-------------------------------------------------------------------*/
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*-------------------------------------------------------------------*/
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@ -107,6 +88,25 @@ int board_early_init_f(void)
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out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
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out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
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out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
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out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic0er, 0x00000000); /* disable all */
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mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
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mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
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mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
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mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic0sr, 0xffffffff); /* clear all */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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mtdcr(uic1er, 0x00000000); /* disable all */
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mtdcr(uic1cr, 0x00000000); /* all non-critical */
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mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
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mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
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mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(uic1sr, 0xffffffff); /* clear all */
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/*--------------------------------------------------------------------
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/*--------------------------------------------------------------------
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* Setup other serial configuration
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* Setup other serial configuration
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*-------------------------------------------------------------------*/
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*-------------------------------------------------------------------*/
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