sysmo-bts
/
u-boot
9
0
Fork 0
Code Pull Requests Releases Activity

Fix the BAT definition of PCI IO on 8610 board 

The address in the BAT register is aligned with the BAT size.
The original definition actually did not define BAT for PCIE2 IO.
This patch fix this.

Signed-off-by: Jason Jin <Jason.jin@freescale.com>
This commit is contained in:
Jason Jin 2007-10-26 18:31:59 +08:00 committed by Jon Loeliger
parent 607b3ae27e
commit f3bceaab23
1 changed files with 7 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
include/configs/MPC8610HPCD.h
View File

@ -361,28 +361,26 @@
#define CFG_IBAT1U CFG_DBAT1U
/*
* BAT2 32M Cache-inhibited, guarded
* BAT2 16M Cache-inhibited, guarded
* 0xe100_0000 1M PCI-1 I/O
* 0xe200_0000 1M PCI-Express 2 I/O
*
*/
#define CFG_DBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CFG_DBAT2U (CFG_PCI1_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
#define CFG_DBAT2U (CFG_PCI1_IO_PHYS | BATU_BL_16M | BATU_VS | BATU_VP)
#define CFG_IBAT2L (CFG_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT2U CFG_DBAT2U
/*
* BAT3 1M Cache-inhibited, guarded
* BAT3 32M Cache-inhibited, guarded
* 0xe200_0000 1M PCI-Express 2 I/O
* 0xe300_0000 1M PCI-Express 1 I/O
*
*/
#define CFG_DBAT3L (CFG_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
#define CFG_DBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CFG_DBAT3U (CFG_PCIE1_IO_PHYS | BATU_BL_1M | BATU_VS | BATU_VP)
#define CFG_IBAT3L (CFG_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_DBAT3U (CFG_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
#define CFG_IBAT3L (CFG_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
#define CFG_IBAT3U CFG_DBAT3U
/*