arm: Move SYS_FSL_SRDS_* and SYS_HAS_SERDES to Kconfig
Move these options to Kconfig and clean up existing uses. Signed-off-by: York Sun <york.sun@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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@ -1,6 +1,8 @@
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config ARCH_LS1021A
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bool
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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menu "LS102xA architecture"
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depends on ARCH_LS1021A
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@ -23,6 +25,15 @@ config MAX_CPUS
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config SYS_FSL_ERRATUM_A010315
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bool "Workaround for PCIe erratum A010315"
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config SYS_FSL_SRDS_1
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bool
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config SYS_FSL_SRDS_2
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bool
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config SYS_HAS_SERDES
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bool
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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depends on ARCH_LS1021A
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@ -14,16 +14,23 @@ config ARCH_LS1046A
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bool
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select FSL_LSCH2
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select SYS_FSL_ERRATUM_A010539
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select SYS_FSL_SRDS_2
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config ARCH_LS2080A
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bool
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select FSL_LSCH3
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select SYS_FSL_HAS_DP_DDR
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select SYS_FSL_SRDS_2
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config FSL_LSCH2
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bool
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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config FSL_LSCH3
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bool
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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menu "Layerscape architecture"
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depends on FSL_LSCH2 || FSL_LSCH3
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@ -65,4 +72,13 @@ config SYS_FSL_IFC_BANK_COUNT
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config SYS_FSL_HAS_DP_DDR
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bool
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config SYS_FSL_SRDS_1
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bool
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config SYS_FSL_SRDS_2
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bool
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config SYS_HAS_SERDES
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bool
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endmenu
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@ -32,8 +32,6 @@
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#ifdef CONFIG_LS2080A
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
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#define SRDS_MAX_LANES 8
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#define CONFIG_SYS_FSL_SRDS_1
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#define CONFIG_SYS_FSL_SRDS_2
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#define CONFIG_SYS_PAGE_SIZE 0x10000
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#ifndef L1_CACHE_BYTES
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#define L1_CACHE_SHIFT 6
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@ -162,8 +160,6 @@
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#define CONFIG_SYS_FSL_PEX_LUT_BE
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#define CONFIG_SYS_FSL_SEC_BE
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#define CONFIG_SYS_FSL_SRDS_1
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/* SoC related */
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#ifdef CONFIG_LS1043A
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#define CONFIG_SYS_FMAN_V3
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@ -212,7 +208,6 @@
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_FSL_SRDS_2
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#define CONFIG_SYS_FSL_IFC_BE
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#define CONFIG_SYS_FSL_SFP_VER_3_2
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#define CONFIG_SYS_FSL_SNVS_LE
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@ -120,8 +120,6 @@
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#define DCU_LAYER_MAX_NUM 16
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#define CONFIG_SYS_FSL_SRDS_1
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#ifdef CONFIG_LS102XA
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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@ -10,8 +10,6 @@
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#define CONFIG_FSL_LAYERSCAPE
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#define CONFIG_GICV2
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#define CONFIG_SYS_HAS_SERDES
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#include <asm/arch/config.h>
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#define CONFIG_SYS_NO_FLASH
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@ -142,8 +142,6 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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#define CONFIG_SYS_HAS_SERDES
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#define CONFIG_FSL_CAAM /* Enable CAAM */
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#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
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@ -169,8 +169,6 @@
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_HAS_SERDES
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#define CONFIG_FSL_CAAM /* Enable CAAM */
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#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
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@ -15,9 +15,6 @@
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#define CONFIG_GICV2
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#include <asm/arch/config.h>
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#ifdef CONFIG_SYS_FSL_SRDS_1
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#define CONFIG_SYS_HAS_SERDES
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#endif
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
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@ -52,8 +52,6 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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#define CONFIG_SYS_HAS_SERDES
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#ifdef CONFIG_SYS_DPAA_FMAN
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#define CONFIG_FMAN_ENET
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#define CONFIG_PHYLIB
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@ -14,9 +14,6 @@
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#define CONFIG_GICV2
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#include <asm/arch/config.h>
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#ifdef CONFIG_SYS_FSL_SRDS_1
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#define CONFIG_SYS_HAS_SERDES
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#endif
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
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@ -49,8 +49,6 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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#define CONFIG_SYS_HAS_SERDES
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/* DSPI */
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#ifdef CONFIG_FSL_DSPI
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#define CONFIG_SPI_FLASH_STMICRO /* cs0 */
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@ -15,9 +15,6 @@
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#include <asm/arch/ls2080a_stream_id.h>
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#include <asm/arch/config.h>
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#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
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#define CONFIG_SYS_HAS_SERDES
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#endif
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
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