arm: Remove polaris and trizepsiv boards
These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Simon Glass
Tom Rini
parent
8896325d73
commit
f6eac00aba
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@ -643,10 +643,6 @@ config TARGET_PXA255_IDP
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bool "Support pxa255_idp"
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select CPU_PXA
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config TARGET_TRIZEPSIV
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bool "Support trizepsiv"
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select CPU_PXA
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config TARGET_VPAC270
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bool "Support vpac270"
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select CPU_PXA
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@ -822,7 +818,6 @@ source "board/ti/ti816x/Kconfig"
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source "board/timll/devkit3250/Kconfig"
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source "board/toradex/colibri_pxa270/Kconfig"
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source "board/toradex/colibri_vf/Kconfig"
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source "board/trizepsiv/Kconfig"
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source "board/technologic/ts4800/Kconfig"
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source "board/ttcontrol/vision2/Kconfig"
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source "board/vpac270/Kconfig"
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@ -1,9 +0,0 @@
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if TARGET_TRIZEPSIV
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config SYS_BOARD
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default "trizepsiv"
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config SYS_CONFIG_NAME
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default "trizepsiv"
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endif
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@ -1,7 +0,0 @@
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TRIZEPSIV BOARD
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M: Stefano Babic <sbabic@denx.de>
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S: Maintained
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F: board/trizepsiv/
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F: include/configs/trizepsiv.h
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F: configs/polaris_defconfig
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F: configs/trizepsiv_defconfig
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@ -1,8 +0,0 @@
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#
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# (C) Copyright 2000-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := conxs.o eeprom.o
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@ -1,148 +0,0 @@
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/*
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* (C) Copyright 2007
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* Stefano Babic, DENX Gmbh, sbabic@denx.de
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*
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* (C) Copyright 2004
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* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
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*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/pxa.h>
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#include <asm/arch/regs-mmc.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <usb.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define RH_A_PSM (1 << 8) /* power switching mode */
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#define RH_A_NPS (1 << 9) /* no power switching */
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extern struct serial_device serial_ffuart_device;
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extern struct serial_device serial_btuart_device;
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extern struct serial_device serial_stuart_device;
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#if CONFIG_MK_POLARIS
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#define BOOT_CONSOLE "serial_stuart"
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#else
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#define BOOT_CONSOLE "serial_ffuart"
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#endif
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/* ------------------------------------------------------------------------- */
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int board_usb_init(int index, enum usb_init_type init)
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{
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writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
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~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
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UHCHR);
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writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
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while (readl(UHCHR) & UHCHR_FSBIR)
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;
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writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
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writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
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/* Clear any OTG Pin Hold */
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if (readl(PSSR) & PSSR_OTGPH)
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writel(readl(PSSR) | PSSR_OTGPH, PSSR);
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writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA);
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writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA);
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/* Set port power control mask bits, only 3 ports. */
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writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
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return 0;
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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return 0;
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}
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void usb_board_stop(void)
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{
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writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
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udelay(11);
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writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
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writel(readl(UHCCOMS) | 1, UHCCOMS);
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udelay(10);
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writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
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return;
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}
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int board_init (void)
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{
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/* We have RAM, disable cache */
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dcache_disable();
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icache_disable();
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/* arch number of ConXS Board */
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gd->bd->bi_arch_number = 776;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0xa000003c;
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return 0;
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}
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int board_late_init(void)
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{
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char *console=getenv("boot_console");
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if ((console == NULL) || (strcmp(console,"serial_btuart") &&
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strcmp(console,"serial_stuart") &&
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strcmp(console,"serial_ffuart"))) {
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console = BOOT_CONSOLE;
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}
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setenv("stdout",console);
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setenv("stdin", console);
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setenv("stderr",console);
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return 0;
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}
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int dram_init(void)
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{
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pxa2xx_dram_init();
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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}
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#ifdef CONFIG_DRIVER_DM9000
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int board_eth_init(bd_t *bis)
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{
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return dm9000_initialize(bis);
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}
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#endif
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#ifdef CONFIG_CMD_MMC
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int board_mmc_init(bd_t *bis)
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{
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pxa_mmc_register(0);
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return 0;
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}
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#endif
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@ -1,62 +0,0 @@
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/*
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* (C) Copyright 2007
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <dm9000.h>
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static int do_read_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
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unsigned int i;
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u8 data[2];
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for (i=0; i < 0x40; i++) {
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if (!(i % 0x10))
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printf("\n%08x:", i);
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dm9000_read_srom_word(i, data);
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printf(" %02x%02x", data[1], data[0]);
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}
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printf ("\n");
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return (0);
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}
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static int do_write_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
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int offset,value;
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if (argc < 4)
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return cmd_usage(cmdtp);
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offset=simple_strtoul(argv[2],NULL,16);
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value=simple_strtoul(argv[3],NULL,16);
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if (offset > 0x40) {
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printf("Wrong offset : 0x%x\n",offset);
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return cmd_usage(cmdtp);
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}
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dm9000_write_srom_word(offset, value);
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return (0);
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}
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int do_dm9000_eeprom ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
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if (argc < 2)
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return cmd_usage(cmdtp);
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if (strcmp (argv[1],"read") == 0)
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return (do_read_dm9000_eeprom(cmdtp,flag,argc,argv));
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else if (strcmp (argv[1],"write") == 0)
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return (do_write_dm9000_eeprom(cmdtp,flag,argc,argv));
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else
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return cmd_usage(cmdtp);
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}
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U_BOOT_CMD(
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dm9000ee,4,1,do_dm9000_eeprom,
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"Read/Write eeprom connected to Ethernet Controller",
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"\ndm9000ee write <word offset> <value> \n"
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"\tdm9000ee read \n"
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"\tword:\t\t00-02 : MAC Address\n"
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"\t\t\t03-07 : DM9000 Configuration\n"
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"\t\t\t08-63 : User data"
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);
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@ -1,4 +0,0 @@
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CONFIG_ARM=y
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CONFIG_TARGET_TRIZEPSIV=y
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CONFIG_SYS_EXTRA_OPTIONS="POLARIS"
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# CONFIG_CMD_SETEXPR is not set
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@ -1,3 +0,0 @@
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CONFIG_ARM=y
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CONFIG_TARGET_TRIZEPSIV=y
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# CONFIG_CMD_SETEXPR is not set
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@ -1,309 +0,0 @@
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/*
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* (C) Copyright 2007
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* Stefano Babic, DENX Gmbh, sbabic@denx.de
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*
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* (C) Copyright 2004
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* Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
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*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* Configuation settings for the LUBBOCK board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_CPU_PXA27X 1 /* This is an PXA27x CPU */
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#define CONFIG_MMC 1
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#define CONFIG_BOARD_LATE_INIT
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#define CONFIG_SYS_TEXT_BASE 0x0
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/* we will never enable dcache, because we have to setup MMU first */
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#define CONFIG_SYS_DCACHE_OFF
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#define RTC
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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/*
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* Hardware drivers
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*/
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/*
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* select serial console configuration
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*/
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#define CONFIG_PXA_SERIAL
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#define CONFIG_FFUART 1 /* we use FFUART on Conxs */
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#define CONFIG_BTUART 1 /* we use BTUART on Conxs */
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#define CONFIG_STUART 1 /* we use STUART on Conxs */
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#define CONFIG_CONS_INDEX 3
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 38400
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#define CONFIG_DOS_PARTITION 1
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_USB
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/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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#undef CONFIG_SHOW_BOOT_PROGRESS
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_SERVERIP 192.168.1.99
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#define CONFIG_BOOTCOMMAND "run boot_flash"
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#define CONFIG_BOOTARGS "console=ttyS0,38400 ramdisk_size=12288"\
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" rw root=/dev/ram initrd=0xa0800000,5m"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"program_boot_mmc=" \
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"mw.b 0xa0010000 0xff 0x20000; " \
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"if mmcinit && " \
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"fatload mmc 0 0xa0010000 u-boot.bin; " \
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"then " \
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"protect off 0x0 0x1ffff; " \
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"erase 0x0 0x1ffff; " \
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"cp.b 0xa0010000 0x0 0x20000; " \
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"fi\0" \
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"program_uzImage_mmc=" \
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"mw.b 0xa0010000 0xff 0x180000; " \
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"if mmcinit && " \
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"fatload mmc 0 0xa0010000 uzImage; " \
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"then " \
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"protect off 0x40000 0x1bffff; " \
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"erase 0x40000 0x1bffff; " \
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"cp.b 0xa0010000 0x40000 0x180000; " \
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"fi\0" \
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"program_ramdisk_mmc=" \
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"mw.b 0xa0010000 0xff 0x500000; " \
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"if mmcinit && " \
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"fatload mmc 0 0xa0010000 ramdisk.gz; " \
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"then " \
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"protect off 0x1c0000 0x6bffff; " \
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"erase 0x1c0000 0x6bffff; " \
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"cp.b 0xa0010000 0x1c0000 0x500000; " \
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"fi\0" \
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"boot_mmc=" \
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"if mmcinit && " \
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"fatload mmc 0 0xa0030000 uzImage && " \
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"fatload mmc 0 0xa0800000 ramdisk.gz; " \
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"then " \
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"bootm 0xa0030000; " \
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"fi\0" \
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"boot_flash=" \
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"cp.b 0x1c0000 0xa0800000 0x500000; " \
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"bootm 0x40000\0" \
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#define CONFIG_SETUP_MEMORY_TAGS 1
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#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
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/* #define CONFIG_INITRD_TAG 1 */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_HUSH_PARSER 1
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#undef CONFIG_SYS_PROMPT
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#ifdef CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
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#else
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#endif
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_DEVICE_NULLDEV 1
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#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */
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#define CONFIG_SYS_CPUSPEED 0x207 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
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#ifdef CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_PXA_MMC_GENERIC
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#define CONFIG_CMD_MMC
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#define CONFIG_SYS_MMC_BASE 0xF0000000
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#endif
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/*
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
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#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
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#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
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#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
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#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
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#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define CONFIG_SYS_DRAM_BASE 0xa0000000
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#define CONFIG_SYS_DRAM_SIZE 0x04000000
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
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/*
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* GPIO settings
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*/
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#define CONFIG_SYS_GPSR0_VAL 0x00018000
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#define CONFIG_SYS_GPSR1_VAL 0x00000000
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#define CONFIG_SYS_GPSR2_VAL 0x400dc000
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#define CONFIG_SYS_GPSR3_VAL 0x00000000
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#define CONFIG_SYS_GPCR0_VAL 0x00000000
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#define CONFIG_SYS_GPCR1_VAL 0x00000000
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#define CONFIG_SYS_GPCR2_VAL 0x00000000
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#define CONFIG_SYS_GPCR3_VAL 0x00000000
|
||||
#define CONFIG_SYS_GPDR0_VAL 0x00018000
|
||||
#define CONFIG_SYS_GPDR1_VAL 0x00028801
|
||||
#define CONFIG_SYS_GPDR2_VAL 0x520dc000
|
||||
#define CONFIG_SYS_GPDR3_VAL 0x0001E000
|
||||
#define CONFIG_SYS_GAFR0_L_VAL 0x801c0000
|
||||
#define CONFIG_SYS_GAFR0_U_VAL 0x00000013
|
||||
#define CONFIG_SYS_GAFR1_L_VAL 0x6990100A
|
||||
#define CONFIG_SYS_GAFR1_U_VAL 0x00000008
|
||||
#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000
|
||||
#define CONFIG_SYS_GAFR2_U_VAL 0x010900F2
|
||||
#define CONFIG_SYS_GAFR3_L_VAL 0x54000003
|
||||
#define CONFIG_SYS_GAFR3_U_VAL 0x00002401
|
||||
#define CONFIG_SYS_GRER0_VAL 0x00000000
|
||||
#define CONFIG_SYS_GRER1_VAL 0x00000000
|
||||
#define CONFIG_SYS_GRER2_VAL 0x00000000
|
||||
#define CONFIG_SYS_GRER3_VAL 0x00000000
|
||||
|
||||
#define CONFIG_SYS_GFER1_VAL 0x00000000
|
||||
#define CONFIG_SYS_GFER3_VAL 0x00000020
|
||||
|
||||
#if CONFIG_POLARIS
|
||||
#define CONFIG_SYS_GFER0_VAL 0x00000001
|
||||
#define CONFIG_SYS_GFER2_VAL 0x00200000
|
||||
#else
|
||||
#define CONFIG_SYS_GFER0_VAL 0x00000000
|
||||
#define CONFIG_SYS_GFER2_VAL 0x00000000
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */
|
||||
|
||||
/*
|
||||
* Clock settings
|
||||
*/
|
||||
#define CONFIG_SYS_CKEN 0x01FFFFFF /* CHECK */
|
||||
#define CONFIG_SYS_CCCR 0x02000290 /* 520Mhz */
|
||||
|
||||
/*
|
||||
* Memory settings
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_MSC0_VAL 0x4df84df0
|
||||
#define CONFIG_SYS_MSC1_VAL 0x7ff87ff4
|
||||
#if CONFIG_POLARIS
|
||||
#define CONFIG_SYS_MSC2_VAL 0xa2697ff8
|
||||
#else
|
||||
#define CONFIG_SYS_MSC2_VAL 0xa26936d4
|
||||
#endif
|
||||
#define CONFIG_SYS_MDCNFG_VAL 0x880009C9
|
||||
#define CONFIG_SYS_MDREFR_VAL 0x20ca201e
|
||||
#define CONFIG_SYS_MDMRS_VAL 0x00220022
|
||||
|
||||
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
|
||||
#define CONFIG_SYS_SXCNFG_VAL 0x40044004
|
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces
|
||||
*/
|
||||
#define CONFIG_SYS_MECR_VAL 0x00000001
|
||||
#define CONFIG_SYS_MCMEM0_VAL 0x00004204
|
||||
#define CONFIG_SYS_MCMEM1_VAL 0x00010204
|
||||
#define CONFIG_SYS_MCATT0_VAL 0x00010504
|
||||
#define CONFIG_SYS_MCATT1_VAL 0x00010504
|
||||
#define CONFIG_SYS_MCIO0_VAL 0x00008407
|
||||
#define CONFIG_SYS_MCIO1_VAL 0x0000c108
|
||||
|
||||
#define CONFIG_DRIVER_DM9000 1
|
||||
|
||||
#if CONFIG_POLARIS
|
||||
#define CONFIG_DM9000_BASE 0x0C800000
|
||||
#else
|
||||
#define CONFIG_DM9000_BASE 0x08000000
|
||||
#endif
|
||||
|
||||
#define DM9000_IO CONFIG_DM9000_BASE
|
||||
#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004)
|
||||
|
||||
#define CONFIG_USB_OHCI_NEW 1
|
||||
#define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "trizepsiv"
|
||||
#define CONFIG_USB_STORAGE 1
|
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
|
||||
|
||||
/*
|
||||
* FLASH and environment organization
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE 0
|
||||
#define CONFIG_SYS_MONITOR_LEN 0x40000
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */
|
||||
|
||||
/* timeout values are in ticks */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
|
||||
|
||||
/* write flash less slowly */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
|
||||
|
||||
/* Unlock to be used with Intel chips */
|
||||
#define CONFIG_SYS_FLASH_PROTECTION 1
|
||||
|
||||
/* Flash environment locations */
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */
|
||||
#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue