Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
This commit is contained in:
Wolfgang Denk
commit
f8b365ceb6
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@ -60,15 +60,18 @@ uchar env_get_char_spec(int index)
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void env_relocate_spec(void)
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{
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struct mtd_info *mtd = &onenand_mtd;
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#ifdef CONFIG_ENV_ADDR_FLEX
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struct onenand_chip *this = &onenand_chip;
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#endif
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loff_t env_addr;
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int use_default = 0;
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size_t retlen;
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env_addr = CONFIG_ENV_ADDR;
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#ifdef CONFIG_ENV_ADDR_FLEX
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if (FLEXONENAND(this))
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env_addr = CONFIG_ENV_ADDR_FLEX;
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#endif
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/* Check OneNAND exist */
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if (mtd->writesize)
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/* Ignore read fail */
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@ -94,7 +97,9 @@ void env_relocate_spec(void)
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int saveenv(void)
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{
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struct mtd_info *mtd = &onenand_mtd;
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#ifdef CONFIG_ENV_ADDR_FLEX
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struct onenand_chip *this = &onenand_chip;
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#endif
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loff_t env_addr = CONFIG_ENV_ADDR;
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struct erase_info instr = {
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.callback = NULL,
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@ -102,12 +107,14 @@ int saveenv(void)
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size_t retlen;
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instr.len = CONFIG_ENV_SIZE;
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#ifdef CONFIG_ENV_ADDR_FLEX
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if (FLEXONENAND(this)) {
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env_addr = CONFIG_ENV_ADDR_FLEX;
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instr.len = CONFIG_ENV_SIZE_FLEX;
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instr.len <<= onenand_mtd.eraseregions[0].numblocks == 1 ?
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1 : 0;
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}
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#endif
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instr.addr = env_addr;
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instr.mtd = mtd;
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if (mtd->erase(mtd, &instr)) {
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@ -59,14 +59,111 @@
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static emif_registers *const emif_regs = (void *) DAVINCI_ASYNC_EMIF_CNTRL_BASE;
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/*
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* Exploit the little endianness of the ARM to do multi-byte transfers
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* per device read. This can perform over twice as quickly as individual
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* byte transfers when buffer alignment is conducive.
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*
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* NOTE: This only works if the NAND is not connected to the 2 LSBs of
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* the address bus. On Davinci EVM platforms this has always been true.
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*/
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static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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struct nand_chip *chip = mtd->priv;
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const u32 *nand = chip->IO_ADDR_R;
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/* Make sure that buf is 32 bit aligned */
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if (((int)buf & 0x3) != 0) {
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if (((int)buf & 0x1) != 0) {
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if (len) {
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*buf = readb(nand);
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buf += 1;
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len--;
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}
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}
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if (((int)buf & 0x3) != 0) {
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if (len >= 2) {
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*(u16 *)buf = readw(nand);
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buf += 2;
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len -= 2;
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}
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}
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}
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/* copy aligned data */
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while (len >= 4) {
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*(u32 *)buf = readl(nand);
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buf += 4;
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len -= 4;
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}
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/* mop up any remaining bytes */
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if (len) {
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if (len >= 2) {
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*(u16 *)buf = readw(nand);
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buf += 2;
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len -= 2;
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}
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if (len)
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*buf = readb(nand);
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}
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}
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static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
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int len)
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{
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struct nand_chip *chip = mtd->priv;
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const u32 *nand = chip->IO_ADDR_W;
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/* Make sure that buf is 32 bit aligned */
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if (((int)buf & 0x3) != 0) {
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if (((int)buf & 0x1) != 0) {
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if (len) {
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writeb(*buf, nand);
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buf += 1;
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len--;
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}
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}
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if (((int)buf & 0x3) != 0) {
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if (len >= 2) {
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writew(*(u16 *)buf, nand);
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buf += 2;
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len -= 2;
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}
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}
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}
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/* copy aligned data */
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while (len >= 4) {
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writel(*(u32 *)buf, nand);
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buf += 4;
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len -= 4;
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}
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/* mop up any remaining bytes */
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if (len) {
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if (len >= 2) {
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writew(*(u16 *)buf, nand);
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buf += 2;
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len -= 2;
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}
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if (len)
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writeb(*buf, nand);
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}
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}
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static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
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IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
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if (ctrl & NAND_CTRL_CHANGE) {
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IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
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if ( ctrl & NAND_CLE )
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IO_ADDR_W |= MASK_CLE;
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if ( ctrl & NAND_ALE )
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@ -75,7 +172,7 @@ static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int c
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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writeb(cmd, IO_ADDR_W);
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}
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#ifdef CONFIG_SYS_NAND_HW_ECC
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@ -248,59 +345,55 @@ static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
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const uint8_t *dat,
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uint8_t *ecc_code)
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{
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unsigned int hw_4ecc[4] = { 0, 0, 0, 0 };
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unsigned int const1 = 0, const2 = 0;
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unsigned char count1 = 0;
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unsigned int hw_4ecc[4];
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unsigned int i;
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nand_davinci_4bit_readecc(mtd, hw_4ecc);
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/*Convert 10 bit ecc value to 8 bit */
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for (count1 = 0; count1 < 2; count1++) {
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const2 = count1 * 5;
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const1 = count1 * 2;
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for (i = 0; i < 2; i++) {
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unsigned int hw_ecc_low = hw_4ecc[i * 2];
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unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];
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/* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
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ecc_code[const2] = hw_4ecc[const1] & 0xFF;
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*ecc_code++ = hw_ecc_low & 0xFF;
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/*
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* Take 2 bits as LSB bits from val1 (count1=0) or val5
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* (count1=1) and 6 bits from val2 (count1=0) or
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* val5 (count1=1)
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*/
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ecc_code[const2 + 1] =
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((hw_4ecc[const1] >> 8) & 0x3) | ((hw_4ecc[const1] >> 14) &
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0xFC);
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*ecc_code++ =
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((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);
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/*
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* Take 4 bits from val2 (count1=0) or val5 (count1=1) and
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* 4 bits from val3 (count1=0) or val6 (count1=1)
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*/
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ecc_code[const2 + 2] =
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((hw_4ecc[const1] >> 22) & 0xF) |
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((hw_4ecc[const1 + 1] << 4) & 0xF0);
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*ecc_code++ =
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((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);
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/*
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* Take 6 bits from val3(count1=0) or val6 (count1=1) and
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* 2 bits from val4 (count1=0) or val7 (count1=1)
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*/
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ecc_code[const2 + 3] =
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((hw_4ecc[const1 + 1] >> 4) & 0x3F) |
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((hw_4ecc[const1 + 1] >> 10) & 0xC0);
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*ecc_code++ =
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((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);
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/* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
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ecc_code[const2 + 4] = (hw_4ecc[const1 + 1] >> 18) & 0xFF;
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*ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
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}
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return 0;
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}
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static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
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uint8_t *read_ecc, uint8_t *calc_ecc)
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{
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unsigned short ecc_10bit[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
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int i;
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unsigned int hw_4ecc[4] = { 0, 0, 0, 0 }, iserror = 0;
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unsigned short *pspare = NULL, *pspare1 = NULL;
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unsigned int hw_4ecc[4];
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unsigned int iserror;
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unsigned short *ecc16;
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unsigned int numerrors, erroraddress, errorvalue;
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u32 val;
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@ -317,44 +410,41 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
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return 0;
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/* Convert 8 bit in to 10 bit */
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pspare = (unsigned short *)&read_ecc[2];
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pspare1 = (unsigned short *)&read_ecc[0];
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/* Take 10 bits from 0th and 1st bytes */
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ecc_10bit[0] = (*pspare1) & 0x3FF;
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/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
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ecc_10bit[1] = (((*pspare1) >> 10) & 0x3F)
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| (((pspare[0]) << 6) & 0x3C0);
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/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
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ecc_10bit[2] = ((pspare[0]) >> 4) & 0x3FF;
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/*Take 2 bits from 3rd byte and 8 bits from 4th byte */
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ecc_10bit[3] = (((pspare[0]) >> 14) & 0x3)
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| ((((pspare[1])) << 2) & 0x3FC);
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/* Take 8 bits from 5th byte and 2 bits from 6th byte */
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ecc_10bit[4] = ((pspare[1]) >> 8)
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| ((((pspare[2])) << 8) & 0x300);
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/* Take 6 bits from 6th byte and 4 bits from 7th byte */
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ecc_10bit[5] = (pspare[2] >> 2) & 0x3FF;
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/* Take 4 bits from 7th byte and 6 bits from 8th byte */
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ecc_10bit[6] = (((pspare[2]) >> 12) & 0xF)
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| ((((pspare[3])) << 4) & 0x3F0);
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/*Take 2 bits from 8th byte and 8 bits from 9th byte */
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ecc_10bit[7] = ((pspare[3]) >> 6) & 0x3FF;
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ecc16 = (unsigned short *)&read_ecc[0];
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/*
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* Write the parity values in the NAND Flash 4-bit ECC Load register.
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* Write each parity value one at a time starting from 4bit_ecc_val8
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* to 4bit_ecc_val1.
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*/
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for (i = 7; i >= 0; i--)
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emif_regs->NAND4BITECCLOAD = ecc_10bit[i];
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/*Take 2 bits from 8th byte and 8 bits from 9th byte */
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writel(((ecc16[4]) >> 6) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
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/* Take 4 bits from 7th byte and 6 bits from 8th byte */
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writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
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&emif_regs->NAND4BITECCLOAD);
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/* Take 6 bits from 6th byte and 4 bits from 7th byte */
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writel((ecc16[3] >> 2) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
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/* Take 8 bits from 5th byte and 2 bits from 6th byte */
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writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
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&emif_regs->NAND4BITECCLOAD);
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/*Take 2 bits from 3rd byte and 8 bits from 4th byte */
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writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
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&emif_regs->NAND4BITECCLOAD);
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/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
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writel(((ecc16[1]) >> 4) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
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/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
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writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
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&emif_regs->NAND4BITECCLOAD);
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/* Take 10 bits from 0th and 1st bytes */
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writel((ecc16[0]) & 0x3FF, &emif_regs->NAND4BITECCLOAD);
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/*
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* Perform a dummy read to the EMIF Revision Code and Status register.
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@ -371,8 +461,7 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
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*/
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nand_davinci_4bit_readecc(mtd, hw_4ecc);
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if (hw_4ecc[0] == ECC_STATE_NO_ERR && hw_4ecc[1] == ECC_STATE_NO_ERR &&
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hw_4ecc[2] == ECC_STATE_NO_ERR && hw_4ecc[3] == ECC_STATE_NO_ERR)
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if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
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return 0;
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/*
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@ -519,6 +608,9 @@ void davinci_nand_init(struct nand_chip *nand)
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/* Set address of hardware control function */
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nand->cmd_ctrl = nand_davinci_hwcontrol;
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nand->read_buf = nand_davinci_read_buf;
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nand->write_buf = nand_davinci_write_buf;
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nand->dev_ready = nand_davinci_dev_ready;
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nand_flash_init();
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