x86: ivybridge: Move more init to the probe() function
Move SPI and port80 init to lpc_early_init(), called from the LPC's probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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@ -30,26 +30,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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DECLARE_GLOBAL_DATA_PTR;
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static void enable_port80_on_lpc(struct pci_controller *hose, pci_dev_t dev)
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{
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/* Enable port 80 POST on LPC */
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pci_hose_write_config_dword(hose, dev, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
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clrbits_le32(RCB_REG(GCS), 4);
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}
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/*
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* Enable Prefetching and Caching.
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*/
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static void enable_spi_prefetch(struct pci_controller *hose, pci_dev_t dev)
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{
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u8 reg8;
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pci_hose_read_config_byte(hose, dev, 0xdc, ®8);
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reg8 &= ~(3 << 2);
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reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
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pci_hose_write_config_byte(hose, dev, 0xdc, reg8);
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}
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static int set_flex_ratio_to_tdp_nominal(void)
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static int set_flex_ratio_to_tdp_nominal(void)
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{
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{
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msr_t flex_ratio, msr;
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msr_t flex_ratio, msr;
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@ -99,22 +79,6 @@ static int set_flex_ratio_to_tdp_nominal(void)
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return -EINVAL;
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return -EINVAL;
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}
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}
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static void set_spi_speed(void)
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{
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u32 fdod;
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/* Observe SPI Descriptor Component Section 0 */
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writel(0x1000, RCB_REG(SPI_DESC_COMP0));
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/* Extract the1 Write/Erase SPI Frequency from descriptor */
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fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
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fdod >>= 24;
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fdod &= 7;
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/* Set Software Sequence frequency to match */
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clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
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}
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int arch_cpu_init(void)
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int arch_cpu_init(void)
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{
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{
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post_code(POST_CPU_INIT);
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post_code(POST_CPU_INIT);
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@ -143,13 +107,6 @@ int arch_cpu_init_dm(void)
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if (!dev)
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if (!dev)
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return -ENODEV;
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return -ENODEV;
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enable_spi_prefetch(hose, PCH_LPC_DEV);
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/* This is already done in start.S, but let's do it in C */
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enable_port80_on_lpc(hose, PCH_LPC_DEV);
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set_spi_speed();
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/*
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/*
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* We should do as little as possible before the serial console is
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* We should do as little as possible before the serial console is
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* up. Perhaps this should move to later. Our next lot of init
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* up. Perhaps this should move to later. Our next lot of init
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@ -454,6 +454,42 @@ static void pch_fixups(pci_dev_t dev)
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setbits_le32(RCB_REG(0x21a8), 0x3);
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setbits_le32(RCB_REG(0x21a8), 0x3);
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}
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}
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/*
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* Enable Prefetching and Caching.
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*/
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static void enable_spi_prefetch(struct udevice *pch)
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{
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u8 reg8;
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dm_pci_read_config8(pch, 0xdc, ®8);
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reg8 &= ~(3 << 2);
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reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
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dm_pci_write_config8(pch, 0xdc, reg8);
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}
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static void enable_port80_on_lpc(struct udevice *pch)
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{
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/* Enable port 80 POST on LPC */
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dm_pci_write_config32(pch, PCH_RCBA_BASE, DEFAULT_RCBA | 1);
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clrbits_le32(RCB_REG(GCS), 4);
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}
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static void set_spi_speed(void)
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{
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u32 fdod;
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/* Observe SPI Descriptor Component Section 0 */
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writel(0x1000, RCB_REG(SPI_DESC_COMP0));
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/* Extract the1 Write/Erase SPI Frequency from descriptor */
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fdod = readl(RCB_REG(SPI_FREQ_WR_ERA));
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fdod >>= 24;
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fdod &= 7;
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/* Set Software Sequence frequency to match */
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clrsetbits_8(RCB_REG(SPI_FREQ_SWSEQ), 7, fdod);
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}
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/**
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/**
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* lpc_early_init() - set up LPC serial ports and other early things
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* lpc_early_init() - set up LPC serial ports and other early things
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*
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*
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@ -492,6 +528,13 @@ static int lpc_early_init(struct udevice *dev)
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dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg);
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dm_pci_write_config32(dev->parent, LPC_GENX_DEC(i), reg);
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}
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}
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enable_spi_prefetch(dev->parent);
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/* This is already done in start.S, but let's do it in C */
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enable_port80_on_lpc(dev->parent);
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set_spi_speed();
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return 0;
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return 0;
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}
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}
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