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Author	SHA1	Message	Date
Wolfgang Denk	1a4596601f	Add GPL-2.0+ SPDX-License-Identifier to source files Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>	2013-07-24 09:44:38 -04:00
Troy Kisky	fdf86c202c	ddr cfg: DRAM_RESET needs 0x00020030 The old value of 0x000e0030 will cause ethernet timeout issues on the sabrelite and possibly other boards using the KSZ9021. I have no explanation as to why. But this is a correct change, the TRM will be updated to show that 00b is the only valid setting for bits 19-18 of DRAM_RESET. My thanks go to Liu Hui(Jason) for this information. Acked-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>	2013-07-20 12:14:09 -04:00
Eric Nelson	d67b0d97b1	Add Boundary Devices Nitrogen6X boards Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>	2013-03-13 09:04:24 +01:00

Author

SHA1

Message

Date

Wolfgang Denk

1a4596601f

Add GPL-2.0+ SPDX-License-Identifier to source files

Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>

2013-07-24 09:44:38 -04:00

Troy Kisky

fdf86c202c

ddr cfg: DRAM_RESET needs 0x00020030

The old value of 0x000e0030 will cause ethernet
timeout issues on the sabrelite and possibly other
boards using the KSZ9021.
I have no explanation as to why.

But this is a correct change, the TRM will be updated
to show that 00b is the only valid setting for bits
19-18 of DRAM_RESET.

My thanks go to Liu Hui(Jason) for this information.

Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>

2013-07-20 12:14:09 -04:00

Eric Nelson

d67b0d97b1

Add Boundary Devices Nitrogen6X boards

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>

2013-03-13 09:04:24 +01:00

3 Commits