Commit graph

1484 commits

Author SHA1 Message Date
Simon Glass
374e78efb0 x86: Add support for the samus chromebook
This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.

Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard

Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).

The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:27 +08:00
Simon Glass
f21069ff8a x86: Update README for new developments
Update a few points which have become out-of-date.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
b24f5c4f27 x86: broadwell: Add a pinctrl driver
GPIO pins need to be set up on start-up. Add a driver to provide this,
configured from the device tree.

The binding is slightly different from the existing ICH6 binding, since that
is quite verbose. The new binding should be just as extensible.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:26 +08:00
Simon Glass
c13dcb3dc7 x86: dts: Update the pinctrl binding a little
Make a few minor updates to make the meaning clearer.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
7ac99be6e2 x86: Add an ICH6 pin configuration driver
Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.

The driver is not in the pinctrl uclass due to some oddities of the way x86
devices work:

- The GPIO controller is not present in I/O space until it is set up
- This is done by writing a register in the PCH
- The PCH has a driver which itself uses PCI, another driver
- The pinctrl uclass requires that a pinctrl device be available before any
other device can be probed

It would be possible to work around the limitations by:
- Hard-coding the GPIO address rather than reading it from the PCH
- Using special x86 PCI access to set the GPIO address in the PCH

However it is not clear that this is better, since the pin configuration
driver does not actually provide normal pin configuration services - it
simply sets up all the pins statically when probed. While this remains the
case, it seems better to use a syscon uclass instead. This can be probed
whenever it is needed, without any limitations.

Also add an 'invert' property to support inverting the input.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:25 +08:00
Simon Glass
e28fcb2279 x86: Add a script to aid code conversion from coreboot
It is useful to automate the process of converting code from coreboot a
little. Add a sed script which performs some common transformations.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-17 10:27:23 +08:00
Bin Meng
2e9ae222f1 x86: Document how to play with SeaBIOS
Boting SeaBIOS is done via U-Boot's bootelf command. Document this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-03-17 10:27:22 +08:00
Alexander Graf
996a18a714 efi_loader: Add README section in README.efi
To preserve all cover letter knowledge of the status on UEFI payload
support, let's add some sections to README.efi.

Signed-off-by: Alexander Graf <agraf@suse.de>

v3 -> v4:

  - Add section about config options
  - s/10kb/10KB/
2016-03-15 21:30:12 -04:00
Alexander Graf
7985cdf74b arm64: Remove non-full-va map code
By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.

To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.

Signed-off-by: Alexander Graf <agraf@suse.de>
2016-03-15 15:13:10 -04:00
Tom Rini
4d339a9e8a Merge branch 'master' of git://git.denx.de/u-boot-video 2016-03-15 08:01:17 -04:00
Simon Glass
722ebc8f84 mkimage: Support placing data outside the FIT
One limitation of FIT is that all the data is 'inline' within it, using a
'data' property in each image node. This means that to find out what is in
the FIT it is necessary to scan the entire file. Once loaded it can be
scanned and then the images can be copied to the correct place in memory.

In SPL it can take a significant amount of time to copy images around in
memory. Also loading data that does not end up being used is wasteful. It
would be useful if the FIT were small, acting as a directory, with the
actual data stored elsewhere.

This allows SPL to load the entire FIT, without the images, then load the
images it wants later.

Add a -E option to mkimage to request that it output an 'external' FIT.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-14 19:18:29 -04:00
Simon Glass
fb4cce0f98 mkimage: Support adding device tree files to a FIT
To make the auto-FIT feature useful we need to be able to provide a list of
device tree files on the command line for mkimage to add into the FIT. Add
support for this feature.

So far there is no support for hashing or verified boot using this method.
For those cases, a .its file must still be provided.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-14 19:18:29 -04:00
Simon Glass
8e35bb07eb mkimage: Support automatic creating of a FIT without a .its
At present, when generating a FIT, mkimage requires a .its file containing
the structure of the FIT and referring to the images to be included.

Creating the .its file is a separate step that makes it harder to use FIT.
This is not required for creating legacy images.

Often the FIT is pretty standard, consisting of an OS image, some device
tree files and a single configuration. We can handle this case automatically
and avoid needing a .its file at all.

To start with, support automatically generate the FIT using a new '-f auto'
option. Initially this only supports adding a single image (e.g. a linux
kernel) and a single configuration.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-14 19:18:28 -04:00
Simon Glass
3837ce65bd tools: Add a function to obtain the size of a file
This will be used in mkimage when working out the required size of the FIT
based on the files to be placed into it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-03-14 19:18:27 -04:00
Jacob Chen
c87c30e3ba doc: dt-bindings: Describe rockchip LVDS interface
I didn't have a common board to enable LVDS.
So add this dcocument to help others who want to enable LVDS in their board.

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-03-14 22:24:44 +01:00
Masahiro Yamada
c6c7eed741 ARM: uniphier: document how-to-build for Ace and Sanji boards
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-03-09 01:10:30 +09:00
Masahiro Yamada
fe7c95ee5c ARM: uniphier: merge two defconfig files
PH1-Pro5 support and ProXstream2/PH1-LD6b support can coexist in one
image and there is bit more room in SPL to accommodate all of them.
Merge uniphier_pro5_defconfig into uniphier_pxs2_defconfig.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
c231c4367a ARM: uniphier: add emmcupdate command
The Boot ROM expects the boot image (SPL) in the Boot Partition 1.
So, updating images involves the hardware partition switch.  It might
be a bit advanced for some users.

To be user-friendly, this commit adds a useful command to update the
images; just put SPL and U-Boot proper into the public directory of
the TFTP server and execute "run emmcupdate" from the command line.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:16 +09:00
Masahiro Yamada
a111bfbfad mmc: uniphier: add driver for UniPhier SD/MMC host controller
Add a driver for the on-chip SD/eMMC host controller used by
UniPhier SoC family.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-02-29 03:50:15 +09:00
Masahiro Yamada
b9a66b63b4 gpio: uniphier: add driver for UniPhier GPIO controller
This GPIO controller device is used on UniPhier SoCs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-02-29 03:50:15 +09:00
Michal Simek
508770ae37 dm: Remove ARM dcc from the list
Remove ARM Debug communication channel driver from the list
of not converted drivers to DM.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-02-24 18:44:14 -05:00
Bin Meng
03bfc78359 x86: doc: Update to include Intel Bayley Bay board instructions
Update existing documentation to mention Intel Bayley Bay board
instructions, an additional Bay Trail based board to MinnowMax.

This also adds a minor change to QEMU section to indicate clearly
the instructions are for bare mode.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-21 13:42:52 +08:00
Bin Meng
a2e3b05e16 x86: Add Intel Cougar Canyon 2 board
This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2016-02-21 13:42:52 +08:00
Vagrant Cascadian
7101c4ce8d Fix variable documented in README.distro for PXE address.
Fixes typo of pxe_addr_r with pxefile_addr_r.

Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
2016-02-15 12:04:45 -05:00
Masahiro Yamada
3cb9abc9c5 ARM: uniphier: update U-Boot file names in workflow
Since commit ad1ecd2063 ("fdt: Build a U-Boot binary without device
tree") and commit 03c25bcd26 ("fdt: Build an SPL binary without
device tree"), we can use shorter file names for the output images.

The default configuration for UniPhier SoCs enables CONFIG_OF_SEPARATE
and CONFIG_SPL_OF_CONTROL.  In this case, spl/u-boot-spl.bin is the
same as spl/u-boot-spl-dtb.bin.  Likewise, u-boot.img is the same as
as u-boot-dtb.img.  So, this change of the flow has no impact.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-14 16:36:13 +09:00
David Müller (ELSOFT AG)
0c2b6dffb7 doc: Remove any reference to CONFIG_MODEM_SUPPORT, CONFIG_CMD_HWFLOW, CONFIG_HWFLOW and friends from the documentation.
Signed-off-by: David Müller <d.mueller@elsoft.ch>
2016-02-08 10:24:17 -05:00
Simon Glass
92d05e50d9 dm: Update on current serial driver status
Update the README to reflect the current status.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-02-08 10:10:43 -05:00
Bin Meng
a187559e3d Use correct spelling of "U-Boot"
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
2016-02-06 12:00:59 +01:00
Ye Li
d4d1dd6749 mx6: soc: Add ENET2 mac address support
The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading
MAC address from fuse for ENET2.

Signed-off-by: Ye Li <ye.li@nxp.com>
2016-02-02 21:03:59 +01:00
Paul Thacker
9e160ee823 drivers: serial: add driver for Microchip PIC32 UART controller.
This adds PIC32 UART controller support based on driver model.

Signed-off-by: Paul Thacker <paul.thacker@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-02-01 22:14:00 +01:00
Purna Chandra Mandal
a0e7908326 drivers: clk: Add clock driver for Microchip PIC32 Microcontroller.
PIC32 clock module consists of multiple oscillators, PLLs, mutiplexers
and dividers capable of supplying clock to various controllers
on or off-chip.

Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2016-02-01 22:14:00 +01:00
Tom Rini
8a36287a01 Merge git://git.denx.de/u-boot-dm 2016-01-29 13:47:38 -05:00
Stephen Warren
986691fb97 distro bootcmd: enumerate PCI before network operations
The PCI bus must be enumerated before PCI devices, such as Ethernet
devices, are known to U-Boot. Enhance the distro boot commands to perform
PCI enumeration when needed.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-28 21:01:23 -07:00
Stephen Warren
3483b75d94 distro bootcmd: make net boot only optionally start USB
Currently, the distro boot commands always enumerate USB devices before
performing network operations. However, depending on the board and end-
user configuration, network devices may not be attached to USB, and so
enumerating USB may not be necessary. Enhance the scripts to make this
step optional, so that the user can decrease boot time if they don't
need USB.

This change is performed by moving the "usb start" invocation into a
standalone variable. If the user desires, they can replace that
variable's value with some no-op command such as "true" instead.

Booting from a USB storage device always needs to enumerate USB devices,
so this action is still hard-coded.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-28 21:01:23 -07:00
Tom Rini
82d72a1b99 Merge branch 'master' of git://git.denx.de/u-boot-net 2016-01-28 18:42:10 -05:00
Dinh Nguyen
c16e69f702 net: phy: micrel: add documentation for Micrel KSZ90x1 binding
Add the DTS documentation for the Micrel KSZ90x1 binding.

The original document was from:
[commit 4b405efbe12de28b26289282b431323d73992381 from the Linux kernel]

This takes the original document and adds a clarification on how the skew
values are represented in the code.

References:

Micrel ksz9021rl/rn Data Sheet, Revision 1.2. Dated 2/13/2014.
http://www.micrel.com/_PDF/Ethernet/datasheets/ksz9021rl-rn_ds.pdf

Micrel ksz9031rnx Data Sheet, Revision 2.1. Dated 11/20/2014.
http://www.micrel.com/_PDF/Ethernet/datasheets/KSZ9031RNX.pdf

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 13:20:29 -06:00
Bin Meng
a1c76c1508 net: tsec: Use priv->tbiaddr to initialize TBI PHY address
Add a new member 'tbiaddr' to tsec_private struct. For non-DM driver,
it is initialized as CONFIG_SYS_TBIPA_VALUE, but for DM driver, we
can get this from device tree. Update the bindings doc as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:23:19 -06:00
Bin Meng
69a00875e3 doc: dt-bindings: Describe Freescale TSEC ethernet controller
Adapted from the same file name in the kernel device tree bindings
documentation, to use with U-Boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:23:10 -06:00
Codrin Ciubotariu
aae0e68909 drivers: net: vsc9953: Add LAG support
You can now configure LAG on VSC9953's ports using the command:
ethsw [port <port_no>] aggr {[help] | show | <lag_group_no>}

A port must belong to a single LAG. By default, a port
belongs to a LAG equal to the port's number.

For each frame, a hash will be calculated based on
Source/Destination MAC addresses, Source/Destination IP(v4/v6)
addresses, Source/Destination ports. This hash will be used to
select a single egress port from LAG. This also assures
that frames from the same flow will always have the
same egress port.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:22:19 -06:00
Codrin Ciubotariu
3507cf7f4a doc: t1040-l2switch: Update README
The driver for VSC9953 L2 switch IP supports many features and
the documentation needs to be updated.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2016-01-28 12:22:11 -06:00
Tom Rini
4b5a4a0535 Merge branch 'master' of git://git.denx.de/u-boot-x86 2016-01-28 10:07:22 -05:00
Stefan Roese
d521197d69 x86: baytrail: Add option to disable the internal UART to setup_early_uart()
This patch adds a parameter to the function setup_early_uart() to either
enable or disable the internal BayTrail legacy UART. Since the name
setup_early_uart() does not match its functionality any more, lets
rename it to setup_internal_uart() as well in this patch.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-28 13:53:30 +08:00
Stefan Roese
9b5dbe1358 x86: baytrail: Add documentation for FSP memory-down values
This patch adds the documentation for the memory-down parameters
of the Intel FSP. To configure a board without SPD DDR DIMM but
with onboard DDR chips. The values are taken from the coreboot
header:

	src/soc/intel/fsp_baytrail/chip.h

(git ID da1a70ea from 2016-01-16 as reference).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Andrew Bradford <andrew.bradford@kodakalaris.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-28 13:53:29 +08:00
Michal Simek
93768393d7 serial: uartlite: Move driver to DM
Enable SPL DM too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
2016-01-27 15:55:49 +01:00
Thomas Chou
75219d57ef ns16550: replace with binding files from Linux kernel
Replace ns16550.txt with binding files from Linux kernel. As suggested
by Stephen Warren, we should keep the directory structure, filenames,
and file content identical to the bindings in the Linux kernel.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-25 10:40:03 -05:00
Simon Glass
f138713073 rockchip: Update the README
GPIO, I2C, LCD and HDMI are now implemented. We have more than one PMIC.
There is an implementation to run the CPU at full speed although it does
not seem to make much difference.

Update the README to cover recent developments.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
7c1058fadc rockchip: Add support for Raxda Rock 2
This board includes an RK3288 SoC on a SOM. It can be mounted on a
base-board which provides a wide range of peripherals.

So far this is verified to boot to a prompt from a microSD card. The serial
console works as well as HDMI.

Thanks to Tom Cubie for sending me a board.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
002c634c1f rockchip: Add a script to parse datasheets
This script has proved useful for parsing datasheets and creating register
shift/mask values for use in header files. Include it in case it is useful
for others.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:37 -07:00
Simon Glass
61101e0583 dts: Bring in pinctrl device tree binding
Add this binding file since we now use it in U-Boot.

Signed-off-by: Simon Glass <sjg@chromium.org>
2016-01-21 20:42:34 -07:00
Bin Meng
fdbae099bf serial: lpuart: Add driver model serial support
This adds driver model support to lpuart serial driver.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Tested-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
2016-01-20 19:10:14 -07:00