Commit graph

2429 commits

Author SHA1 Message Date
Matthias Fuchs
ced5b90290 [PATCH] 4xx: allow CONFIG_I2C_CMD_TREE without CONFIG_I2C_MULTI_BUS
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2007-03-08 22:17:04 +01:00
Matthias Fuchs
d8a8ea5c47 [PATCH] I2C: Add missing default CFG_SPD_BUS_NUM
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2007-03-08 22:16:00 +01:00
Matthias Fuchs
f9fc6a5852 fixed ethernet phy configuration for plu405 board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
2007-03-08 22:14:47 +01:00
Wolfgang Denk
769104c935 Minor cleanup 2007-03-08 21:49:27 +01:00
Wolfgang Denk
dd0321f5f8 Merge with /home/hs/jupiter/u-boot 2007-03-08 21:45:04 +01:00
Wolfgang Denk
efa013df33 Merge with /home/git/u-boot 2007-03-08 11:41:19 +01:00
Wolfgang Denk
35ded29fd9 Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx 2007-03-08 11:38:58 +01:00
Wolfgang Denk
d8be57669b Merge with /home/git/u-boot 2007-03-08 11:34:24 +01:00
Stefan Roese
cd84528f20 Merge with /home/stefan/git/u-boot/yucca-ddr2 2007-03-08 10:32:45 +01:00
Stefan Roese
00cdb4ce5e [PATCH] Update AMCC Luan 440SP eval board support
The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR
inititializition. This includes DDR auto calibration and support
for different DIMM modules, instead of the fixed setup used in
the earlier version.

This patch also enables the cache in FLASH for the startup
phase of U-Boot (while running from FLASH). After relocating to
SDRAM the cache is disabled again. This will speed up the boot
process, especially the SDRAM setup, since there are some loops
for memory testing (auto calibration).

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-08 10:13:16 +01:00
Stefan Roese
2f5df47351 [PATCH] Update AMCC Yucca 440SPe eval board support
The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR
inititializition. This includes DDR auto calibration and support
for different DIMM modules, instead of the fixed setup used in
the earlier version.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-08 10:10:18 +01:00
Stefan Roese
2721a68a9e ppc4xx: Small AMCC Katmai 440SPe update
Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-08 10:07:18 +01:00
Stefan Roese
df29449747 ppc4xx: Update 440SP/440SPe DDR SPD setup code to support 440SP
Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-08 10:06:09 +01:00
Ed Swarthout
83853178bd net - Support ping reply when processing net-loop
Add ICMP_ECHO_REQUEST packet support by responding with a ICMP_ECHO_REPLY.

This permits the ping command to test the phy interface when the phy
is put in loopback mode (typically by setting register 0 bit 14).

It also allows the port to respond to an external ping when u-boot is
processing some other net command (such as tftp).  This is useful when
tftp appears to hang.

Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
Signed-off-by: Ben Warren <bwarren@qstreams.com>
2007-03-07 18:12:15 -05:00
Wolfgang Denk
46270c2851 Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx 2007-03-07 16:50:34 +01:00
Stefan Roese
fa1aef15bc [PATCH] Use dynamic SDRAM TLB setup on AMCC Ocotea eval board
Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the
DDR memory are dynamically programmed matching the total size
of the equipped memory (DIMM modules).

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-07 16:43:00 +01:00
Stefan Roese
e2ebe69681 [PATCH] Fix AMCC 44x SPD SDRAM init code to support 2 DIMM's
This patch fixes a problem that occurs when 2 DIMM's are
used. This problem was first spotted and fixed by Gerald Jackson
<gerald.jackson@reaonixsecurity.com> but this patch fixes the
problem in a little more clever way.

This patch also adds the nice functionality to dynamically
create the TLB entries for the SDRAM (tlb.c). So we should
never run into such problems with wrong (too short) TLB
initialization again on these platforms.

As this feature is new to the "old" 44x SPD DDR driver, it
has to be enabled via the CONFIG_PROG_SDRAM_TLB define.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-07 16:39:36 +01:00
Wolfgang Denk
3921843398 UC101: fix compiler warnings 2007-03-07 16:33:44 +01:00
Wolfgang Denk
8d7e273222 HMI1001: fix build error, cleanup compiler warnings. 2007-03-07 16:19:46 +01:00
Wolfgang Denk
ad5bb451ad Restructure POST directory to support of other CPUs, boards, etc. 2007-03-06 18:08:43 +01:00
Wolfgang Denk
a5284efd12 Fix HOSTARCH handling.
Patch by Mike Frysinger, Mar 05 2007
2007-03-06 18:01:47 +01:00
Stefan Roese
07b7b0037a [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setup
As provided by the AMCC applications team, this patch optimizes the
DDR2 setup for 166MHz bus speed. The values provided are also save
to use on a "normal" 133MHz PLB bus system. Only the refresh counter
setup has to be adjusted as done in this patch.

For this the NAND booting version had to include the "speed.c" file
from the cpu/ppc4xx directory. With this addition the NAND SPL image
will just fit into the 4kbytes of program space. gcc version 4.x as
provided with ELDK 4.x is needed to generate this optimized code.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-06 07:47:04 +01:00
Wolfgang Denk
647d3c3eed Some code cleanup. 2007-03-04 01:36:05 +01:00
Wolfgang Denk
b24444f1b3 Merge with http://opensource.freescale.com/pub/scm/u-boot-7448hpc2.git 2007-03-04 01:17:20 +01:00
Kim Phillips
781e026c8a mpc83xx: fix implicit declaration of function 'ft_get_prop' warnings
(cherry picked from c5bf13b02284c3204a723566a9bab700e5059659 commit)
2007-03-02 14:08:26 -06:00
Kumar Gala
4feab4de7b mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode
The config value for:
* CFG_ACR_PIPE_DEP
* CFG_ACR_RPTCNT
* CFG_SPCR_TSEC1EP
* CFG_SPCR_TSEC2EP
* CFG_SCCR_TSEC1CM
* CFG_SCCR_TSEC2CM

Were not being used when setting the appropriate register

Added:
* CFG_SCCR_USBMPHCM
* CFG_SCCR_USBDRCM
* CFG_SCCR_PCICM
* CFG_SCCR_ENCCM

To allow full config of the SCCR.

Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349
that were just bogus.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-03-02 14:08:26 -06:00
Kim Phillips
d51b3cf371 mpc83xx: update [local-]mac-address properties on UEC based devices
8360 and 832x weren't updating their [local-]mac-address
properties. This patch fixes that.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2007-03-02 11:05:54 -06:00
Timur Tabi
61f4f912ac mpc83xx: write MAC address to mac-address and local-mac-address
Some device trees have a mac-address property, some have local-mac-address,
and some have both.  To support all of these device trees, this patch
updates ftp_cpu_setup() to write the MAC address to mac-address if it exists.
This function already updates local-mac-address.

Signed-off-by: Timur Tabi <timur@freescale.com>
2007-03-02 11:05:54 -06:00
Kim Phillips
22d71a71f5 mpc83xx: add command line editing by default 2007-03-02 11:05:54 -06:00
Kim Phillips
3fc0bd1591 mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers
Disable G1TXCLK, G2TXCLK h/w buffers. This patch
fixes a networking timeout issue with MPC8360EA (Rev.2) PBs.

Verified on Rev. 1.1, Rev. 1.2, and Rev. 2.0 boards.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Emilian Medve <Emilian.Medve@freescale.com>
2007-03-02 11:05:54 -06:00
Xie Xiaobo
d61853cf24 mpc83xx: Add DDR2 controller fixed/SPD Init for MPC83xx
The code supply fixed and SPD initialization for MPC83xx DDR2 Controller.
it pass DDR/DDR2 compliance tests.

Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
2007-03-02 11:05:54 -06:00
Xie Xiaobo
b110f40bd1 mpc83xx: Add the cpu specific code for MPC8360E rev2.0 MDS
MPC8360E rev2.0 have new spridr,and PVR value,
The MDS board for MPC8360E rev2.0 has 32M bytes Flash and 256M DDR2 DIMM.

Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
2007-03-02 11:05:54 -06:00
Xie Xiaobo
8d172c0f0d mpc83xx: Add the cpu and board specific code for MPC8349E rev3.1 MDS
MPC8349E rev3.1 have new spridr,and PVR value,
The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM.

Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>
2007-03-02 11:05:54 -06:00
Joakim Tjernlund
f6f5f709e5 mpc83xx: Fix empty i2c reads/writes in fsl_i2c.c
Fix empty i2c reads/writes, i2c_write(0x50, 0x00, 0, NULL, 0)
which is used to se if an slave will ACK after receiving its address.

Correct i2c probing to use this method as the old method could upset
a slave as it wrote a data byte to it.

Add a small delay in i2c_init() to let the controller
shutdown any ongoing I2C activity.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
2007-03-02 11:05:54 -06:00
Timur Tabi
7a78f148d6 mpc83xx: Add support for the MPC8349E-mITX-GP
Add support for the MPC8349E-mITX-GP, a stripped-down version of the
MPC8349E-mITX.  Bonus features include support for low-boot (BMS bit in
HRCW is 0) for the ITX and a README for the ITX and the ITX-GP.

Signed-off-by: Timur Tabi <timur@freescale.com>
2007-03-02 11:05:54 -06:00
Timur Tabi
fab16807ad mpc83xx: Delete sdram_init() for MPC8349E-mITX
There is no SDRAM on any of the 8349 ITX variants, so function sdram_init()
never does anything.  This patch deletes it.

Signed-off-by: Timur Tabi <timur@freescale.com>
2007-03-02 11:05:54 -06:00
Dave Liu
a87c856eb4 mpc83xx: Fix the LAW1/3 bug
The patch solves the alignment problem of the local bus access windows to
render accessible the memory bank and PHY registers of UPC 1 (starting at
0xf801 0000). What we actually did was to adjust the sizes of the bus
access windows so that the base address alignment requirement would be met.

Signed-off-by: Chereji Marian <marian.chereji@freescale.com>
Signed-off-by: Gridish Shlomi <gridish@freescale.com>
Signed-off-by: Dave Liu <daveliu@freescale.com>
2007-03-02 11:05:54 -06:00
Kim Phillips
97c4b397dc mpc83xx: don't hang if watchdog configured on 8360, 832x
don't hang if watchdog configured on 8360, 832x

The watchdog programming model is the same across all 83xx devices;
make the code reflect that.
2007-03-02 11:05:53 -06:00
Kim Phillips
b700474785 mpc83xx: protect memcpy to bad address if a local-mac-address is missing from dt
protect memcpy to bad address if a local-mac-address is missing from dt
2007-03-02 11:05:53 -06:00
Kim Phillips
6752ed088c mpc83xx: make 8360 default environment fdt be 8360 (not 8349)
make 8360 default environment fdt be 8360 (not 8349)
2007-03-02 11:05:53 -06:00
Emilian Medve
a28899c910 mpc83xx: Fix alternating tx error / tx buffer not ready bug in QE UEC
The problem is not gcc4 but the code itself. The BD_STATUS() macro can't
be used for busy-waiting since it strips the 'volatile' property from
the bd variable. gcc3 was working by pure luck.

This is a follow on patch to "Fix the UEC driver bug of QE"
2007-03-02 11:05:53 -06:00
Kumar Gala
3e78a31cfe mpc83xx: Replace CONFIG_MPC8349 and use CONFIG_MPC834X instead
The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all
MPC834X class processors.  Change the protections from CONFIG_MPC8349 to
CONFIG_MPC834X so they are more generic.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-03-02 11:05:53 -06:00
Kim Phillips
ae246dc6c1 mpc83xx: add MPC832XEMDS and sbc8349 to MAKEALL 2007-03-02 11:05:53 -06:00
Kim Phillips
4decd84e8f mpc83xx: sort Makefile targets
reordered targets alphabetically
2007-03-02 11:05:53 -06:00
Paul Gortmaker
91e2576977 mpc83xx: U-Boot support for Wind River SBC8349
I've redone the SBC8349 support to match git-current, which
incorporates all the MPC834x updates from Freescale since the 1.1.6
release,  including the DDR changes.

I've kept all the SBC8349 files as parallel as possible to the
MPC8349EMDS ones for ease of maintenance and to allow for easy
inspection of what was changed to support this board.  Hence the SBC8349
U-Boot has FDT support and everything else that the MPC8349EMDS has.

Fortunately the Freescale updates added support for boards using CS0,
but I had to change spd_sdram.c to allow for board specific settings for
the sdram_clk_cntl (it is/was hard coded to zero, and that remains the
default if the board doesn't specify a value.)

Hopefully this should be mergeable as-is and require no whitespace
cleanups or similar, but if something doesn't measure up then let me
know and I'll fix it.

Thanks,
Paul.
2007-03-02 11:05:53 -06:00
Sam Song
05031db456 mpc83xx: Remove a redundant semicolon in mpc8349itx.c
A redundant semicolon existed in mpc8349itx.c
should be removed.

Signed-off-by: Sam Song <samsongshu@yahoo.com.cn>
2007-03-02 11:05:53 -06:00
Jerry Van Baren
f35f358241 mpc83xx: Put the version (and magic) after the HRCW.
Put the version (and magic) after the HRCW.  This puts it in a fixed
location in flash, not at the start of flash but as close as we can get.

Signed-off-by: Jerry Van Baren <vanbaren@cideas.com>
2007-03-02 11:05:53 -06:00
Dave Liu
48aecd9691 mpc83xx: Add the MPC832XEMDS board readme
Add the MPC832XEMDS board readme

Signed-off-by: Dave Liu <daveliu@freescale.com>
2007-03-02 11:05:53 -06:00
Dave Liu
24c3aca3f1 mpc83xx: Add support for the MPC832XEMDS board
This patch supports DUART, ETH3/4 and PCI etc.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2007-03-02 11:05:53 -06:00
Dave Liu
e080313c32 mpc83xx: streamline the 83xx immr head file
For better format and style, I streamlined the 83xx head files,
including immap_83xx.h and mpc83xx.h. In the old head files, 1)
duplicated macro definition appear in the both files; 2) the structure
of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The
macro definition put inside the each structure. So, I cleaned up the
structure of QE immr from immap_83xx.h, deleted the duplicated stuff and
moved the macro definition to mpc83xx.h, Just like MPC8260.

CHANGELOG

*streamline the 83xx immr head file

Signed-off-by: Dave Liu <daveliu@freescale.com>
2007-03-02 11:05:53 -06:00