Commit graph

69 commits

Author SHA1 Message Date
Dave Mitchell
b14ca4b61a ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRs
Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and
L2 cache DCRs from ppc440.h to this new header.

Also converted these DCR defines from lowercase to uppercase and
modified referencing modules to use them.

Signed-off-by: Dave Mitchell <dmitch71@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-11-21 10:52:33 +01:00
Steven A. Falco
711e2b2af8 ppc4xx: Delete unused definitions for SDR0_DDRCFG from ppc4xx.h
The definitions of bits in SDR_CFG are incorrect, and not used within
U-Boot.  Therefore, they can be removed.

The naming of the sdr_ddrdl/sdr_cfg registers do not follow conventions,
and are unused, so they can be removed too.

A definition for SDR0_DDRCFG is added.

Signed-off-by: Steven A. Falco <sfalco@harris.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-11-21 10:52:09 +01:00
Adam Graham
f09f09d389 ppc4xx: Add AMCC Arches board support (dual 460GT)
The Arches Evaluation board is based on the AMCC 460GT SoC chip.
This board is a dual processor board with each processor providing
independent resources for Rapid IO, Gigabit Ethernet, and serial
communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR
FLASH, UART, EEPROM and temperature sensor, along with a shared debug
port. The two 460GT's will communicate with each other via shared
memory, Gigabit Ethernet and x1 PCI-Express.

Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Victor Gallardo <vgallardo@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:34:46 +02:00
Jean-Christophe PLAGNIOL-VILLARD
6d0f6bcf33 rename CFG_ macros to CONFIG_SYS
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
2008-10-18 21:54:03 +02:00
Adam Graham
f6b6c45840 ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routines
Signed-off-by: Adam Graham <agraham@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-09-05 12:04:16 +02:00
Prodyut Hazarika
079589bcfb ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,
PPC405EX and PPC460EX/GT/SX

- Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX
  processors
- Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared
  across processors (405 and 440/460)
- Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX
  processors
- Add register bit definitions for Memory Queue Configuration registers

Signed-off-by: Prodyut Hazarika <phazarika@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-08-21 10:31:16 +02:00
Stefan Roese
26173fc6f6 ppc4xx: Continue cleanup of ppc440.h
This patch continues the ppc440.h cleanup by removing some of the unused
defines.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:14 +02:00
Stefan Roese
d1631fe1a0 ppc4xx: Consolidate PPC4xx UIC defines
This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.

Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.

Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:14 +02:00
Stefan Roese
7ee2619c20 ppc4xx: Consolidate PPC4xx EBC defines
This patch removes all EBC related defines from the PPC4xx headers
ppc405.h and ppc440.h and introduces a new header

include/asm-ppc/ppc4xx-ebc.h

with all those defines.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:13 +02:00
Feng Kan
96e5fc0e6a ppc4xx: Add initial 460SX reference board (redwood) config file and defines.
Signed-off-by: Feng Kan <fkan@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-07-11 13:18:12 +02:00
Stefan Roese
745d8a0d3c ppc4xx: Fix 460EX errata with CPU lockup upon high AHB traffic
This patch implements a fix provided by AMCC so that the lockup upon
simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur
anymore:

Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2]
(bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG,
USB 2.0 host and SATA.

This errata is not officially available yet. I'll update the comment
to add the errata number later.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-30 15:20:41 +02:00
Stefan Roese
36ea16f6a0 ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1
This patch removes all SDRAM related defines from the PPC4xx headers
ppc405.h and ppc440.h. This is needed since now some 405 PPC's use
the same SDRAM controller as 440 systems do (like 405EX and 440SP).

It also introduces new defines for the equipped SDRAM controller based on
which PPC variant is used. There new defines are:

used on 405GR/CR/EP and some Xilinx Virtex boards.

used on 440GP/GX/EP/GR.

used on 440EPx/GRx.

used on 405EX/r/440SP/SPe/460EX/GT.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-06-03 20:21:53 +02:00
Wolfgang Denk
53677ef18e Big white-space cleanup.
This commit gets rid of a huge amount of silly white-space issues.
Especially, all sequences of SPACEs followed by TAB characters get
removed (unless they appear in print statements).

Also remove all embedded "vim:" and "vi:" statements which hide
indentation problems.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-05-21 00:14:08 +02:00
Yuri Tikhonov
eb0615bf60 lwmon5: watchdog POST fix
Use the GPT0_MASKx registers as the temporary storage for watch-dog
timer POST test instead of GPT0_COMPx. The latter
(GPT0_COMP1..GPT0_COMP5) are used for the log-buffer header.

Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
2008-04-25 11:35:32 +02:00
Eugene O'Brien
5b2052e5f5 ppc4xx: Fix power mgt definitions for PPC440
Corrected DCR addresses of PPC440EP power management registers.

Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com>
2008-04-11 16:27:58 +02:00
Stefan Roese
4c9e855734 ppc4xx: Add AMCC Glacier 406GT eval board support
This patch adds support for the AMCC Glacier 460GT eval board.
The main difference to the Canyonlands board are listed here:

- 4 ethernet ports instead of 2
- no SATA port
- no USB port

Currently EMAC2+3 are not working. This will be fixed in a later
release.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-27 09:54:41 +01:00
Yuri Tikhonov
3d61018643 The patch introduces the alternative configuration of the log buffer for the lwmon5 board: the storage for the log-buffer itself is OCM(on-chip memory), the log-buffer header is moved to six GPT registers (PPC440EPX_GPT0_COMP1, ..., PPC440EPX_GPT0_COMP5).
To enable this, alternative, configuration the U-Boot board configuration
file for lwmon5 includes the definitions of alternative addresses for header
(CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR).

 The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set,
and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the
lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h).

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
2008-03-18 22:24:48 +01:00
Yuri Tikhonov
8f15d4addd The patch adds new POST tests for the Lwmon5 board. These are:
* External Watchdog test;
* dsPIC tests;
* FPGA test;
* GDC test;
* Sysmon tests.

Signed-off-by: Dmitry Rakhchev <rda@emcraft.com>
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
2008-03-18 22:24:47 +01:00
Stefan Roese
41712b4e8c ppc4xx: Add USB OHCI support to AMCC Canyonlands 460EX eval board
This patch adds USB OHCI support to the Canyonlands board port. It also
enables EXT2 support.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:05 +01:00
Stefan Roese
43c60992cd ppc4xx: Add basic support for AMCC 460EX/460GT (5/5)
This patch adds basic support for the AMCC 460EX/460GT PPC's.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-03-15 07:28:04 +01:00
Stefan Roese
1466ef8db5 Merge branch 'lwmon5-no-ocm' 2008-01-09 10:43:47 +01:00
Stefan Roese
8f24e0637a ppc4xx: Change LWMON5 to not use OCM for init-ram and POST anymore
This patch configures the LWMON5 port to use d-cache as init-ram and
the unused GPT0_COMP6 as POST WORD storage.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-09 10:28:20 +01:00
Stefan Roese
845c6c95db ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setup
On Katmai the complete auto-calibration somehow doesn't seem to
produce the best results, meaning optimal values for RQFD/RFFD.
This was discovered by GDA using a high bandwidth scope,
analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
so now on Katmai "only" RFFD is auto-calibrated.

This patch also adds RDCC calibration as mentioned on page 7 of
the AMCC PowerPC440SP/SPe DDR2 application note:
"DDR1/DDR2 Initialization Sequence and Dynamic Tuning"

Signed-off-by: Stefan Roese <sr@denx.de>
2008-01-05 09:12:41 +01:00
Larry Johnson
c46f53333b Add definitions for 440EPx/GRx SDRAM controller to ppc440.h
This patch adds the Denali SDRAM controller definitions to "ppc440.h".
It also fixes two typos in the definitions, so the board-specific
"sdram.h" files containing these definitions are also fixed to avoid
compiler warnings.

Signed-off-by: Larry Johnson <lrj@acm.org>
2007-12-27 19:35:36 +01:00
Stefan Roese
a27044b14a ppc4xx: Enable hardware-fix for PCI/DMA errata on AMCC 440SP/SPe boards
This patch enables the hardware-fix for the PCI/DMA errata's 19+22 by
setting the FIXD bit in the SDR0_MFR register. Here a description of the
symptoms:

Problem Description
------------------------------
If a DMA is performed between memory and PCI with the DMA 1 Controller
using prefetch, and as a result uses a special purpose buffer selected by
the PCIXn Bridge Options 1 Register (PCIXn_BRDGOPT1[RBP7] - bits 31-29),
the first part of the transfer sequence is performed twice. The
PPC440SPe PCI Controller requests more data than was needed such that in
the case of enforce memory protection, a host CPU  exception can occur.
No data is corrupted, because data transfer is stopped in the PCI
Controller. Prefetch enable is specified by setting DMA Configuration
Register (I2O0_DMAx_CFG[DXEPD] - bit 31) to 0.

Behavior that may be observed in a running system
---------------------------------------------------------------------------

1. DMA performance is decreased because of the double access on the PCI bus
interface.
2. If an illegal access to some address on the PCI bus is detected at the
system level, a machine check or similar system error may occur.

Workarounds Available
----------------------------------

1. Do not program prefetch. Note that a prefetch command cannot be programmed
without selecting a special purpose buffer.
2. To avoid crossing a physical boundary of the PCI slave device, add 512
bytes of address to the PCI address range.

This patch was originally provided by Pravin M. Bathija <pbathija@amcc.com>
from AMCC and slighly changed.

Signed-off-by: Pravin M. Bathija <pbathija@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-12-06 05:58:43 +01:00
Stefan Roese
aee747f19b ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platforms
- Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE
- Cleanup of the 4xx GPIO functions
- Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h

Signed-off-by: Stefan Roese <sr@denx.de>
2007-11-15 14:23:55 +01:00
Stefan Roese
9b94ac61d2 ppc4xx: Rework 4xx cache support
New cache handling functions added and all existing functions
moved from start.S into seperate cache.S.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:21:46 +01:00
Stefan Roese
087dfdb79b ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xx
This patch moves some common 4xx macros and the PPC405_SYS_INFO/
PPC440_SYS_INFO structure into the common ppc4xx.h header.

Lot's of other macros are good candidates to be consolidated this way
in the future.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:50 +01:00
Stefan Roese
dbbd125721 ppc4xx: Add PPC405EX support
Signed-off-by: Stefan Roese <sr@denx.de>
2007-10-31 21:20:49 +01:00
Stefan Roese
ea9f6bce38 ppc4xx: Update 440EPx lwmon5 board support
- Clear ECC status regs after ECC POST test
- Set dcbz for ECC generation with caches enabled as default
- Code cleanup

Signed-off-by: Stefan Roese <sr@denx.de>
2007-07-31 08:37:01 +02:00
Sergei Poselenov
b44896215a Merged POST framework with the current TOT.
Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
2007-07-05 08:17:37 +02:00
Niklaus Giger
f780b83316 resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPX
Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
2007-07-04 10:14:07 +02:00
Wolfgang Denk
1636d1c852 Coding stylke cleanup; rebuild CHANGELOG 2007-06-22 23:59:00 +02:00
Igor Lisitsin
a11e06965e Extend POST support for PPC440
Added memory, CPU, UART, I2C and SPR POST tests for PPC440.

Signed-off-by: Igor Lisitsin <igor@emcraft.com>
--
2007-06-22 23:21:01 +02:00
Stefan Roese
b7c3e93105 Merge with /home/stefan/git/u-boot/denx-440-exceptions 2007-06-15 11:20:13 +02:00
Grzegorz Bernacki
efa35cf12d ppc4xx: Clean up 440 exceptions handling
- Introduced dedicated switches for building 440 and 405 images required
  for 440-specific machine instructions like 'rfmci' etc.

- Exception vectors moved to the proper location (_start moved away from
  the critical exception handler space, which it occupied)

- CriticalInput now serviced (with default handler)

- MachineCheck properly serviced (added a dedicated handler and return
  subroutine)

- Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
  unhandled and those not relevant for 4xx were eliminated)

- Eliminated Linux leftovers, removed dead code

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-15 11:19:28 +02:00
Stefan Roese
b765ffb773 [ppc4xx] Add initial lwmon5 board support
This patch adds initial support for the Liebherr lwmon5 board euqipped
with an AMCC 440EPx PowerPC.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-06-15 08:18:01 +02:00
Stefan Roese
61936667e8 ppc4xx: Add mtcpr/mfcpr access macros
Signed-off-by: Stefan Roese <sr@denx.de>
2007-05-11 12:01:49 +02:00
Stefan Roese
90e6f41cf0 ppc4xx: Add output for bootrom location to 405EZ ports
Now 405EZ ports also show upon bootup from which boot device
they are configured to boot:

U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05)

CPU:   AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz)
       Bootstrap Option E - Boot ROM Location EBC (32 bits)
       16 kB I-Cache 16 kB D-Cache
Board: Acadia - AMCC PPC405EZ Evaluation Board

Signed-off-by: Stefan Roese <sr@denx.de>
2007-04-18 12:05:59 +02:00
Stefan Roese
e50b791b3f Merge with /home/stefan/git/u-boot/acadia 2007-03-24 15:59:23 +01:00
Stefan Roese
0d974d5297 [PATCH] Add 4xx GPIO functions
This patch adds some 4xx GPIO functions. It also moves some of the
common code and defines into a common 4xx GPIO header file.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-24 15:57:09 +01:00
Wolfgang Denk
35ded29fd9 Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx 2007-03-08 11:38:58 +01:00
Stefan Roese
df29449747 ppc4xx: Update 440SP/440SPe DDR SPD setup code to support 440SP
Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-08 10:06:09 +01:00
Stefan Roese
07b7b0037a [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setup
As provided by the AMCC applications team, this patch optimizes the
DDR2 setup for 166MHz bus speed. The values provided are also save
to use on a "normal" 133MHz PLB bus system. Only the refresh counter
setup has to be adjusted as done in this patch.

For this the NAND booting version had to include the "speed.c" file
from the cpu/ppc4xx directory. With this addition the NAND SPL image
will just fit into the 4kbytes of program space. gcc version 4.x as
provided with ELDK 4.x is needed to generate this optimized code.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-06 07:47:04 +01:00
Stefan Roese
ba58e4c9a9 [PATCH] Update AMCC Katmai 440SPe eval board support
This patch updates the recently added Katmai board support. The biggest
change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2
driver.

Please note, that still some problems are left with some memory
configurations. See the driver for more details.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-03-01 21:11:36 +01:00
Stefan Roese
4745acaa1a [PATCH] Add support for the AMCC Katmai (440SPe) eval board
Signed-off-by: Stefan Roese <sr@denx.de>
2007-02-20 10:57:08 +01:00
Stefan Roese
a78bc443ae [PATCH] Clear PLB4A0_ACR[WRP] on Sequoia (440EPx)
This fix will make the MAL burst disabling patch for the Linux
EMAC driver obsolete.

Signed-off-by: Stefan Roese <sr@denx.de>
2007-01-05 10:40:36 +01:00
Stefan Roese
4e26f1074c [PATCH] include/ppc440.h minor error affecting interrupts
Fixed include/ppc440.c for UIC address Bug

Corrects bug affecting the addresses for the universal interrupt
controller UIC2 and UIC3 on the PPC440 Epx, GRx, and SPE chips.

Signed-off-by: Jeff Mann <mannj@embeddedplanet.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2006-11-29 12:03:57 +01:00
Stefan Roese
dfc8a9ee00 Merge with /home/stefan/git/u-boot/denx 2006-11-10 07:48:47 +01:00
Wolfgang Denk
ac611700e5 Fix comments in include/ppc440.h
Patch by Martin Hicks, 16 Jun 2006
2006-09-20 23:47:49 +02:00