This patch fixes a typo in the routine to calculate the cs offset
based upon the contents of the SDRC cs_cfg register. This function
mistakenly shifts the CS1STARTLOW field 17 bits right instead of
17 bits left.
This hasn't been an issue to date because all OMAP3 boards currently
are configured to have zeros in this field.
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Steve Sakoman <steve.sakoman@linaro.org>
Generalized misuse of ble within relocation and bss
initialization loops caused one iteration too many.
Instead of ble ('branch if lower or equal'), use
blo ('branch if lower').
While we're at it, fix all 'addreee' typos.
Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
The OMAP3 cpu directory contains a syslib file with some utilities
that can be shared by all targets using arm cortexa8 processors,
not only OMAP.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Calculate the SDRAM size from DMM configuration registers instead of using
hard-coded values. This gives correct values for all different boards.
It's assumed that DMM sections do not overlap memory areas.
Signed-off-by: Aneesh V <aneesh@ti.com>
Tested-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Change the implementation for ARM V7 to relocate the code to an
arbitrary address in RAM.
Adapt the Beagle board (Cortex A8) to test the changes.
Portions of this work were supported by funding from
the CE Linux Forum.
Signed-off-by: Heiko Schocher <hs@denx.de>
Add data cache support for ARM V7 systems. Used cache flush
functions from linux:arch/arm/mm/cache-v7.S developed from
Catalin Marinas.
Enable "cache" command on Beagle board and test performance.
Test 1: Loading 127 MB of data from NAND flash into RAM:
Instr. Cache off on on
Data Cache off off on
--------------------------------------------------
Beagle (Cortex A8) 116s 106s 30.3s = x 3.8
Test 2: uncompressing a gzipped image from RAM to RAM
(size compressed: 6.5 MiB, uncompressed: 35 MiB):
Instr. Cache off on on
Data Cache off off on
--------------------------------------------------
Beagle (Cortex A8) 1.84s 1.64s 0.12s = x 15.3
Portions of this work were supported by funding from
the CE Linux Forum.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Ben Gardiner<bengardiner@nanometrics.ca>
Upcoming Beagle and Overo revisions use POP memory with 256MB or 512MB
per bank. This patches uses the SDRC settings from x-load or the config
header to set up timing properly.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Using the reset command on OMAP36XX/37XX and OMAP4 caused a hang. This
patch uses the reset bit appropriate for each CPU architecture.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The workarounds for errata 621766 and 725233 should only be applied
on affected Cortex-A8 revisions. Recent chips use r3px cores where
these have been fixed.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This function consists entirely of inline asm statements, so writing
it directly in a .S file is simpler. Additionally, the inline asm is
not safe as is, since registers are not guaranteed to be preserved
between asm() statements.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
On OMAP34xx ES1.0, the L2 enable bit can only be set in secure mode,
so an SMC call to the ROM monitor is required. On later versions,
and on newer devices, this bit is banked and we can set it directly.
The code checked only the ES revision of the chip, and hence incorrectly
used the ROM call on ES1.0 versions of other devices.
This patch adds a check for chip family as well as revision, and also
removes some code duplication between the enable and disable functions.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch configures clocks properly when a 36XX/37XX
processor is detected.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
TI has added new processors to the OMAP3 family. This patch enhances
the code in sysinfo.c to detect which family member is present.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The functions in syslib.c can be shared, so this patch moves it from
cpu/omap3 to cpu/omap-common
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Because of peripheral devices can select clock sources,
separate the peripheral clocks. (pwm, uart and so on)
It just return the pclk at s5pc1xx SoC,
but s5pc210 SoC must be calculated by own clock register setting.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Because of these are common files around s5p Socs, rename from s5pc1xx to s5p.
And getting cpu_id is SoC specific, so move to SoC's header file.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
This patch adds basic support for s5pc210.
s5p-common will be used by all of s5p SoCs.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
This patch is intended to prepare the other S5P SoC. (s5pc210)
If use SoC specific defines then can't share with other SoC.
So, make the accessor functions for access the base address by common way.
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
get_timer_masked() should return current timestamp,
not current ticks from hardware register.
Tested on one custom board with NAND flash.
Without this patch, NAND write always TIMEOUT
because get_timer(0) return a big value.
This patch applies for u-boot-2010.06
Signed-off-by: Li Haibo <hbli@sinocastel.com>
The OMAP4 x-load code sets gptimer1 clock source to 32Khz. This isn't
acceptable for udelay. This patch changes from gptimer1 to gptimer2,
which uses sys_clk at 38.4 Mhz.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Add functional multiplexing support for OMAP4 pads.
Configure all the pads for the OMAP4430 SDP
and OMAP4 Panda boards
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds a gpmc_init function for OMAP4 and adds calls to
gpmc_init for existing OMAP4 boards: panda and sdp4430
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This patch adds minimum support for OMAP4. Code which can be shared
between OMAP3 and OMAP4 is placed in arch/arm/cpu/armv7/omap-common
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
The purpose of this patch is to prepare for adding the OMAP4 architecture, which is Cortex A9
Cortex A8 and A9 both belong to the armv7 architecture, hence the name change.
The two architectures are similar enough that substantial code can be shared.
Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Steve Sakoman
Heiko Schocher
Albert Aribaud
Stefano Babic
Wolfgang Denk
Aneesh V
Mans Rullgard
Minkyu Kang
Li Haibo