Commit graph

6803 commits

Author SHA1 Message Date
Kumar Gala
0151cbaccf 85xx: Enable 64-bit PCI resources on all Freescale boards
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
2008-10-24 17:33:06 -05:00
Kumar Gala
30e76d5e3b pci: Allow for PCI addresses to be 64-bit
PCI bus is inherently 64-bit.  While not all system require access to
the full 64-bit PCI address range some do.  This allows those systems
to enable the full PCI address width via CONFIG_SYS_PCI_64BIT.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
Acked-by: Wolfgang Denk <wd@denx.de>
2008-10-24 17:32:49 -05:00
Dave Liu
ae5f943ba8 85xx: Fix the incorrect register used for DDR erratum1
The 8572 DDR erratum1:
DDR controller may enter an illegal state when operating
in 32-bit bus mode with 4-beat bursts.

Description:
When operating with a 32-bit bus, it is recommended that
DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used.
This forces the DDR controller to use 4-beat bursts when
communicating to the DRAMs. However, an issue exists that
could lead to data corruption when the DDR controller is
in 32-bit bus mode while using 4-beat bursts.

Projected Impact:
If the DDR controller is operating in 32-bit bus mode with
4-beat bursts, then the controller may enter into a bad state.
All subsequent reads from memory is corrupted.
Four-beat bursts with a 32-bit bus only is used with DDR2 memories.
Therefore, this erratum does not affect DDR3 mode.

Work Arounds:
To work around this issue, software must set DEBUG_1[31] in
DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1
and CCSRBAR offset + 0x6f00 for DDR_2).

Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2
as condition, but it should be DDR_SDRAM_CFG register.

Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-10-24 17:29:37 -05:00
Dave Liu
d5b693090e 85xx: remove unused config definition
Signed-off-by: Dave Liu <daveliu@freescale.com>
2008-10-24 16:18:33 -05:00
Kumar Gala
0f060c3bf8 85xx: Add basic e500mc core support
Introduce CONFIG_E500MC to deal with the minor differences between
e500v2 and e500mc.

* Certain fields of HID0/1 don't exist anymore on e500mc
* Cache line size is 64-bytes on e500mc
* reset value of PIR is different

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-24 15:10:47 -05:00
Kumar Gala
a38a5b6edd 85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic number
Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle
e500mc's 64-byte cacheline properly when it gets added.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2008-10-24 15:10:23 -05:00
Georg Schardt
5deb8022c3 ppc4xx: New board avnet fx12 minimodul
This patch adds support for the avnet fx12 minimodul.
It needs the "ppc4xx: Generic architecture for xilinx ppc405"
patch from Ricardo.

Signed-off-by: Georg Schardt <schardt@team-ctech.de>
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-24 17:34:26 +02:00
Ricardo Ribalda Delgado
1f4d53260e ppc4xx: Generic architecture for xilinx ppc405(v3)
As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx
ppc440 boards, this patch presents a common architecture for all the
xilinx ppc405 boards.

Any custom xilinx ppc405 board can be added very easily with no code
duplicity.

This patch also adds a simple generic board, that can be used on almost
any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h

This patch is prepared to work with the latest version of EDK (10.1)

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-24 17:26:09 +02:00
Stefan Roese
485c00a57f ppc4xx: Disable DDR2 autocalibration on Kilauea for now
Since the new autocalibration still has some problems on some Kilauea
boards with 200MHz DDR2 frequency we disable the autocalibration and
use the hardcoded values as done before. This seems to work reliably
on all known DDR2 frequencies.

After the autocalibration issue is fixed we will enable it again.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-24 17:25:13 +02:00
Mike Frysinger
f177f4250c Blackfin: fix up UART status bit handling
Some Blackfin UARTs are read-to-clear while others are write-to-clear.
This can cause problems when we poll the LSR and then later try and handle
any errors detected.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:51 -04:00
Mike Frysinger
ae0910298f Blackfin: bf561-ezkit: drop redundant code
Common Blackfin code already announces CPU information.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:51 -04:00
Mike Frysinger
e2eea98bff Blackfin: bf561-ezkit: drop pointless USB code
The USB/LAN register settings are not actually used/needed in order to
drive things from U-Boot, so drop the code.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:51 -04:00
Mike Frysinger
c23bff63fb Blackfin: linker scripts: force start.o and set initcode boundaries
Make sure that the start.o object is always the first object in our linker
script regardless of configuration settings, and add some linker symbols
so the ldr utility can properly locate the initcode when generating a LDR.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:51 -04:00
Mike Frysinger
bd33e5c613 Blackfin: small cpu init optimization while setting interrupt mask
Use the sti instruction to set the initial interrupt mask rather than
banging on the core IMASK MMR to save both space and time.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:51 -04:00
Mike Frysinger
960922291c Blackfin: set initial stack correctly according to Blackfin ABI
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:51 -04:00
Mike Frysinger
25cd33d82e Blackfin: make baud calculation more accurate
We should use the algorithm in the Linux kernel so that the UART divisor
calculation is more accurate.  It also fixes problems on some picky UARTs
that have sampling anomalies.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:51 -04:00
Mike Frysinger
0ba1da116e Blackfin: decode hwerrcause/excause when crashing
Having to decode hwerrcause/excause values is a pain, so automate it.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
2de95bb20c Blackfin: fix register dump messages
Make sure we report RETI/IPEND correctly.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
7133999e6f Blackfin: don't bother displaying reboot msg when crashing
The hang function already tells you to reboot, so no point in showing it
twice.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
70c4c032ea Blackfin: enable support for nested interrupts
During cpu init, make sure we initialize the CEC properly so that
interrupts can fire and be handled while U-Boot is running.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
39782727e1 Blackfin: init NAND before relocating env
If booting out of NAND, we need to make sure we initialize it properly
before attempting to relocate the environment.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
0f9a881941 Blackfin: check cache bits, not cplb bits
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
2c1ea9e370 Blackfin: drop unused cache flush code
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
50f0d21191 Blackfin: unify cache handling code
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
3c87989834 Blackfin: only initialize the RTC when actually used
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
621e579b81 Blackfin: fix SWRST register definition
The SWRST register is a 16bit, not 32bit, register.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
06121c4e2d Blackfin: build with -fomit-frame-pointer
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
adbfeeb7b3 Blackfin: document some of the blackfin directories
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
e4337968e4 Blackfin: only enable hardware error irq by default
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
2b66f08f25 Blackfin: punt old unused mem_init.h header
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:50 -04:00
Mike Frysinger
bcc121a016 Blackfin: delete unused page_descriptor_table_size define
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:49 -04:00
Mike Frysinger
30fb9d24ae Blackfin: fix typo in boot mode comment and add NAND define
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:49 -04:00
Ben Maan
2e5cbe5461 Blackfin: fix port mux defines for BF54x
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:49 -04:00
Mike Frysinger
0656ef2ba2 Blackfin: update anomaly lists
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:49 -04:00
Mike Frysinger
50ca954028 Blackfin: unify DSPID/DBGSTAT MMR definitions
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
2008-10-23 05:03:49 -04:00
Wolfgang Denk
d9d8c7c696 Fix strmhz(): avoid printing negative fractions
Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-22 08:52:19 +02:00
Richard Retanubun
4a7f6b750d mpc83xx: Removed #ifdef CONFIG_MPC834X dependency on upmconfig function
This is done to allow other 83XX based platforms which also have UPM
(e.g. 8360) to configure and use their UPM in u-boot.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:41:04 -05:00
Anton Vorontsov
3bf1be3c0c mpc83xx: add support for switching between USB Host/Function for MPC837XEMDS
With this patch u-boot can fixup the dr_mode and phy_type properties
for the Dual-Role USB controller.

While at it, also remove #ifdefs around includes, they are not needed.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:40:01 -05:00
Anton Vorontsov
b3379f3fd1 mpc83xx: add ELBC NAND support for the MPC837XEMDS boards
Though NAND chip is replaceable on the MPC837XE-MDS boards, the
current settings don't work with the default chip on the board.
Nevertheless Freescale's U-Boot sets the option register correctly,
so I just dumped the register from the working u-boot. My guess is
that the old settings were applicable for some pilot boards, not
found in the production.

This patch also enables FSL ELBC driver so that we could access
the NAND storage in the u-boot.

The NAND support costs about 45KB, so the u-boot no longer fits
into two 128KB NOR flash sectors, thus we also have to adjust
environment location: add another 128KB to the monitor length.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>

It is due to hardware design and logic defect, that is the
I/O[0:7] of NAND chip is connected to LAD[7:0], so when
the NAND chip connected to nLCS3,  you have to set up the
OR3[BCTLD] = '1' for normal operation, otherwise it will have
bus contention due to the pin 48/25 of U60 is enabled.

Setup the OR3[BCTLD] = '1' , that meaning the LBCTL is not
asserted upon access to the NAND chip, keep the default state.

Acked-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:17 -05:00
Anton Vorontsov
00f7bbae92 mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boards
The MPC837xE-MDS board's CPLD can auto-detect if the board is on the PIB,
standalone or acting as a PCI agent. User's Guide says:

- When the CPLD recognizes its location on the PIB it automatically
  configures RCW to the PCI Host.
- If the CPLD fails to recognize its location then it is automatically
  configured as an Agent and the PCI is configured to an external arbiter.

This sounds good. Though in the standalone setup the CPLD sets PCI_HOST
flag (it's ok, we can't act as PCI agents since we receive CLKIN, not
PCICLK), but the CPLD doesn't set the ARBITER_ENABLE flag, and without
any arbiter bad things will happen (here the board hangs during any config
space reads).

In this situation we must disable the PCI. And in case of anybody really
want to use an external arbiter, we provide "pci_external_aribter"
environment variable.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:14 -05:00
Anton Vorontsov
1da83a63d8 mpc83xx: add SGMII riser module support for the MPC8378E-MDS boards
This involves configuring the SerDes and fixing up the flags and
PHY addresses for the TSECs.

For Linux we also fix up the device tree.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:08 -05:00
Anton Vorontsov
e6d9c8916d mpc83xx: add TSECs' HRCWH masks for MPC837x processors
We'll use these masks to parse TSEC modes out of HRCWH.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:05 -05:00
Anton Vorontsov
6f9cc6608b mpc83xx: serdes: add forgotten shifts for rfcks
The rfcks should be shifted by 28 bits left. We didn't notice the bug
because we were using only 100MHz clocks (for which rfcks == 0).

Though, for SGMII we'll need 125MHz clocks.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:34:01 -05:00
Anton Vorontsov
55c531984d mpc83xx: fix serdes setup for the MPC8378E boards
MPC837xE specs says that SerDes1 has:

— Two lanes running x1 SGMII at 1.25 Gbps;
— Two lanes running x1 SATA at 1.5 or 3.0 Gbps.

And for SerDes2:

— Two lanes running x1 PCI Express at 2.5 Gbps;
— One lane running x2 PCI Express at 2.5 Gbps;
— Two lanes running x1 SATA at 1.5 or 3.0 Gbps.

The spec also explicitly states that PEX options are not valid for
the SD1.

Nevertheless MPC8378 RDB and MDS boards configure the SD1 for PEX,
which is wrong to do.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:33:25 -05:00
Anton Vorontsov
5c2ff323a9 mpc83xx: mpc8360emds: rework LBC SDRAM setup
Currently 64M of LBC SDRAM are mapped at 0xF0000000 which makes
it difficult to use (b/c then the memory is discontinuous and
there is quite big memory hole between the DDR/SDRAM regions).

This patch reworks LBC SDRAM setup so that now we dynamically
place the LBC SDRAM near the DDR (or at 0x0 if there isn't any
DDR memory).

With this patch we're able to:

- Boot without external DDR memory;
- Use most "DDR + SDRAM" setups without need to support for
  sparse/discontinuous memory model in the software.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
2008-10-21 18:31:07 -05:00
Wolfgang Denk
def0819e92 FDT: don't use private kernel header files
On some systems (for example Fedora Core 4) U-Boot builds with the
following wanrings only:

...
In file included from /home/wd/git/u-boot/include/libfdt_env.h:33,
                 from fdt.c:51:
		 /usr/include/asm/byteorder.h:6:2: warning: #warning using private kernel header; include <endian.h> instead!

This patch fixes this problem.

Signed-off-by: Wolfgang Denk <wd@denx.de>
2008-10-21 21:35:44 +02:00
Wolfgang Denk
06c2942218 Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx 2008-10-21 21:19:35 +02:00
Stefan Roese
f4d14c5550 ppc4xx: Add 1.0 & 1.066 GHz to canyonlands bootstrap command for PLL setup
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:35:02 +02:00
Stefan Roese
43cbce69d4 ppc4xx: Correctly setup ranges property in ebc node
Previously only the NOR flash mapping was written into the ranges
property of the ebc node. This patch now writes all enabled chip
select areas into the ranges property.

Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:35:02 +02:00
Dirk Eibach
d7b26d5832 ppc4xx: Add GDSys neo 405EP board support
Signed-off-by: Dirk Eibach <eibach@gdsys.de>
Signed-off-by: Stefan Roese <sr@denx.de>
2008-10-21 17:35:02 +02:00